1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _DEV_IC_Z8530_H_
30#define _DEV_IC_Z8530_H_
31
32/*
33 * legacy: SUN compatible
34 * escc: Macintosh
35 * legacy escc
36 * Channel B control: 0 0
37 * Channel B data: 1 1
38 * Channel A control: 2 16
39 * Channel A data: 3 17
40 */
41
42#define REG_CTRL 0
43#define REG_DATA 1
44
45/* Write registers. */
46#define WR_CR 0 /* Command Register. */
47#define WR_IDT 1 /* Interrupt and Data Transfer Mode. */
48#define WR_IV 2 /* Interrupt Vector (shared). */
49#define WR_RPC 3 /* Receive Parameters and Control. */
50#define WR_MPM 4 /* Miscellaneous Parameters and Modes. */
51#define WR_TPC 5 /* Transmit Parameters and Control. */
52#define WR_SCAF 6 /* Sync Character or (SDLC) Address Field. */
53#define WR_SCF 7 /* Sync Character or (SDCL) Flag. */
54#define WR_EFC 7 /* Extended Feature and FIFO Control. */
55#define WR_TB 8 /* Transmit Buffer. */
56#define WR_MIC 9 /* Master Interrupt Control (shared). */
57#define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */
58#define WR_CMC 11 /* Clock Mode Control. */
59#define WR_TCL 12 /* BRG Time Constant Low. */
60#define WR_TCH 13 /* BRG Time Constant High. */
61#define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */
62#define WR_IC 15 /* Interrupt Control. */
63
64/* Read registers. */
65#define RR_BES 0 /* Buffer and External Status. */
66#define RR_SRC 1 /* Special Receive Condition. */
67#define RR_IV 2 /* Interrupt Vector. */
68#define RR_IP 3 /* Interrupt Pending (ch A only). */
69#define RR_MPM 4 /* Miscellaneous Parameters and Modes. */
70#define RR_TPC 5 /* Transmit Parameters and Control. */
71#define RR_BCL 6 /* Byte Count Low. */
72#define RR_BCH 7 /* Byte Count High. */
73#define RR_RB 8 /* Receive Buffer. */
74#define RR_RPC 9 /* Receive Parameters and Control. */
75#define RR_MSB 10 /* Miscellaneous Status Bits. */
76#define RR_MCB1 11 /* Miscellaneous Control Bits (part 1). */
77#define RR_TCL 12 /* BRG Time Constant Low. */
78#define RR_TCH 13 /* BRG Time Constant High. */
79#define RR_EFC 14 /* Extended Feature and FIFO Control. */
80#define RR_IC 15 /* Interrupt Control. */
81
82/* Buffer and External Status (RR0). */
83#define BES_BRK 0x80 /* Break (Abort). */
84#define BES_TXU 0x40 /* Tx Underrun (EOM). */
85#define BES_CTS 0x20 /* CTS. */
86#define BES_SYNC 0x10 /* Sync. */
87#define BES_DCD 0x08 /* DCD. */
88#define BES_TXE 0x04 /* Tx Empty. */
89#define BES_ZC 0x02 /* Zero Count. */
90#define BES_RXA 0x01 /* Rx Available. */
91
92/* Clock Mode Control (WR11). */
93#define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */
94#define CMC_RC_DPLL 0x60 /* Rx Clock from DPLL. */
95#define CMC_RC_BRG 0x40 /* Rx Clock from BRG. */
96#define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */
97#define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */
98#define CMC_TC_DPLL 0x18 /* Tx Clock from DPLL */
99#define CMC_TC_BRG 0x10 /* Tx Clock from BRG */
100#define CMC_TC_TRXC 0x08 /* Tx Clock from -TRxC. */
101#define CMC_TC_RTXC 0x00 /* Tx Clock from -RTxC. */
102#define CMC_TRXC_OUT 0x04 /* -TRxC is output. */
103#define CMC_TRXC_DPLL 0x03 /* -TRxC from DPLL */
104#define CMC_TRXC_BRG 0x02 /* -TRxC from BRG */
105#define CMC_TRXC_XMIT 0x01 /* -TRxC from Tx clock. */
106#define CMC_TRXC_XTAL 0x00 /* -TRxC from XTAL. */
107
108/* Command Register (WR0). */
109#define CR_RSTTXU 0xc0 /* Reset Tx. Underrun/EOM. */
110#define CR_RSTTXCRC 0x80 /* Reset Tx. CRC. */
111#define CR_RSTRXCRC 0x40 /* Reset Rx. CRC. */
112#define CR_RSTIUS 0x38 /* Reset Int. Under Service. */
113#define CR_RSTERR 0x30 /* Error Reset. */
114#define CR_RSTTXI 0x28 /* Reset Tx. Int. */
115#define CR_ENARXI 0x20 /* Enable Rx. Int. */
116#define CR_ABORT 0x18 /* Send Abort. */
117#define CR_RSTXSI 0x10 /* Reset Ext/Status Int. */
118
119/* Extended Feature and FIFO Control (WR7 prime). */
120#define EFC_ERE 0x40 /* Extended Read Enable. */
121#define EFC_FE 0x20 /* Transmit FIFO Empty. */
122#define EFC_RQT 0x10 /* Request Timing. */
123#define EFC_FHF 0x08 /* Receive FIFO Half Full. */
124#define EFC_RTS 0x04 /* Auto RTS Deactivation. */
125#define EFC_EOM 0x02 /* Auto EOM Reset. */
126#define EFC_FLAG 0x01 /* Auto SDLC Flag on Tx. */
127
128/* Interrupt Control (WR15). */
129#define IC_BRK 0x80 /* Break (Abort) IE. */
130#define IC_TXU 0x40 /* Tx Underrun IE. */
131#define IC_CTS 0x20 /* CTS IE. */
132#define IC_SYNC 0x10 /* Sync IE. */
133#define IC_DCD 0x08 /* DCD IE. */
134#define IC_FIFO 0x04 /* SDLC FIFO Enable. */
135#define IC_ZC 0x02 /* Zero Count IE. */
136#define IC_EF 0x01 /* Extended Feature Enable. */
137
138/* Interrupt and Data Transfer Mode (WR1). */
139#define IDT_WRE 0x80 /* Wait/DMA Request Enable. */
140#define IDT_REQ 0x40 /* DMA Request. */
141#define IDT_WRR 0x20 /* Wait/DMA Reuest on Receive. */
142#define IDT_RISC 0x18 /* Rx Int. on Special Condition Only. */
143#define IDT_RIA 0x10 /* Rx Int. on All Characters. */
144#define IDT_RIF 0x08 /* Rx Int. on First Character. */
145#define IDT_PSC 0x04 /* Parity is Special Condition. */
146#define IDT_TIE 0x02 /* Tx Int. Enable. */
147#define IDT_XIE 0x01 /* Ext. Int. Enable. */
148
149/* Interrupt Pending (RR3). */
150#define IP_RIA 0x20 /* Rx. Int. ch. A. */
151#define IP_TIA 0x10 /* Tx. Int. ch. A. */
152#define IP_SIA 0x08 /* Ext/Status Int. ch. A. */
153#define IP_RIB 0x04 /* Rx. Int. ch. B. */
154#define IP_TIB 0x02 /* Tx. Int. ch. B. */
155#define IP_SIB 0x01 /* Ext/Status Int. ch. B. */
156
157/* Interrupt Vector Status Low (RR2). */
158#define IV_SCA 0x0e /* Special Condition ch. A. */
159#define IV_RAA 0x0c /* Receive Available ch. A. */
160#define IV_XSA 0x0a /* External/Status Change ch. A. */
161#define IV_TEA 0x08 /* Transmitter Empty ch. A. */
162#define IV_SCB 0x06 /* Special Condition ch. B. */
163#define IV_RAB 0x04 /* Receive Available ch. B. */
164#define IV_XSB 0x02 /* External/Status Change ch. B. */
165#define IV_TEB 0x00 /* Transmitter Empty ch. B. */
166
167/* Miscellaneous Control Bits part 1 (WR10). */
168#define MCB1_CRC1 0x80 /* CRC presets to 1. */
169#define MCB1_FM0 0x60 /* FM0 Encoding. */
170#define MCB1_FM1 0x40 /* FM1 Encoding. */
171#define MCB1_NRZI 0x20 /* NRZI Encoding. */
172#define MCB1_NRZ 0x00 /* NRZ Encoding. */
173#define MCB1_AOP 0x10 /* Active On Poll. */
174#define MCB1_MI 0x08 /* Mark Idle. */
175#define MCB1_AOU 0x04 /* Abort On Underrun. */
176#define MCB1_LM 0x02 /* Loop Mode. */
177#define MCB1_SIX 0x01 /* 6 or 12 bit SYNC. */
178
179/* Miscellaneous Control Bits part 2 (WR14). */
180#define MCB2_NRZI 0xe0 /* DPLL - NRZI mode. */
181#define MCB2_FM 0xc0 /* DPLL - FM mode. */
182#define MCB2_RTXC 0xa0 /* DPLL - Clock from -RTxC. */
183#define MCB2_BRG 0x80 /* DPLL - Clock from BRG. */
184#define MCB2_OFF 0x60 /* DPLL - Disable. */
185#define MCB2_RMC 0x40 /* DPLL - Reset Missing Clock. */
186#define MCB2_ESM 0x20 /* DPLL - Enter Search Mode. */
187#define MCB2_LL 0x10 /* Local Loopback. */
188#define MCB2_AE 0x08 /* Auto Echo. */
189#define MCB2_REQ 0x04 /* Request Function. */
190#define MCB2_PCLK 0x02 /* BRG source is PCLK. */
191#define MCB2_BRGE 0x01 /* BRG enable. */
192
193/* Master Interrupt Control (WR9). */
194#define MIC_FHR 0xc0 /* Force Hardware Reset. */
195#define MIC_CRA 0x80 /* Channel Reset A. */
196#define MIC_CRB 0x40 /* Channel Reset B. */
197#define MIC_SIE 0x20 /* Software INTACK Enable. */
198#define MIC_SH 0x10 /* Status High. */
199#define MIC_MIE 0x08 /* Master Interrupt Enable. */
200#define MIC_DLC 0x04 /* Disable Lower Chain. */
201#define MIC_NV 0x02 /* No Vector. */
202#define MIC_VIS 0x01 /* Vector Includes Status. */
203
204/* Transmit/Receive Miscellaneous Parameters and Modes (WR4). */
205#define MPM_CM64 0xc0 /* X64 Clock Mode. */
206#define MPM_CM32 0x80 /* X32 Clock Mode. */
207#define MPM_CM16 0x40 /* X16 Clock Mode. */
208#define MPM_CM1 0x00 /* X1 Clock Mode. */
209#define MPM_EXT 0x30 /* External Sync Mode. */
210#define MPM_SDLC 0x20 /* SDLC mode. */
211#define MPM_BI 0x10 /* 16-bit Sync (bi-sync). */
212#define MPM_MONO 0x00 /* 8-bit Sync (mono-sync). */
213#define MPM_SB2 0x0c /* Async mode: 2 stopbits. */
214#define MPM_SB15 0x08 /* Async mode: 1.5 stopbits. */
215#define MPM_SB1 0x04 /* Async mode: 1 stopbit. */
216#define MPM_SYNC 0x00 /* Sync Mode Enable. */
217#define MPM_EVEN 0x02 /* Async mode: even parity. */
218#define MPM_PE 0x01 /* Async mode: parity enable. */
219
220/* Receive Parameters and Control (WR3). */
221#define RPC_RB8 0xc0 /* 8 databits. */
222#define RPC_RB6 0x80 /* 6 databits. */
223#define RPC_RB7 0x40 /* 7 databits. */
224#define RPC_RB5 0x00 /* 5 databits. */
225#define RPC_AE 0x20 /* Auto Enable. */
226#define RPC_EHM 0x10 /* Enter Hunt Mode. */
227#define RPC_CRC 0x08 /* CRC Enable. */
228#define RPC_ASM 0x04 /* Address Search Mode. */
229#define RPC_LI 0x02 /* SYNC Character Load Inhibit */
230#define RPC_RXE 0x01 /* Receiver Enable */
231
232/* Special Receive Condition (RR1). */
233#define SRC_EOF 0x80 /* End Of Frame. */
234#define SRC_FE 0x40 /* Framing Error. */
235#define SRC_OVR 0x20 /* Rx. Overrun. */
236#define SRC_PE 0x10 /* Parity Error. */
237#define SRC_RC0 0x08 /* Residue Code 0. */
238#define SRC_RC1 0x04 /* Residue Code 1. */
239#define SRC_RC2 0x02 /* Residue Code 2. */
240#define SRC_AS 0x01 /* All Sent. */
241
242/* Transmit Parameter and Control (WR5). */
243#define TPC_DTR 0x80 /* DTR. */
244#define TPC_TB8 0x60 /* 8 databits. */
245#define TPC_TB6 0x40 /* 6 databits. */
246#define TPC_TB7 0x20 /* 7 databits. */
247#define TPC_TB5 0x00 /* 5 or fewer databits. */
248#define TPC_BRK 0x10 /* Send break. */
249#define TPC_TXE 0x08 /* Transmitter Enable. */
250#define TPC_CRC16 0x04 /* CRC16. */
251#define TPC_RTS 0x02 /* RTS. */
252#define TPC_CRC 0x01 /* CRC Enable. */
253
254#endif /* _DEV_IC_Z8530_H_ */