1/*-
2 * Copyright (c) 2018, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#ifndef _DEV_MLX5_MLX5IO_H_
27#define _DEV_MLX5_MLX5IO_H_
28
29#include <sys/ioccom.h>
30
31struct mlx5_fwdump_reg {
32 uint32_t addr;
33 uint32_t val;
34};
35
36struct mlx5_tool_addr {
37 uint32_t domain;
38 uint8_t bus;
39 uint8_t slot;
40 uint8_t func;
41};
42
43struct mlx5_fwdump_get {
44 struct mlx5_tool_addr devaddr;
45 struct mlx5_fwdump_reg *buf;
46 size_t reg_cnt;
47 size_t reg_filled; /* out */
48};
49
50struct mlx5_fw_update {
51 struct mlx5_tool_addr devaddr;
52 void *img_fw_data;
53 size_t img_fw_data_len;
54};
55
56struct mlx5_eeprom_get {
57 struct mlx5_tool_addr devaddr;
58 uint32_t *eeprom_info_buf;
59 uint8_t eeprom_info_page_valid;
60 size_t eeprom_info_out_len;
61};
62
63#define MLX5_FWDUMP_GET _IOWR('m', 1, struct mlx5_fwdump_get)
64#define MLX5_FWDUMP_RESET _IOW('m', 2, struct mlx5_tool_addr)
65#define MLX5_FWDUMP_FORCE _IOW('m', 3, struct mlx5_tool_addr)
66#define MLX5_FW_UPDATE _IOW('m', 4, struct mlx5_fw_update)
67#define MLX5_FW_RESET _IOW('m', 5, struct mlx5_tool_addr)
68#define MLX5_EEPROM_GET _IOWR('m', 6, struct mlx5_eeprom_get)
69
70#ifndef _KERNEL
71#define MLX5_DEV_PATH _PATH_DEV"mlx5ctl"
72#endif
73
74enum mlx5_fpga_id {
75 MLX5_FPGA_NEWTON = 0,
76 MLX5_FPGA_EDISON = 1,
77 MLX5_FPGA_MORSE = 2,
78 MLX5_FPGA_MORSEQ = 3,
79};
80
81enum mlx5_fpga_image {
82 MLX5_FPGA_IMAGE_USER = 0,
83 MLX5_FPGA_IMAGE_FACTORY = 1,
84 MLX5_FPGA_IMAGE_FACTORY_FAILOVER = 2,
85 MLX5_FPGA_IMAGE_RESET = 17,
86 MLX5_FPGA_IMAGE_RELOAD = 18,
87};
88
89enum mlx5_fpga_status {
90 MLX5_FPGA_STATUS_SUCCESS = 0,
91 MLX5_FPGA_STATUS_FAILURE = 1,
92 MLX5_FPGA_STATUS_IN_PROGRESS = 2,
93 MLX5_FPGA_STATUS_DISCONNECTED = 3,
94};
95
96struct mlx5_fpga_query {
97 enum mlx5_fpga_image admin_image;
98 enum mlx5_fpga_image oper_image;
99 enum mlx5_fpga_status image_status;
100};
101
102enum mlx5_fpga_tee {
103 MLX5_FPGA_TEE_DISABLE = 0,
104 MLX5_FPGA_TEE_GENERATE_EVENT = 1,
105 MLX5_FPGA_TEE_GENERATE_SINGLE_EVENT = 2,
106};
107
108enum mlx5_fpga_connect {
109 MLX5_FPGA_CONNECT_QUERY = 0,
110 MLX5_FPGA_CONNECT_DISCONNECT = 0x9,
111 MLX5_FPGA_CONNECT_CONNECT = 0xA,
112};
113
114/**
115 * enum mlx5_fpga_access_type - Enumerated the different methods possible for
116 * accessing the device memory address space
117 */
118enum mlx5_fpga_access_type {
119 /** Use the slow CX-FPGA I2C bus*/
120 MLX5_FPGA_ACCESS_TYPE_I2C = 0x0,
121 /** Use the fast 'shell QP' */
122 MLX5_FPGA_ACCESS_TYPE_RDMA,
123 /** Use the fastest available method */
124 MLX5_FPGA_ACCESS_TYPE_DONTCARE,
125 MLX5_FPGA_ACCESS_TYPE_MAX = MLX5_FPGA_ACCESS_TYPE_DONTCARE,
126};
127
128#define MLX5_FPGA_INTERNAL_SENSORS_LOW 63
129#define MLX5_FPGA_INTERNAL_SENSORS_HIGH 63
130
131struct mlx5_fpga_temperature {
132 uint32_t temperature;
133 uint32_t index;
134 uint32_t tee;
135 uint32_t max_temperature;
136 uint32_t temperature_threshold_hi;
137 uint32_t temperature_threshold_lo;
138 uint32_t mte;
139 uint32_t mtr;
140 char sensor_name[16];
141};
142
143#define MLX5_FPGA_CAP_ARR_SZ 0x40
144
145#define MLX5_FPGA_ACCESS_TYPE _IOWINT('m', 0x80)
146#define MLX5_FPGA_LOAD _IOWINT('m', 0x81)
147#define MLX5_FPGA_RESET _IO('m', 0x82)
148#define MLX5_FPGA_IMAGE_SEL _IOWINT('m', 0x83)
149#define MLX5_FPGA_QUERY _IOR('m', 0x84, struct mlx5_fpga_query)
150#define MLX5_FPGA_CAP _IOR('m', 0x85, uint32_t[MLX5_FPGA_CAP_ARR_SZ])
151#define MLX5_FPGA_TEMPERATURE _IOWR('m', 0x86, struct mlx5_fpga_temperature)
152#define MLX5_FPGA_CONNECT _IOWR('m', 0x87, enum mlx5_fpga_connect)
153#define MLX5_FPGA_RELOAD _IO('m', 0x88)
154
155#define MLX5_FPGA_TOOLS_NAME_SUFFIX "_mlx5_fpga_tools"
156
157#endif