1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#ifndef __X86_INTR_MACHDEP_H__
29#define __X86_INTR_MACHDEP_H__
30
31#ifdef _KERNEL
32
33/*
34 * Values used in determining the allocation of IRQ values among
35 * different types of I/O interrupts. These values are used as
36 * indices into a interrupt source array to map I/O interrupts to a
37 * device interrupt source whether it be a pin on an interrupt
38 * controller or an MSI interrupt. The 16 ISA IRQs are assigned fixed
39 * IDT vectors, but all other device interrupts allocate IDT vectors
40 * on demand. Currently we have 191 IDT vectors available for device
41 * interrupts on each CPU. On many systems with I/O APICs, a lot of
42 * the IRQs are not used, so the total number of IRQ values reserved
43 * can exceed the number of available IDT slots.
44 *
45 * The first 16 IRQs (0 - 15) are reserved for ISA IRQs. Interrupt
46 * pins on I/O APICs for non-ISA interrupts use IRQ values starting at
47 * IRQ 17. This layout matches the GSI numbering used by ACPI so that
48 * IRQ values returned by ACPI methods such as _CRS can be used
49 * directly by the ACPI bus driver.
50 *
51 * MSI interrupts allocate a block of interrupts starting at the end
52 * of the I/O APIC range. When running under the Xen Hypervisor, an
53 * additional range of IRQ values are available for binding to event
54 * channel events.
55 */
56extern u_int first_msi_irq;
57extern u_int num_io_irqs;
58extern u_int num_msi_irqs;
59
60/*
61 * Default base address for MSI messages on x86 platforms.
62 */
63#define MSI_INTEL_ADDR_BASE 0xfee00000
64
65typedef void inthand_t(void);
66
67#define IDTVEC(name) __CONCAT(X,name)
68
69struct intsrc;
70
71/*
72 * Methods that a PIC provides to mask/unmask a given interrupt source,
73 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
74 * return the vector associated with this source.
75 */
76struct pic {
77 void (*pic_register_sources)(struct pic *);
78 void (*pic_enable_source)(struct intsrc *);
79 void (*pic_disable_source)(struct intsrc *, int);
80 void (*pic_eoi_source)(struct intsrc *);
81 void (*pic_enable_intr)(struct intsrc *);
82 void (*pic_disable_intr)(struct intsrc *);
83 int (*pic_vector)(struct intsrc *);
84 int (*pic_source_pending)(struct intsrc *);
85 void (*pic_suspend)(struct pic *);
86 void (*pic_resume)(struct pic *, bool suspend_cancelled);
87 int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
88 enum intr_polarity);
89 int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
90 void (*pic_reprogram_pin)(struct intsrc *);
91 TAILQ_ENTRY(pic) pics;
92};
93
94/* Flags for pic_disable_source() */
95enum {
96 PIC_EOI,
97 PIC_NO_EOI,
98};
99
100/*
101 * An interrupt source. The upper-layer code uses the PIC methods to
102 * control a given source. The lower-layer PIC drivers can store additional
103 * private data in a given interrupt source such as an interrupt pin number
104 * or an I/O APIC pointer.
105 */
106struct intsrc {
107 struct pic *is_pic;
108 struct intr_event *is_event;
109 u_long *is_count;
110 u_long *is_straycount;
111 u_int is_index;
112 u_int is_handlers;
113 u_int is_domain;
114 u_int is_cpu;
115};
116
117struct trapframe;
118
119#ifdef SMP
120extern cpuset_t intr_cpus;
121#endif
122extern struct mtx icu_lock;
123extern int elcr_found;
124#ifdef SMP
125extern int msix_disable_migration;
126#endif
127
128#ifndef DEV_ATPIC
129void atpic_reset(void);
130#endif
131/* XXX: The elcr_* prototypes probably belong somewhere else. */
132int elcr_probe(void);
133enum intr_trigger elcr_read_trigger(u_int irq);
134void elcr_resume(void);
135void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
136#ifdef SMP
137void intr_add_cpu(u_int cpu);
138#endif
139int intr_add_handler(struct intsrc *isrc, const char *name,
140 driver_filter_t filter, driver_intr_t handler, void *arg,
141 enum intr_type flags, void **cookiep, int domain);
142int intr_config_intr(struct intsrc *isrc, enum intr_trigger trig,
143 enum intr_polarity pol);
144int intr_describe(struct intsrc *isrc, void *ih, const char *descr);
145void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
146u_int intr_next_cpu(int domain);
147struct intsrc *intr_lookup_source(int vector);
148int intr_register_pic(struct pic *pic);
149int intr_register_source(struct intsrc *isrc);
150int intr_remove_handler(void *cookie);
151void intr_resume(bool suspend_cancelled);
152void intr_suspend(void);
153void intr_reprogram(void);
154void intrcnt_add(const char *name, u_long **countp);
155void nexus_add_irq(u_long irq);
156int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
157void msi_init(void);
158int msi_map(int irq, uint64_t *addr, uint32_t *data);
159int msi_release(int *irqs, int count);
160int msix_alloc(device_t dev, int *irq);
161int msix_release(int irq);
162#ifdef XENHVM
163void xen_intr_alloc_irqs(void);
164#endif
165
166#endif /* _KERNEL */
167#endif /* !__X86_INTR_MACHDEP_H__ */