1/*-
2 * Copyright (c) 1995 Bruce D. Evans.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#ifndef _X86_X86_VAR_H_
31#define _X86_X86_VAR_H_
32
33/*
34 * Miscellaneous machine-dependent declarations.
35 */
36
37extern long Maxmem;
38extern u_int basemem;
39extern u_int cpu_exthigh;
40extern u_int cpu_feature;
41extern u_int cpu_feature2;
42extern u_int amd_feature;
43extern u_int amd_feature2;
44extern u_int amd_rascap;
45extern u_int amd_pminfo;
46extern u_int amd_extended_feature_extensions;
47extern u_int via_feature_rng;
48extern u_int via_feature_xcrypt;
49extern u_int cpu_clflush_line_size;
50extern u_int cpu_stdext_feature;
51extern u_int cpu_stdext_feature2;
52extern u_int cpu_stdext_feature3;
53extern u_int cpu_stdext_feature4;
54extern uint64_t cpu_ia32_arch_caps;
55extern u_int cpu_high;
56extern u_int cpu_id;
57extern u_int cpu_max_ext_state_size;
58extern u_int cpu_mxcsr_mask;
59extern u_int cpu_procinfo;
60extern u_int cpu_procinfo2;
61extern u_int cpu_procinfo3;
62extern char cpu_vendor[];
63extern char cpu_model[];
64extern u_int cpu_vendor_id;
65extern u_int cpu_mon_mwait_flags;
66extern u_int cpu_mon_mwait_edx;
67extern u_int cpu_mon_min_size;
68extern u_int cpu_mon_max_size;
69extern u_int cpu_maxphyaddr;
70extern u_int cpu_power_eax;
71extern u_int cpu_power_ebx;
72extern u_int cpu_power_ecx;
73extern u_int cpu_power_edx;
74extern u_int hv_base;
75extern u_int hv_high;
76extern char hv_vendor[];
77extern char kstack[];
78extern char sigcode[];
79extern int szsigcode;
80extern int workaround_erratum383;
81extern int _udatasel;
82extern int _ucodesel;
83extern int _ucode32sel;
84extern int _ufssel;
85extern int _ugssel;
86extern int use_xsave;
87extern uint64_t xsave_mask;
88extern u_int max_apic_id;
89extern int i386_read_exec;
90extern int pti;
91extern int hw_ibrs_ibpb_active;
92extern int hw_mds_disable;
93extern int hw_ssb_active;
94extern int x86_taa_enable;
95extern int cpu_flush_rsb_ctxsw;
96extern int x86_rngds_mitg_enable;
97extern int zenbleed_enable;
98extern int cpu_amdc1e_bug;
99extern char bootmethod[16];
100
101struct pcb;
102struct thread;
103struct reg;
104struct fpreg;
105struct dbreg;
106struct dumperinfo;
107struct trapframe;
108struct minidumpstate;
109
110/*
111 * The interface type of the interrupt handler entry point cannot be
112 * expressed in C. Use simplest non-variadic function type as an
113 * approximation.
114 */
115typedef void alias_for_inthand_t(void);
116
117bool acpi_get_fadt_bootflags(uint16_t *flagsp);
118void *alloc_fpusave(int flags);
119u_int cpu_auxmsr(void);
120vm_paddr_t cpu_getmaxphyaddr(void);
121bool cpu_mwait_usable(void);
122void cpu_probe_amdc1e(void);
123void cpu_setregs(void);
124int dbreg_set_watchpoint(vm_offset_t addr, vm_size_t size, int access);
125int dbreg_clr_watchpoint(vm_offset_t addr, vm_size_t size);
126void dbreg_list_watchpoints(void);
127void x86_clear_dbregs(struct pcb *pcb);
128bool disable_wp(void);
129void restore_wp(bool old_wp);
130void finishidentcpu(void);
131void identify_cpu1(void);
132void identify_cpu2(void);
133void identify_cpu_ext_features(void);
134void identify_cpu_fixup_bsp(void);
135void identify_hypervisor(void);
136void initializecpu(void);
137void initializecpucache(void);
138bool fix_cpuid(void);
139void fillw(int /*u_short*/ pat, void *base, size_t cnt);
140int isa_nmi(int cd);
141void handle_ibrs_entry(void);
142void handle_ibrs_exit(void);
143void hw_ibrs_recalculate(bool all_cpus);
144void hw_mds_recalculate(void);
145void hw_ssb_recalculate(bool all_cpus);
146void x86_taa_recalculate(void);
147void x86_rngds_mitg_recalculate(bool all_cpus);
148void zenbleed_sanitize_enable(void);
149void zenbleed_check_and_apply(bool all_cpus);
150void nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame);
151void nmi_call_kdb_smp(u_int type, struct trapframe *frame);
152void nmi_register_handler(int (*handler)(struct trapframe *));
153void nmi_remove_handler(int (*handler)(struct trapframe *));
154void nmi_handle_intr(struct trapframe *frame);
155void pagecopy(void *from, void *to);
156void printcpuinfo(void);
157int pti_get_default(void);
158int user_dbreg_trap(register_t dr6);
159int cpu_minidumpsys(struct dumperinfo *, const struct minidumpstate *);
160struct pcb *get_pcb_td(struct thread *td);
161void x86_set_fork_retval(struct thread *td);
162uint64_t rdtsc_ordered(void);
163
164/*
165 * MSR ops for x86_msr_op()
166 */
167#define MSR_OP_ANDNOT 0x00000001
168#define MSR_OP_OR 0x00000002
169#define MSR_OP_WRITE 0x00000003
170#define MSR_OP_READ 0x00000004
171
172/*
173 * Where and which execution mode
174 */
175#define MSR_OP_LOCAL 0x10000000
176#define MSR_OP_SCHED_ALL 0x20000000
177#define MSR_OP_SCHED_ONE 0x30000000
178#define MSR_OP_RENDEZVOUS_ALL 0x40000000
179#define MSR_OP_RENDEZVOUS_ONE 0x50000000
180#define MSR_OP_CPUID(id) ((id) << 8)
181
182void x86_msr_op(u_int msr, u_int op, uint64_t arg1, uint64_t *res);
183
184#if defined(__i386__) && defined(INVARIANTS)
185void trap_check_kstack(void);
186#else
187#define trap_check_kstack()
188#endif
189
190#endif