1/* $NetBSD: atareg.h,v 1.46 2022/07/05 19:21:26 andvar Exp $ */
2
3/*
4 * Copyright (c) 1998, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27/*-
28 * Copyright (c) 1991 The Regents of the University of California.
29 * All rights reserved.
30 *
31 * This code is derived from software contributed to Berkeley by
32 * William Jolitz.
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. Neither the name of the University nor the names of its contributors
43 * may be used to endorse or promote products derived from this software
44 * without specific prior written permission.
45 *
46 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
49 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56 * SUCH DAMAGE.
57 *
58 * @(#)wdreg.h 7.1 (Berkeley) 5/9/91
59 */
60
61#ifndef _DEV_ATA_ATAREG_H_
62#define _DEV_ATA_ATAREG_H_
63
64/*
65 * ATA Task File register definitions.
66 */
67
68/* Status bits. */
69#define WDCS_BSY 0x80 /* busy */
70#define WDCS_DRDY 0x40 /* drive ready */
71#define WDCS_DWF 0x20 /* drive write fault */
72#define WDCS_DSC 0x10 /* drive seek complete */
73#define WDCS_DRQ 0x08 /* data request */
74#define WDCS_CORR 0x04 /* corrected data */
75#define WDCS_IDX 0x02 /* index */
76#define WDCS_ERR 0x01 /* error */
77#define WDCS_BITS \
78 "\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err"
79
80/* Error bits. */
81#define WDCE_BBK 0x80 /* bad block detected */
82#define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */
83#define WDCE_UNC 0x40 /* uncorrectable data error */
84#define WDCE_MC 0x20 /* media changed */
85#define WDCE_IDNF 0x10 /* id not found */
86#define WDCE_MCR 0x08 /* media change requested */
87#define WDCE_ABRT 0x04 /* aborted command */
88#define WDCE_TK0NF 0x02 /* track 0 not found */
89#define WDCE_AMNF 0x01 /* address mark not found */
90
91/* Commands for Disk Controller. */
92#define WDCC_NOP 0x00 /* Always fail with "aborted command" */
93#define ATA_DATA_SET_MANAGEMENT 0x06
94#define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */
95
96#define WDCC_READ 0x20 /* disk read code */
97
98#define WDCC_READ_LOG_EXT 0x2f
99#define WDCC_LOG_PAGE_NCQ 0x10
100#define WDCC_LOG_NQ __BIT(7)
101
102#define WDCC_WRITE 0x30 /* disk write code */
103#define WDCC__LONG 0x02 /* modifier -- access ecc bytes */
104#define WDCC__NORETRY 0x01 /* modifier -- no retries */
105
106#define WDCC_READ_LOG_DMA_EXT 0x47 /* DMA variant of READ_LOG_EXT */
107
108#define WDCC_FORMAT 0x50 /* disk format code */
109#define WDCC_DIAGNOSE 0x90 /* controller diagnostic */
110#define WDCC_IDP 0x91 /* initialize drive parameters */
111
112#define WDCC_SMART 0xb0 /* Self Mon, Analysis, Reporting Tech */
113
114#define WDCC_READMULTI 0xc4 /* read multiple */
115#define WDCC_WRITEMULTI 0xc5 /* write multiple */
116#define WDCC_SETMULTI 0xc6 /* set multiple mode */
117
118#define WDCC_READDMA 0xc8 /* read with DMA */
119#define WDCC_WRITEDMA 0xca /* write with DMA */
120
121#define WDCC_ACKMC 0xdb /* acknowledge media change */
122#define WDCC_LOCK 0xde /* lock drawer */
123#define WDCC_UNLOCK 0xdf /* unlock drawer */
124
125#define WDCC_FLUSHCACHE 0xe7 /* Flush cache */
126#define WDCC_FLUSHCACHE_EXT 0xea /* Flush cache ext */
127#define WDCC_IDENTIFY 0xec /* read parameters from controller */
128#define SET_FEATURES 0xef /* set features */
129
130#define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */
131#define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */
132#define WDCC_SLEEP 0xe6 /* enter sleep mode */
133#define WDCC_STANDBY 0xe2 /* set standby timer & enter standby */
134#define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */
135#define WDCC_CHECK_PWR 0xe5 /* check power mode */
136
137/* Security feature set */
138#define WDCC_SECURITY_SET_PASSWORD 0xf1
139#define WDCC_SECURITY_UNLOCK 0xf2
140#define WDCC_SECURITY_ERASE_PREPARE 0xf3
141#define WDCC_SECURITY_ERASE_UNIT 0xf4
142#define WDCC_SECURITY_FREEZE 0xf5
143#define WDCC_SECURITY_DISABLE_PASSWORD 0xf6
144
145/* Big Drive support */
146#define WDCC_READ_EXT 0x24 /* read 48-bit addressing */
147#define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */
148
149#define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */
150#define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */
151
152#define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */
153#define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */
154#define WDCC_WRITEDMA_FUA_EXT 0x3d /* write 48-bit addr with DMA & FUA */
155
156#if defined(_KERNEL) || defined(_STANDALONE)
157#include <dev/ata/ataconf.h>
158
159/* Convert a 32-bit command to a 48-bit command. */
160static __inline int
161atacmd_to48(int cmd32)
162{
163 switch (cmd32) {
164 case WDCC_READ:
165 return WDCC_READ_EXT;
166 case WDCC_WRITE:
167 return WDCC_WRITE_EXT;
168 case WDCC_READMULTI:
169 return WDCC_READMULTI_EXT;
170 case WDCC_WRITEMULTI:
171 return WDCC_WRITEMULTI_EXT;
172#if NATA_DMA
173 case WDCC_READDMA:
174 return WDCC_READDMA_EXT;
175 case WDCC_WRITEDMA:
176 return WDCC_WRITEDMA_EXT;
177#endif
178 default:
179 panic("atacmd_to48: illegal 32-bit command: %d", cmd32);
180 /* NOTREACHED */
181 }
182}
183#endif /* _KERNEL || _STANDALONE */
184
185/* Native SATA command queueing */
186#define WDCC_READ_FPDMA_QUEUED 0x60 /* SATA native queued read (48bit) */
187#define WDCC_WRITE_FPDMA_QUEUED 0x61 /* SATA native queued write (48bit) */
188
189/* Subcommands for SET_FEATURES (features register) */
190#define WDSF_8BIT_PIO_EN 0x01
191#define WDSF_WRITE_CACHE_EN 0x02
192#define WDSF_SET_MODE 0x03
193#define WDSF_REASSIGN_EN 0x04
194#define WDSF_APM_EN 0x05
195#define WDSF_PUIS_EN 0x06
196#define WDSF_PUIS_SPIN_UP 0x07
197#define WDSF_SATA_EN 0x10
198#define WDSF_RETRY_DS 0x33
199#define WDSF_AAM_EN 0x42
200#define WDSF_SET_CACHE_SGMT 0x54
201#define WDSF_READAHEAD_DS 0x55
202#define WDSF_POD_DS 0x66
203#define WDSF_ECC_DS 0x77
204#define WDSF_WRITE_CACHE_DS 0x82
205#define WDSF_REASSIGN_DS 0x84
206#define WDSF_APM_DS 0x85
207#define WDSF_PUIS_DS 0x86
208#define WDSF_ECC_EN 0x88
209#define WDSF_SATA_DS 0x90
210#define WDSF_RETRY_EN 0x99
211#define WDSF_SET_CURRENT 0x9a
212#define WDSF_READAHEAD_EN 0xaa
213#define WDSF_PREFETCH_SET 0xab
214#define WDSF_AAM_DS 0xc2
215#define WDSF_POD_EN 0xcc
216
217/* Subcommands for WDSF_SATA (count register) */
218#define WDSF_SATA_NONZERO_OFFSETS 0x01
219#define WDSF_SATA_DMA_SETUP_AUTO 0x02
220#define WDSF_SATA_DRIVE_PWR_MGMT 0x03
221#define WDSF_SATA_IN_ORDER_DATA 0x04
222#define WDSF_SATA_ASYNC_NOTIFY 0x05
223#define WDSF_SATA_SW_STTNGS_PRS 0x06
224
225/* Subcommands for SMART (features register) */
226#define WDSM_RD_DATA 0xd0
227#define WDSM_RD_THRESHOLDS 0xd1
228#define WDSM_ATTR_AUTOSAVE_EN 0xd2
229#define WDSM_SAVE_ATTR 0xd3
230#define WDSM_EXEC_OFFL_IMM 0xd4
231#define WDSM_RD_LOG 0xd5
232#define WDSM_ENABLE_OPS 0xd8
233#define WDSM_DISABLE_OPS 0xd9
234#define WDSM_STATUS 0xda
235
236#define WDSMART_CYL 0xc24f
237
238/* parameters uploaded to count register for NCQ */
239#define WDSC_PRIO_HIGH __BIT(15)
240#define WDSC_PRIO_ISOCHRONOUS __BIT(14)
241#define WDSC_PRIO_NORMAL 0x0000
242
243/* parameters uploaded to device/heads register */
244#define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */
245#define WDSD_CHS 0x00 /* cylinder/head/sector addressing */
246#define WDSD_LBA 0x40 /* logical block addressing */
247#define WDSD_FUA 0x80 /* Forced Unit Access (FUA) */
248
249/* Commands for ATAPI devices */
250#define ATAPI_CHECK_POWER_MODE 0xe5
251#define ATAPI_EXEC_DRIVE_DIAGS 0x90
252#define ATAPI_IDLE_IMMEDIATE 0xe1
253#define ATAPI_NOP 0x00
254#define ATAPI_PKT_CMD 0xa0
255#define ATAPI_IDENTIFY_DEVICE 0xa1
256#define ATAPI_SOFT_RESET 0x08
257#define ATAPI_SLEEP 0xe6
258#define ATAPI_STANDBY_IMMEDIATE 0xe0
259
260/* Bytes used by ATAPI_PACKET_COMMAND (feature register) */
261#define ATAPI_PKT_CMD_FTRE_DMA 0x01
262#define ATAPI_PKT_CMD_FTRE_OVL 0x02
263
264/* ireason */
265#define WDCI_CMD 0x01 /* command(1) or data(0) */
266#define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */
267#define WDCI_RELEASE 0x04 /* bus released until completion */
268
269#define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD)
270#define PHASE_DATAIN (WDCS_DRQ | WDCI_IN)
271#define PHASE_DATAOUT (WDCS_DRQ)
272#define PHASE_COMPLETED (WDCI_IN | WDCI_CMD)
273#define PHASE_ABORTED (0)
274
275/*
276 * Drive parameter structure for ATA/ATAPI.
277 * Bit fields: WDC_* : common to ATA/ATAPI
278 * ATA_* : ATA only
279 * ATAPI_* : ATAPI only.
280 */
281struct ataparams {
282 /* drive info */
283 uint16_t atap_config; /* 0: general configuration */
284#define WDC_CFG_CFA_MAGIC 0x848a
285#define WDC_CFG_ATAPI 0x8000
286#define ATA_CFG_REMOVABLE 0x0080
287#define ATA_CFG_FIXED 0x0040
288#define ATAPI_CFG_TYPE_MASK 0x1f00
289#define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8)
290#define ATAPI_CFG_REMOV 0x0080
291#define ATAPI_CFG_DRQ_MASK 0x0060
292#define ATAPI_CFG_STD_DRQ 0x0000
293#define ATAPI_CFG_IRQ_DRQ 0x0020
294#define ATAPI_CFG_ACCEL_DRQ 0x0040
295#define ATAPI_CFG_CMD_MASK 0x0003
296#define ATAPI_CFG_CMD_12 0x0000
297#define ATAPI_CFG_CMD_16 0x0001
298/* words 1-9 are ATA only */
299 uint16_t atap_cylinders; /* 1: # of non-removable cylinders */
300 uint16_t __reserved1;
301 uint16_t atap_heads; /* 3: # of heads */
302 uint16_t __retired1[2]; /* 4-5: # of unform. bytes/track */
303 uint16_t atap_sectors; /* 6: # of sectors */
304 uint16_t __retired2[3];
305
306 uint8_t atap_serial[20]; /* 10-19: serial number */
307 uint16_t __retired3[2];
308 uint16_t __obsolete1;
309 uint8_t atap_revision[8]; /* 23-26: firmware revision */
310 uint8_t atap_model[40]; /* 27-46: model number */
311 uint16_t atap_multi; /* 47: maximum sectors per irq (ATA) */
312 uint16_t __reserved2;
313 uint16_t atap_capabilities1; /* 49: capability flags */
314#define WDC_CAP_IORDY 0x0800
315#define WDC_CAP_IORDY_DSBL 0x0400
316#define WDC_CAP_LBA 0x0200
317#define WDC_CAP_DMA 0x0100
318#define ATA_CAP_STBY 0x2000
319#define ATAPI_CAP_INTERL_DMA 0x8000
320#define ATAPI_CAP_CMD_QUEUE 0x4000
321#define ATAPI_CAP_OVERLP 0X2000
322#define ATAPI_CAP_ATA_RST 0x1000
323 uint16_t atap_capabilities2; /* 50: capability flags (ATA) */
324#if BYTE_ORDER == LITTLE_ENDIAN
325 uint8_t __junk2;
326 uint8_t atap_oldpiotiming; /* 51: old PIO timing mode */
327 uint8_t __junk3;
328 uint8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */
329#else
330 uint8_t atap_oldpiotiming; /* 51: old PIO timing mode */
331 uint8_t __junk2;
332 uint8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */
333 uint8_t __junk3;
334#endif
335 uint16_t atap_extensions; /* 53: extensions supported */
336#define WDC_EXT_UDMA_MODES 0x0004
337#define WDC_EXT_MODES 0x0002
338#define WDC_EXT_GEOM 0x0001
339/* words 54-62 are ATA only */
340 uint16_t atap_curcylinders; /* 54: current logical cylinders */
341 uint16_t atap_curheads; /* 55: current logical heads */
342 uint16_t atap_cursectors; /* 56: current logical sectors/tracks */
343 uint16_t atap_curcapacity[2]; /* 57-58: current capacity */
344 uint16_t atap_curmulti; /* 59: current multi-sector setting */
345#define WDC_MULTI_VALID 0x0100
346#define WDC_MULTI_MASK 0x00ff
347 uint16_t atap_capacity[2]; /* 60-61: total capacity (LBA only) */
348 uint16_t __retired4;
349#if BYTE_ORDER == LITTLE_ENDIAN
350 uint8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */
351 uint8_t atap_dmamode_act; /* multiword DMA mode active */
352 uint8_t atap_piomode_supp; /* 64: PIO mode supported */
353 uint8_t __junk4;
354#else
355 uint8_t atap_dmamode_act; /* multiword DMA mode active */
356 uint8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */
357 uint8_t __junk4;
358 uint8_t atap_piomode_supp; /* 64: PIO mode supported */
359#endif
360 uint16_t atap_dmatiming_mimi; /* 65: minimum DMA cycle time */
361 uint16_t atap_dmatiming_recom; /* 66: recommended DMA cycle time */
362 uint16_t atap_piotiming; /* 67: mini PIO cycle time without FC */
363 uint16_t atap_piotiming_iordy; /* 68: mini PIO cycle time with IORDY FC */
364 uint16_t __reserved3[2];
365/* words 71-72 are ATAPI only */
366 uint16_t atap_pkt_br; /* 71: time (ns) to bus release */
367 uint16_t atap_pkt_bsyclr; /* 72: tme to clear BSY after service */
368 uint16_t __reserved4[2];
369 uint16_t atap_queuedepth; /* 75: */
370#define WDC_QUEUE_DEPTH_MASK 0x1F
371 uint16_t atap_sata_caps; /* 76: */
372#define SATA_SIGNAL_GEN1 0x02
373#define SATA_SIGNAL_GEN2 0x04
374#define SATA_SIGNAL_GEN3 0x08
375#define SATA_NATIVE_CMDQ 0x0100 /* supp. NCQ feature set */
376#define SATA_HOST_PWR_MGMT 0x0200 /* supp. host-init. pwr mngmt reqs */
377#define SATA_PHY_EVNT_CNT 0x0400 /* supp. SATA Phy Event Counters log */
378#define SATA_UNLOAD_W_NCQ 0x0800 /* supp. unload w/ NCQ commands act */
379#define SATA_NCQ_PRIO 0x1000 /* supp. NCQ priority information */
380 uint16_t atap_sata_reserved; /* 77: */
381 uint16_t atap_sata_features_supp; /* 78: */
382#define SATA_NONZERO_OFFSETS 0x02
383#define SATA_DMA_SETUP_AUTO 0x04
384#define SATA_DRIVE_PWR_MGMT 0x08
385#define SATA_IN_ORDER_DATA 0x10
386#define SATA_SW_STTNGS_PRS 0x40
387 uint16_t atap_sata_features_en; /* 79: */
388 uint16_t atap_ata_major; /* 80: Major version number */
389#define WDC_VER_ATA1 0x0002
390#define WDC_VER_ATA2 0x0004
391#define WDC_VER_ATA3 0x0008
392#define WDC_VER_ATA4 0x0010
393#define WDC_VER_ATA5 0x0020
394#define WDC_VER_ATA6 0x0040
395#define WDC_VER_ATA7 0x0080
396#define WDC_VER_ATA8 0x0100
397 uint16_t atap_ata_minor; /* 81: Minor version number */
398 uint16_t atap_cmd_set1; /* 82: command set supported */
399#define WDC_CMD1_NOP 0x4000 /* NOP */
400#define WDC_CMD1_RB 0x2000 /* READ BUFFER */
401#define WDC_CMD1_WB 0x1000 /* WRITE BUFFER */
402/* 0x0800 Obsolete */
403#define WDC_CMD1_HPA 0x0400 /* Host Protected Area */
404#define WDC_CMD1_DVRST 0x0200 /* DEVICE RESET */
405#define WDC_CMD1_SRV 0x0100 /* SERVICE */
406#define WDC_CMD1_RLSE 0x0080 /* release interrupt */
407#define WDC_CMD1_AHEAD 0x0040 /* look-ahead */
408#define WDC_CMD1_CACHE 0x0020 /* write cache */
409#define WDC_CMD1_PKT 0x0010 /* PACKET */
410#define WDC_CMD1_PM 0x0008 /* Power Management */
411#define WDC_CMD1_REMOV 0x0004 /* Removable Media */
412#define WDC_CMD1_SEC 0x0002 /* Security Mode */
413#define WDC_CMD1_SMART 0x0001 /* SMART */
414 uint16_t atap_cmd_set2; /* 83: command set supported */
415#define ATA_CMD2_FCE 0x2000 /* FLUSH CACHE EXT */
416#define WDC_CMD2_FC 0x1000 /* FLUSH CACHE */
417#define WDC_CMD2_DCO 0x0800 /* Device Configuration Overlay */
418#define ATA_CMD2_LBA48 0x0400 /* 48-bit Address */
419#define WDC_CMD2_AAM 0x0200 /* Automatic Acoustic Management */
420#define WDC_CMD2_SM 0x0100 /* SET MAX security extension */
421#define WDC_CMD2_SFREQ 0x0040 /* SET FEATURE is required
422 to spin-up after power-up */
423#define WDC_CMD2_PUIS 0x0020 /* Power-Up In Standby */
424#define WDC_CMD2_RMSN 0x0010 /* Removable Media Status Notify */
425#define ATA_CMD2_APM 0x0008 /* Advanced Power Management */
426#define ATA_CMD2_CFA 0x0004 /* CFA */
427#define ATA_CMD2_RWQ 0x0002 /* READ/WRITE DMA QUEUED */
428#define WDC_CMD2_DM 0x0001 /* DOWNLOAD MICROCODE */
429 uint16_t atap_cmd_ext; /* 84: command/features supp. ext. */
430#define ATA_CMDE_TLCONT 0x1000 /* Time-limited R/W Continuous */
431#define ATA_CMDE_TL 0x0800 /* Time-limited R/W */
432#define ATA_CMDE_URGW 0x0400 /* URG for WRITE STREAM DMA/PIO */
433#define ATA_CMDE_URGR 0x0200 /* URG for READ STREAM DMA/PIO */
434#define ATA_CMDE_WWN 0x0100 /* World Wide name */
435#define ATA_CMDE_WQFE 0x0080 /* WRITE DMA QUEUED FUA EXT */
436#define ATA_CMDE_WFE 0x0040 /* WRITE DMA/MULTIPLE FUA EXT */
437#define ATA_CMDE_GPL 0x0020 /* General Purpose Logging */
438#define ATA_CMDE_STREAM 0x0010 /* Streaming */
439#define ATA_CMDE_MCPTC 0x0008 /* Media Card Pass Through Cmd */
440#define ATA_CMDE_MS 0x0004 /* Media serial number */
441#define ATA_CMDE_SST 0x0002 /* SMART self-test */
442#define ATA_CMDE_SEL 0x0001 /* SMART error logging */
443 uint16_t atap_cmd1_en; /* 85: cmd/features enabled */
444/* bits are the same as atap_cmd_set1 */
445 uint16_t atap_cmd2_en; /* 86: cmd/features enabled */
446/* bits are the same as atap_cmd_set2 */
447 uint16_t atap_cmd_def; /* 87: cmd/features default */
448#if BYTE_ORDER == LITTLE_ENDIAN
449 uint8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */
450 uint8_t atap_udmamode_act; /* Ultra-DMA mode active */
451#else
452 uint8_t atap_udmamode_act; /* Ultra-DMA mode active */
453 uint8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */
454#endif
455/* 89-92 are ATA-only */
456 uint16_t atap_seu_time; /* 89: Sec. Erase Unit compl. time */
457 uint16_t atap_eseu_time; /* 90: Enhanced SEU compl. time */
458 uint16_t atap_apm_val; /* 91: current APM value */
459 uint16_t __reserved5[8]; /* 92-99: reserved */
460 uint16_t atap_max_lba[4]; /* 100-103: Max. user LBA addr */
461 uint16_t __reserved6; /* 104: reserved */
462 uint16_t max_dsm_blocks; /* 105: DSM (ATA-8/ACS-2) */
463 uint16_t atap_secsz; /* 106: physical/logical sector size */
464#define ATA_SECSZ_VALID_MASK 0xc000
465#define ATA_SECSZ_VALID 0x4000
466#define ATA_SECSZ_LPS 0x2000 /* long physical sectors */
467#define ATA_SECSZ_LLS 0x1000 /* long logical sectors */
468#define ATA_SECSZ_LPS_SZMSK 0x000f /* 2**N logical per physical */
469 uint16_t atap_iso7779_isd; /* 107: ISO 7779 inter-seek delay */
470 uint16_t atap_wwn[4]; /* 108-111: World Wide Name */
471 uint16_t __reserved7[5]; /* 112-116 */
472 uint16_t atap_lls_secsz[2]; /* 117-118: long logical sector size */
473 uint16_t __reserved8[8]; /* 119-126 */
474 uint16_t atap_rmsn_supp; /* 127: remov. media status notif. */
475#define WDC_RMSN_SUPP_MASK 0x0003
476#define WDC_RMSN_SUPP 0x0001
477 uint16_t atap_sec_st; /* 128: security status */
478#define WDC_SEC_LEV_MAX 0x0100
479#define WDC_SEC_ESE_SUPP 0x0020
480#define WDC_SEC_EXP 0x0010
481#define WDC_SEC_FROZEN 0x0008
482#define WDC_SEC_LOCKED 0x0004
483#define WDC_SEC_EN 0x0002
484#define WDC_SEC_SUPP 0x0001
485 uint16_t __reserved9[31]; /* 129-159: vendor specific */
486 uint16_t atap_cfa_power; /* 160: CFA powermode */
487#define ATA_CFA_MAX_MASK 0x0fff
488#define ATA_CFA_MODE1_DIS 0x1000 /* CFA Mode 1 Disabled */
489#define ATA_CFA_MODE1_REQ 0x2000 /* CFA Mode 1 Required */
490#define ATA_CFA_WORD160 0x8000 /* Word 160 supported */
491 uint16_t __reserved10[8]; /* 161-168: reserved for CFA */
492 uint16_t support_dsm; /* 169: DSM (ATA-8/ACS-2) */
493#define ATA_SUPPORT_DSM_TRIM 0x0001
494 uint16_t __reserved10a[6]; /* 170-175: reserved for CFA */
495 uint8_t atap_media_serial[60]; /* 176-205: media serial number */
496 uint16_t __reserved11[3]; /* 206-208: */
497 uint16_t atap_logical_align; /* 209: logical/physical alignment */
498#define ATA_LA_VALID_MASK 0xc000
499#define ATA_LA_VALID 0x4000
500#define ATA_LA_MASK 0x3fff /* offset of sector LBA 0 in PBA 0 */
501 uint16_t __reserved12[45]; /* 210-254: */
502 uint16_t atap_integrity; /* 255: Integrity word */
503#define WDC_INTEGRITY_MAGIC_MASK 0x00ff
504#define WDC_INTEGRITY_MAGIC 0x00a5
505};
506
507/*
508 * If WDSM_ATTR_ADVISORY, device exceeded intended design life period.
509 * If not WDSM_ATTR_ADVISORY, imminent data loss predicted.
510 */
511#define WDSM_ATTR_ADVISORY 1
512
513/*
514 * If WDSM_ATTR_COLLECTIVE, attribute only updated in off-line testing.
515 * If not WDSM_ATTR_COLLECTIVE, attribute updated also in on-line testing.
516 */
517#define WDSM_ATTR_COLLECTIVE 2
518
519/*
520 * ATA SMART attributes
521 */
522
523struct ata_smart_attr {
524 uint8_t id; /* attribute id number */
525 uint16_t flags;
526 uint8_t value; /* attribute value */
527 uint8_t worst;
528 uint8_t raw[6];
529 uint8_t reserved;
530} __packed;
531
532struct ata_smart_attributes {
533 uint16_t data_structure_revision;
534 struct ata_smart_attr attributes[30];
535 uint8_t offline_data_collection_status;
536 uint8_t self_test_exec_status;
537 uint16_t total_time_to_complete_off_line;
538 uint8_t vendor_specific_366;
539 uint8_t offline_data_collection_capability;
540 uint16_t smart_capability;
541 uint8_t errorlog_capability;
542 uint8_t vendor_specific_371;
543 uint8_t short_test_completion_time;
544 uint8_t extend_test_completion_time;
545 uint8_t reserved_374_385[12];
546 uint8_t vendor_specific_386_509[125];
547 int8_t checksum;
548} __packed;
549
550struct ata_smart_thresh {
551 uint8_t id;
552 uint8_t value;
553 uint8_t reserved[10];
554} __packed;
555
556struct ata_smart_thresholds {
557 uint16_t data_structure_revision;
558 struct ata_smart_thresh thresholds[30];
559 uint8_t reserved[18];
560 uint8_t vendor_specific[131];
561 int8_t checksum;
562} __packed;
563
564struct ata_smart_selftest {
565 uint8_t number;
566 uint8_t status;
567 uint16_t time_stamp;
568 uint8_t failure_check_point;
569 uint32_t lba_first_error;
570 uint8_t vendor_specific[15];
571} __packed;
572
573struct ata_smart_selftestlog {
574 uint16_t data_structure_revision;
575 struct ata_smart_selftest log_entries[21];
576 uint8_t vendorspecific[2];
577 uint8_t mostrecenttest;
578 uint8_t reserved[2];
579 uint8_t checksum;
580} __packed;
581
582#endif /* _DEV_ATA_ATAREG_H_ */