1/* $NetBSD: hdaudioreg.h,v 1.4 2022/03/21 09:12:10 jmcneill Exp $ */
2
3/*
4 * Copyright (c) 2009 Precedence Technologies Ltd <support@precedence.co.uk>
5 * Copyright (c) 2009 Jared D. McNeill <jmcneill@invisible.ca>
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Precedence Technologies Ltd
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#ifndef _HDAUDIOREG_H
33#define _HDAUDIOREG_H
34
35#include <sys/cdefs.h>
36#include <sys/types.h>
37
38/*
39 * High Definition Audio Memory Mapped Configuration Registers
40 */
41#define HDAUDIO_MMIO_GCAP 0x000
42#define HDAUDIO_GCAP_64OK(x) ((x) & 1)
43#define HDAUDIO_GCAP_NSDO(x) ((((x) & 6) != 0) ? ((x) & 6) : 1)
44#define HDAUDIO_GCAP_BSS(x) (((x) >> 3) & 0x1f)
45#define HDAUDIO_GCAP_ISS(x) (((x) >> 8) & 0x0f)
46#define HDAUDIO_GCAP_OSS(x) (((x) >> 12) & 0x0f)
47#define HDAUDIO_MMIO_VMIN 0x002
48#define HDAUDIO_MMIO_VMAJ 0x003
49#define HDAUDIO_MMIO_OUTPAY 0x004
50#define HDAUDIO_MMIO_INPAY 0x006
51#define HDAUDIO_MMIO_GCTL 0x008
52#define HDAUDIO_GCTL_UNSOL_EN (1 << 8)
53#define HDAUDIO_GCTL_FLUSH_CTL (1 << 1)
54#define HDAUDIO_GCTL_CRST (1 << 0)
55#define HDAUDIO_MMIO_WAKEEN 0x00c
56#define HDAUDIO_MMIO_STATESTS 0x00e
57#define HDAUDIO_STATESTS_SDIWAKE 0x7fff
58#define HDAUDIO_MMIO_GSTS 0x010
59#define HDAUDIO_MMIO_INTCTL 0x020
60#define HDAUDIO_INTCTL_GIE (1u << 31)
61#define HDAUDIO_INTCTL_CIE (1 << 30)
62#define HDAUDIO_MMIO_INTSTS 0x024
63#define HDAUDIO_INTSTS_GIS (1u << 31)
64#define HDAUDIO_INTSTS_CIS (1 << 30)
65#define HDAUDIO_INTSTS_SIS_MASK 0x3fffffff
66#define HDAUDIO_MMIO_WALCLK 0x030
67#define HDAUDIO_MMIO_SYNC 0x034
68#define HDAUDIO_MMIO_CORBLBASE 0x040
69#define HDAUDIO_MMIO_CORBUBASE 0x044
70#define HDAUDIO_MMIO_CORBWP 0x048
71#define HDAUDIO_MMIO_CORBRP 0x04a
72#define HDAUDIO_CORBRP_RP_RESET (1 << 15)
73#define HDAUDIO_MMIO_CORBCTL 0x04c
74#define HDAUDIO_CORBCTL_RUN (1 << 1)
75#define HDAUDIO_CORBCTL_CMEI_EN (1 << 0)
76#define HDAUDIO_MMIO_CORBST 0x04d
77#define HDAUDIO_MMIO_CORBSIZE 0x04e
78#define HDAUDIO_MMIO_RIRBLBASE 0x050
79#define HDAUDIO_MMIO_RIRBUBASE 0x054
80#define HDAUDIO_MMIO_RIRBWP 0x058
81#define HDAUDIO_RIRBWP_WP_RESET (1 << 15)
82#define HDAUDIO_MMIO_RINTCNT 0x05a
83#define HDAUDIO_MMIO_RIRBCTL 0x05c
84#define HDAUDIO_RIRBCTL_ROI_EN (1 << 2)
85#define HDAUDIO_RIRBCTL_RUN (1 << 1)
86#define HDAUDIO_RIRBCTL_INT_EN (1 << 0)
87#define HDAUDIO_MMIO_RIRBSTS 0x05d
88#define HDAUDIO_RIRBSTS_RIRBOIS (1 << 2)
89#define HDAUDIO_RIRBSTS_RINTFL (1 << 0)
90#define HDAUDIO_MMIO_RIRBSIZE 0x05e
91#define HDAUDIO_MMIO_IC 0x060
92#define HDAUDIO_MMIO_IR 0x064
93#define HDAUDIO_MMIO_IRS 0x068
94#define HDAUDIO_MMIO_DPLBASE 0x070
95#define HDAUDIO_MMIO_DPUBASE 0x074
96
97#define HDAUDIO_MMIO_SD_SIZE 0x20
98#define HDAUDIO_MMIO_SD_BASE 0x080
99
100#define HDAUDIO_SD_REG(off, x) \
101 (HDAUDIO_MMIO_SD_BASE + ((x) * HDAUDIO_MMIO_SD_SIZE) + (off))
102#define HDAUDIO_SD_CTL0(x) HDAUDIO_SD_REG(0x00, x)
103#define HDAUDIO_CTL_SRST (1 << 0)
104#define HDAUDIO_CTL_RUN (1 << 1)
105#define HDAUDIO_CTL_IOCE (1 << 2)
106#define HDAUDIO_CTL_FEIE (1 << 3)
107#define HDAUDIO_CTL_DEIE (1 << 4)
108#define HDAUDIO_SD_CTL1(x) HDAUDIO_SD_REG(0x01, x)
109#define HDAUDIO_SD_CTL2(x) HDAUDIO_SD_REG(0x02, x)
110#define HDAUDIO_SD_STS(x) HDAUDIO_SD_REG(0x03, x)
111#define HDAUDIO_STS_FIFORDY (1 << 5)
112#define HDAUDIO_STS_DESE (1 << 4)
113#define HDAUDIO_STS_FIFOE (1 << 3)
114#define HDAUDIO_STS_BCIS (1 << 2)
115#define HDAUDIO_SD_LPIB(x) HDAUDIO_SD_REG(0x04, x)
116#define HDAUDIO_SD_CBL(x) HDAUDIO_SD_REG(0x08, x)
117#define HDAUDIO_SD_LVI(x) HDAUDIO_SD_REG(0x0c, x)
118#define HDAUDIO_SD_FIFOW(x) HDAUDIO_SD_REG(0x0e, x)
119#define HDAUDIO_SD_FIFOS(x) HDAUDIO_SD_REG(0x10, x)
120#define HDAUDIO_SD_FMT(x) HDAUDIO_SD_REG(0x12, x)
121#define HDAUDIO_FMT_TYPE_MASK 0x8000
122#define HDAUDIO_FMT_TYPE_PCM 0x0000
123#define HDAUDIO_FMT_TYPE_NONPCM 0x8000
124#define HDAUDIO_FMT_BASE_MASK 0x4000
125#define HDAUDIO_FMT_BASE_48 0x0000
126#define HDAUDIO_FMT_BASE_44 0x4000
127#define HDAUDIO_FMT_MULT_MASK 0x3800
128#define HDAUDIO_FMT_MULT(x) ((((x) - 1) << 11) & HDAUDIO_FMT_MULT_MASK)
129#define HDAUDIO_FMT_DIV_MASK 0x0700
130#define HDAUDIO_FMT_DIV(x) ((((x) - 1) << 8) & HDAUDIO_FMT_DIV_MASK)
131#define HDAUDIO_FMT_BITS_MASK 0x0070
132#define HDAUDIO_FMT_BITS_8_16 (0 << 4)
133#define HDAUDIO_FMT_BITS_16_16 (1 << 4)
134#define HDAUDIO_FMT_BITS_20_32 (2 << 4)
135#define HDAUDIO_FMT_BITS_24_32 (3 << 4)
136#define HDAUDIO_FMT_BITS_32_32 (4 << 4)
137#define HDAUDIO_FMT_CHAN_MASK 0x000f
138#define HDAUDIO_FMT_CHAN(x) (((x) - 1) & HDAUDIO_FMT_CHAN_MASK)
139#define HDAUDIO_SD_BDPL(x) HDAUDIO_SD_REG(0x18, x)
140#define HDAUDIO_SD_BDPU(x) HDAUDIO_SD_REG(0x1c, x)
141
142/*
143 * Codec Parameters and Controls
144 */
145#define CORB_GET_PARAMETER 0xf00
146#define COP_VENDOR_ID 0x00
147#define COP_REVISION_ID 0x02
148#define COP_SUBORDINATE_NODE_COUNT 0x04
149#define COP_NODECNT_STARTNODE(x) (((x) >> 16) & 0xff)
150#define COP_NODECNT_NUMNODES(x) (((x) >> 0) & 0xff)
151#define COP_FUNCTION_GROUP_TYPE 0x05
152#define COP_AUDIO_FUNCTION_GROUP_CAPABILITIES 0x08
153#define COP_AUDIO_WIDGET_CAPABILITIES 0x09
154#define COP_AWCAP_CHANNEL_COUNT(x) \
155 (((((x) & (0x7 << 13)) >> 12) | ((x) & 0x1)) + 1)
156#define COP_AWCAP_INAMP_PRESENT (1 << 1)
157#define COP_AWCAP_OUTAMP_PRESENT (1 << 2)
158#define COP_AWCAP_AMP_PARAM_OVERRIDE (1 << 3)
159#define COP_AWCAP_FORMAT_OVERRIDE (1 << 4)
160#define COP_AWCAP_STRIPE (1 << 5)
161#define COP_AWCAP_PROC_WIDGET (1 << 6)
162#define COP_AWCAP_UNSOL_CAPABLE (1 << 7)
163#define COP_AWCAP_CONN_LIST (1 << 8)
164#define COP_AWCAP_DIGITAL (1 << 9)
165#define COP_AWCAP_POWER_CNTRL (1 << 10)
166#define COP_AWCAP_LR_SWAP (1 << 11)
167#define COP_AWCAP_CP_CAPS (1 << 12)
168#define COP_AWCAP_CHAN_COUNT_EXT(x) (((x) >> 13) & 0x7)
169#define COP_AWCAP_DELAY(x) (((x) >> 16) & 0xf)
170#define COP_AWCAP_TYPE(x) (((x) >> 20) & 0xf)
171#define COP_AWCAP_TYPE_MASK 0x00f00000
172#define COP_AWCAP_TYPE_SHIFT 20
173#define COP_AWCAP_TYPE_AUDIO_OUTPUT 0x0
174#define COP_AWCAP_TYPE_AUDIO_INPUT 0x1
175#define COP_AWCAP_TYPE_AUDIO_MIXER 0x2
176#define COP_AWCAP_TYPE_AUDIO_SELECTOR 0x3
177#define COP_AWCAP_TYPE_PIN_COMPLEX 0x4
178#define COP_AWCAP_TYPE_POWER_WIDGET 0x5
179#define COP_AWCAP_TYPE_VOLUME_KNOB 0x6
180#define COP_AWCAP_TYPE_BEEP_GENERATOR 0x7
181#define COP_AWCAP_TYPE_VENDOR_DEFINED 0xf
182#define COP_SUPPORTED_PCM_SIZE_RATES 0x0a
183#define COP_SUPPORTED_STREAM_FORMATS 0x0b
184#define COP_STREAM_FORMAT_PCM (1 << 0)
185#define COP_STREAM_FORMAT_FLOAT32 (1 << 1)
186#define COP_STREAM_FORMAT_AC3 (1 << 2)
187#define COP_PIN_CAPABILITIES 0x0c
188#define COP_PINCAP_IMPEDANCE_SENSE_CAPABLE (1 << 0)
189#define COP_PINCAP_TRIGGER_REQD (1 << 1)
190#define COP_PINCAP_PRESENSE_DETECT_CAPABLE (1 << 2)
191#define COP_PINCAP_HEADPHONE_DRIVE_CAPABLE (1 << 3)
192#define COP_PINCAP_OUTPUT_CAPABLE (1 << 4)
193#define COP_PINCAP_INPUT_CAPABLE (1 << 5)
194#define COP_PINCAP_BALANCED_IO_PINS (1 << 6)
195#define COP_PINCAP_HDMI (1 << 7)
196#define COP_PINCAP_VREF_CONTROL(x) (((x) >> 8) & 0xff)
197#define COP_VREF_HIZ (1 << 0)
198#define COP_VREF_50 (1 << 1)
199#define COP_VREF_GROUND (1 << 2)
200#define COP_VREF_80 (1 << 4)
201#define COP_VREF_100 (1 << 5)
202#define COP_PINCAP_EAPD_CAPABLE (1 << 16)
203#define COP_PINCAP_DP (1 << 24)
204#define COP_PINCAP_HBR (1 << 27)
205#define COP_AMPLIFIER_CAPABILITIES_INAMP 0x0d
206#define COP_AMPLIFIER_CAPABILITIES_OUTAMP 0x12
207#define COP_AMPCAP_OFFSET(x) (((x) >> 0) & 0x7f)
208#define COP_AMPCAP_NUM_STEPS(x) (((x) >> 8) & 0x7f)
209#define COP_AMPCAP_STEP_SIZE(x) (((x) >> 16) & 0x7f)
210#define COP_AMPCAP_MUTE_CAPABLE(x) (((x) >> 31) & 0x1)
211#define COP_CONNECTION_LIST_LENGTH 0x0e
212#define COP_CONNECTION_LIST_LENGTH_LEN(x) ((x) & 0x7f)
213#define COP_CONNECTION_LIST_LENGTH_LONG_FORM (1 << 7)
214#define COP_SUPPORTED_POWER_STATES 0x0f
215#define COP_PROCESSING_CAPABILITIES 0x10
216#define COP_GPIO_COUNT 0x11
217#define COP_GPIO_COUNT_NUM_GPIO(x) ((x) & 0xff)
218#define COP_VOLUME_KNOB_CAPABILITIES 0x13
219#define COP_HDMI_LPCM_CAD 0x20
220#define COP_LPCM_CAD_44_1_MS (1u << 31)
221#define COP_LPCM_CAD_44_1 (1 << 30)
222#define COP_LPCM_CAD_192K_24BIT (1 << 29)
223#define COP_LPCM_CAD_192K_20BIT (1 << 28)
224#define COP_LPCM_CAD_192K_MAXCHAN(x) (((x) >> 24) & 0xf)
225#define COP_LPCM_CAD_192K_MAXCHAN_CP(x) (((x) >> 20) & 0xf)
226#define COP_LPCM_CAD_96K_24BIT (1 << 19)
227#define COP_LPCM_CAD_96K_20BIT (1 << 18)
228#define COP_LPCM_CAD_96K_MAXCHAN(x) (((x) >> 14) & 0xf)
229#define COP_LPCM_CAD_96K_MAXCHAN_CP(x) (((x) >> 10) & 0xf)
230#define COP_LPCM_CAD_48K_24BIT (1 << 9)
231#define COP_LPCM_CAD_48K_20BIT (1 << 8)
232#define COP_LPCM_CAD_48K_MAXCHAN(x) (((x) >> 4) & 0xf)
233#define COP_LPCM_CAD_48K_MAXCHAN_CP(x) (((x) >> 0) & 0xf)
234#define CORB_GET_CONNECTION_SELECT_CONTROL 0xf01
235#define CORB_SET_CONNECTION_SELECT_CONTROL 0x701
236#define CORB_GET_CONNECTION_LIST_ENTRY 0xf02
237#define CORB_GET_PROCESSING_STATE 0xf03
238#define CORB_SET_PROCESSING_STATE 0x703
239#define CORB_GET_COEFFICIENT_INDEX 0xd00
240#define CORB_SET_COEFFICIENT_INDEX 0x500
241#define CORB_GET_PROCESSING_COEFFICIENT 0xc00
242#define CORB_SET_PROCESSING_COEFFICIENT 0x400
243#define CORB_GET_AMPLIFIER_GAIN_MUTE 0xb00
244#define CORB_SET_AMPLIFIER_GAIN_MUTE 0x300
245#define CORB_GET_CONVERTER_FORMAT 0xa00
246#define CORB_SET_CONVERTER_FORMAT 0x200
247#define CORB_GET_DIGITAL_CONVERTER_CONTROL 0xf0d
248#define CORB_SET_DIGITAL_CONVERTER_CONTROL_1 0x70d
249#define COP_DIGITAL_CONVCTRL1_DIGEN (1 << 0)
250#define COP_DIGITAL_CONVCTRL1_V (1 << 1)
251#define COP_DIGITAL_CONVCTRL1_VCFG (1 << 2)
252#define COP_DIGITAL_CONVCTRL1_PRE (1 << 3)
253#define COP_DIGITAL_CONVCTRL1_COPY (1 << 4)
254#define COP_DIGITAL_CONVCTRL1_NAUDIO (1 << 5)
255#define COP_DIGITAL_CONVCTRL1_PRO (1 << 6)
256#define COP_DIGITAL_CONVCTRL1_L (1 << 7)
257#define CORB_SET_DIGITAL_CONVERTER_CONTROL_2 0x70e
258#define COP_DIGITAL_CONVCTRL2_CC_MASK 0x7f
259#define CORB_GET_POWER_STATE 0xf05
260#define CORB_SET_POWER_STATE 0x705
261#define COP_POWER_STATE_D0 0x00
262#define COP_POWER_STATE_D1 0x01
263#define COP_POWER_STATE_D2 0x02
264#define COP_POWER_STATE_D3 0x03
265#define CORB_GET_CONVERTER_STREAM_CHANNEL 0xf06
266#define CORB_SET_CONVERTER_STREAM_CHANNEL 0x706
267#define CORB_GET_INPUT_CONVERTER_SDI_SELECT 0xf04
268#define CORB_SET_INPUT_CONVERTER_SDI_SELECT 0x704
269#define CORB_GET_PIN_WIDGET_CONTROL 0xf07
270#define CORB_SET_PIN_WIDGET_CONTROL 0x707
271#define COP_PWC_VREF_ENABLE_MASK 0x7
272#define COP_PWC_VREF_HIZ 0x00
273#define COP_PWC_VREF_50 0x01
274#define COP_PWC_VREF_GND 0x02
275#define COP_PWC_VREF_80 0x04
276#define COP_PWC_VREF_100 0x05
277#define COP_PWC_IN_ENABLE (1 << 5)
278#define COP_PWC_OUT_ENABLE (1 << 6)
279#define COP_PWC_HPHN_ENABLE (1 << 7)
280#define COP_PWC_EPT_MASK 0x3
281#define COP_PWC_EPT_NATIVE 0x0
282#define COP_PWC_EPT_HIGH_BIT_RATE 0x3
283#define CORB_GET_UNSOLICITED_RESPONSE 0xf08
284#define CORB_SET_UNSOLICITED_RESPONSE 0x708
285#define COP_SET_UNSOLICITED_RESPONSE_ENABLE (1 << 7)
286#define CORB_GET_PIN_SENSE 0xf09
287#define COP_GET_PIN_SENSE_PRESENSE_DETECT (1u << 31)
288#define COP_GET_PIN_SENSE_ELD_VALID (1 << 30) /* digital */
289#define COP_GET_PIN_SENSE_IMPEDENCE_SENSE(x) ((x) & 0x7fffffff) /* analog */
290#define CORB_SET_PIN_SENSE 0x709
291#define CORB_GET_EAPD_BTL_ENABLE 0xf0c
292#define CORB_SET_EAPD_BTL_ENABLE 0x70c
293#define COP_EAPD_ENABLE_BTL (1 << 0)
294#define COP_EAPD_ENABLE_EAPD (1 << 1)
295#define COP_EAPD_ENABLE_LR_SWAP (1 << 2)
296#define CORB_GET_GPI_DATA 0xf10
297#define CORB_SET_GPI_DATA 0x710
298#define CORB_GET_GPI_WAKE_ENABLE_MASK 0xf11
299#define CORB_SET_GPI_WAKE_ENABLE_MASK 0x711
300#define CORB_GET_GPI_UNSOLICITED_ENABLE_MASK 0xf12
301#define CORB_SET_GPI_UNSOLICITED_ENABLE_MASK 0x712
302#define CORB_GET_GPI_STICKY_MASK 0xf13
303#define CORB_SET_GPI_STICKY_MASK 0x713
304#define CORB_GET_GPO_DATA 0xf14
305#define CORB_SET_GPO_DATA 0x714
306#define CORB_GET_GPIO_DATA 0xf15
307#define CORB_SET_GPIO_DATA 0x715
308#define CORB_GET_GPIO_ENABLE_MASK 0xf16
309#define CORB_SET_GPIO_ENABLE_MASK 0x716
310#define CORB_GET_GPIO_DIRECTION 0xf17
311#define CORB_SET_GPIO_DIRECTION 0x717
312#define CORB_GET_GPIO_WAKE_ENABLE_MASK 0xf18
313#define CORB_SET_GPIO_WAKE_ENABLE_MASK 0x718
314#define CORB_GET_GPIO_UNSOLICITED_ENABLE_MASK 0xf19
315#define CORB_SET_GPIO_UNSOLICITED_ENABLE_MASK 0x719
316#define CORB_GET_GPIO_STICKY_MASK 0xf1a
317#define CORB_SET_GPIO_STICKY_MASK 0x71a
318#define CORB_GET_BEEP_GENERATION 0xf0a
319#define CORB_SET_BEEP_GENERATION 0x70a
320#define CORB_GET_VOLUME_KNOB 0xf0f
321#define CORB_SET_VOLUME_KNOB 0x70f
322#define CORB_GET_SUBSYSTEM_ID 0xf20
323#define CORB_SET_SUBSYSTEM_ID_1 0x720
324#define CORB_SET_SUBSYSTEM_ID_2 0x721
325#define CORB_SET_SUBSYSTEM_ID_3 0x722
326#define CORB_SET_SUBSYSTEM_ID_4 0x723
327#define CORB_GET_CONFIGURATION_DEFAULT 0xf1c
328#define COP_CFG_SEQUENCE(x) (((x) >> 0) & 0xf)
329#define COP_CFG_DEFAULT_ASSOCIATION(x) (((x) >> 4) & 0xf)
330#define COP_CFG_MISC(x) (((x) >> 8) & 0xf)
331#define COP_CFG_COLOR(x) (((x) >> 12) & 0xf)
332#define COP_CFG_CONNECTION_TYPE(x) (((x) >> 16) & 0xf)
333#define COP_CONN_TYPE_UNKNOWN 0x0
334#define COP_CONN_TYPE_18INCH 0x1
335#define COP_CONN_TYPE_14INCH 0x2
336#define COP_CONN_TYPE_ATAPI_INTERNAL 0x3
337#define COP_CONN_TYPE_RCA 0x4
338#define COP_CONN_TYPE_OPTICAL 0x5
339#define COP_CONN_TYPE_OTHER_DIGITAL 0x6
340#define COP_CONN_TYPE_OTHER_ANALOG 0x7
341#define COP_CONN_TYPE_DIN 0x8
342#define COP_CONN_TYPE_XLR 0x9
343#define COP_CONN_TYPE_RJ11 0xa
344#define COP_CONN_TYPE_COMBINATION 0xb
345#define COP_CONN_TYPE_OTHER 0xf
346#define COP_CFG_DEFAULT_DEVICE(x) (((x) >> 20) & 0xf)
347#define COP_DEVICE_MASK 0x00f00000
348#define COP_DEVICE_SHIFT 20
349#define COP_DEVICE_LINE_OUT 0x0
350#define COP_DEVICE_SPEAKER 0x1
351#define COP_DEVICE_HP_OUT 0x2
352#define COP_DEVICE_CD 0x3
353#define COP_DEVICE_SPDIF_OUT 0x4
354#define COP_DEVICE_DIGITAL_OTHER_OUT 0x5
355#define COP_DEVICE_MODEM_LINE_SIDE 0x6
356#define COP_DEVICE_MODEM_HANDSET_SIDE 0x7
357#define COP_DEVICE_LINE_IN 0x8
358#define COP_DEVICE_AUX 0x9
359#define COP_DEVICE_MIC_IN 0xa
360#define COP_DEVICE_TELEPHONY 0xb
361#define COP_DEVICE_SPDIF_IN 0xc
362#define COP_DEVICE_DIGITAL_OTHER_IN 0xd
363#define COP_DEVICE_OTHER 0xf
364#define COP_CFG_LOCATION(x) (((x) >> 24) & 0x3f)
365#define COP_CFG_PORT_CONNECTIVITY(x) (((x) >> 30) & 0x3)
366#define COP_PORT_JACK 0x0
367#define COP_PORT_NONE 0x1
368#define COP_PORT_FIXED_FUNCTION 0x2
369#define COP_PORT_BOTH 0x3
370#define CORB_SET_CONFIGURATION_DEFAULT_1 0x71c
371#define CORB_SET_CONFIGURATION_DEFAULT_2 0x71d
372#define CORB_SET_CONFIGURATION_DEFAULT_3 0x71e
373#define CORB_SET_CONFIGURATION_DEFAULT_4 0x71f
374#define CORB_GET_STRIPE_CONTROL 0xf24
375#define CORB_SET_STRIPE_CONTROL 0x720
376#define CORB_EXECUTE_RESET 0x7ff
377#define CORB_GET_CONVERTER_CHANNEL_COUNT 0xf2d
378#define CORB_SET_CONVERTER_CHANNEL_COUNT 0x72d
379#define CORB_GET_HDMI_DIP_SIZE 0xf2e
380#define COP_DIP_ELD_SIZE (1 << 3)
381#define COP_DIP_PI_GP(x) ((x) & 0x7)
382#define COP_DIP_PI_AUDIO_INFO COP_DIP_PI_GP(0)
383#define COP_DIP_BUFFER_SIZE(x) ((x) & 0xff)
384#define CORB_GET_HDMI_ELD_DATA 0xf2f
385#define COP_ELD_VALID (1u << 31)
386#define COP_ELD_DATA(x) (((x) >> 0) & 0xff)
387#define CORB_GET_HDMI_DIP_INDEX 0xf30
388#define CORB_SET_HDMI_DIP_INDEX 0x730
389#define COP_DIP_INDEX_BYTE_SHIFT 0
390#define COP_DIP_INDEX_BYTE_MASK 0xf
391#define COP_DIP_INDEX_PACKET_INDEX_SHIFT 4
392#define COP_DIP_INDEX_PACKET_INDEX_MASK 0xf
393#define CORB_GET_HDMI_DIP_DATA 0xf31
394#define CORB_SET_HDMI_DIP_DATA 0x731
395#define CORB_GET_HDMI_DIP_XMIT_CTRL 0xf32
396#define CORB_SET_HDMI_DIP_XMIT_CTRL 0x732
397#define COP_DIP_XMIT_CTRL_DISABLE (0x0 << 6)
398#define COP_DIP_XMIT_CTRL_ONCE (0x2 << 6)
399#define COP_DIP_XMIT_CTRL_BEST_EFFORT (0x3 << 6)
400#define CORB_GET_PROTECTION_CONTROL 0xf33
401#define CORB_SET_PROTECTION_CONTROL 0x733
402#define COP_PROTECTION_CONTROL_CES_ON (1 << 9)
403#define COP_PROTECTION_CONTROL_READY (1 << 8)
404#define COP_PROTECTION_CONTROL_URSUBTAG_SHIFT 3
405#define COP_PROTECTION_CONTROL_URSUBTAG_MASK 0x1f
406#define COP_PROTECTION_CONTROL_CPSTATE_MASK 0x3
407#define COP_PROTECTION_CONTROL_CPSTATE_DONTCARE (0 << 0)
408#define COP_PROTECTION_CONTROL_CPSTATE_OFF (2 << 0)
409#define COP_PROTECTION_CONTROL_CPSTATE_ON (3 << 0)
410#define CORB_ASP_GET_CHANNEL_MAPPING 0xf34
411#define CORB_ASP_SET_CHANNEL_MAPPING 0x734
412
413
414/*
415 * RIRB Entry Format
416 */
417struct rirb_entry {
418 uint32_t resp;
419 uint32_t resp_ex;
420#define RIRB_CODEC_ID(entry) ((entry)->resp_ex & 0xf)
421#define RIRB_UNSOL(entry) ((entry)->resp_ex & 0x10)
422} __packed;
423
424#endif /* !_HDAUDIOREG_H */