1/* $NetBSD: summitreg.h,v 1.16 2025/01/29 15:35:22 macallan Exp $ */
2
3/*
4 * Copyright (c) 2024 Michael Lorenz
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/* HP Visualize FX 4 and related hardware, aka Summit */
30
31/*
32 * register values, found by disassembling the ROM
33 * some found by Sven Schnelle
34 * ( see https://patchwork.kernel.org/project/linux-parisc/patch/20211031204952.25678-2-svens@stackframe.org/ )
35 * some by me
36 */
37
38#ifndef SUMMITREG_H
39#define SUMMITREG_H
40
41#define VISFX_CONTROL 0x641000
42 #define CONTROL_WFC 0x00000200 // FIFO when 0, direct when 1
43#define VISFX_FC 0x641040 // Fault Control
44#define VISFX_STATUS 0x641400 // zero when idle
45/*
46 * about the FIFO register:
47 * - on FX4, there are 0x800 FIFO slots, quite a lot
48 * - based on observation, every register write seems to occupy *two* slots
49 * - we need to write 0 to VISFX_CONTROL to enable FIFO pacing
50 * - the FIFO is quite difficult to overrun but things like x11perf copywinwin
51 * will do it if we're not careful
52 */
53#define VISFX_FIFO 0x641440
54#define VISFX_FOE 0x920404 // Fragment Operation Enable
55 #define FOE_TEXTURE 0x00000001
56 #define FOE_SPECULAR 0x00000002
57 #define FOE_DEPTHCUE 0x00000004
58 #define FOE_ALPHATEST 0x00000008
59 #define FOE_STENCIL 0x00000010
60 #define FOE_Z_TEST 0x00000020
61 #define FOE_BLEND_ROP 0x00000040 // IBO is used
62 #define FOE_DITHER 0x00000080
63#define VISFX_IBO 0x921110 // ROP in lowest nibble
64#define VISFX_CBR 0x92111c // constant colour for blending
65#define VISFX_IAA0 0x921200 // XLUT, 16 entries
66#define VISFX_IAA(n) (0x921200 + ((n) << 2))
67#define VISFX_OTR 0x921148 // overlay transparency
68
69#define VISFX_VRAM_WRITE_MODE 0xa00808
70#define VISFX_VRAM_READ_MODE 0xa0080c
71#define VISFX_PIXEL_MASK 0xa0082c
72#define VISFX_FG_COLOUR 0xa0083c
73#define VISFX_BG_COLOUR 0xa00844
74#define VISFX_PLANE_MASK 0xa0084c
75/* this controls what we see in the FB aperture */
76#define VISFX_APERTURE_ACCESS 0xa00858
77 #define VISFX_DEPTH_8 0x30
78 #define VISFX_DEPTH_32 0x50
79#define VISFX_RPH 0xa0085c // read prefetch hint
80 #define VISFX_RPH_RTL 0x80000000 // right-to-left
81 #define VISFX_RPH_LTR 0x00000000 // left-to-right
82
83#define VISFX_READ_DATA 0xa41480
84
85#define VISFX_VRAM_WRITE_DATA_INCRX 0xa60000
86#define VISFX_VRAM_WRITE_DATA_INCRY 0xa68000
87#define VISFX_VRAM_WRITE_DEST 0xac1000
88#define VISFX_TCR 0xac1024 /* throttle control */
89#define VISFX_CLIP_TL 0xac1050 /* clipping rect, top/left */
90#define VISFX_CLIP_WH 0xac1054 /* clipping rect, w/h */
91
92#define VISFX_WRITE_MODE_PLAIN 0x02000000
93#define VISFX_WRITE_MODE_EXPAND 0x050004c0
94#define VISFX_WRITE_MODE_FILL 0x050008c0
95#define VISFX_WRITE_MODE_TRANSPARENT 0x00000800 /* bg is tansparent */
96#define VISFX_WRITE_MODE_MASK 0x00000400 /* apply pixel mask */
97/* 0x00000200 - some pattern */
98/* looks like 0x000000c0 enables fb/bg colours to be applied */
99
100#define VISFX_READ_MODE_COPY 0x02000400
101
102#define OTC01 0x00000000 /* one pixel per 32bit write */
103#define OTC04 0x02000000 /* 4 pixels per 32bit write */
104#define OTC32 0x05000000 /* 32 pixels per 32bit write */
105#define BIN8I 0x00000000 /* 8bit indexed */
106#define BIN12I 0x00010000 /* 12bit indexed */
107#define BIN332F 0x00040000 /* R3G3B2 */
108#define BIN8F 0x00070000 /* ARGB8 */
109#define BINapln 0x00110000 /* attribute plane */
110#define BINhost 0x00300000 /* DMA to host */
111#define BUFovl 0x00000000 /* 8bit overlay */
112#define BUFBL 0x00008000 /* back/left */
113#define BUFFL 0x00004000 /* front/left */
114#define BUFBR 0x00002000 /* back/right */
115#define BUFFR 0x00001000 /* front/right */
116
117/* attribute table, this only selects depth and CFS */
118#define IAA_8I 0x00000000 /* 8bit CI */
119#define IAA_8F 0x00000070 /* RGB8 */
120#define IAA_CFS0 0x00000000 /* CFS select */
121#define IAA_CFS1 0x00000100 /* CFS 1 etc. */
122
123#define OTR_T 0x00010000 /* when set 0 is transparent, otherwise 0xff */
124#define OTR_A 0x00000100 /* always transparent */
125#define OTR_L1 0x00000002 /* transparency controlled by CFS17 */
126#define OTR_L0 0x00000001 /* transparency controlled by CFS16 */
127
128/*
129 * for STI colour change mode:
130 * set VISFX_FG_COLOUR, VISFX_BG_COLOUR
131 * set VISFX_VRAM_READ_MODE 0x05000400
132 * set VISFX_VRAM_WRITE_MODE 0x050000c0
133 */
134
135/* fill */
136#define VISFX_START 0xb3c000
137#define VISFX_SIZE 0xb3c808 /* start, FX4 uses 0xb3c908 */
138
139/* copy */
140#define VISFX_COPY_SRC 0xb3c010
141#define VISFX_COPY_WH 0xb3c008
142#define VISFX_COPY_DST 0xb3cc00
143/*
144 * looks like ORing 0x800 to the register address starts a command
145 * - 0x800 - fill
146 * - 0xc00 - copy
147 * 0x100 and 0x200 seem to have functions as well, not sure what though
148 * for example, the FX4 ROM uses 0xb3c908 to start a rectangle fill, but
149 * it also works with 0xb3c808 and 0xb3ca08
150 * same with copy, 0xc00 seems to be what matters, setting 0x100 or 0x200
151 * doesn't seem to make a difference
152 * 0x400 or 0x100 by themselves don't start a command either
153 */
154
155/*
156 * alpha blending operations
157 * source and destination blend functions are in 0xf0 and 0x0f
158 * how they're combined is in 0x700
159 */
160#define IBO_ROP 0 /* ROP in lower 4 bit */
161#define IBO_ADD 0x200
162#define IBO_S_MINUS_D 0x400 /* source - dest */
163#define IBO_D_MINUS_S 0x500 /* dest - source */
164#define IBO_MIN 0x600
165#define IBO_MAX 0x700
166
167/*
168 * here are the blend functions I identified
169 * apparently the upper byte in 32bit mode is not implemented on FX2/4/6, and
170 * neither is any blend mode that takes the colour value from CBR
171 * so no blending with screen-to-screen blits, alpha will always read zero
172 * the only ways to actually use alpha blending is with fills ( the alpha part
173 * of the FG register is used ) and BINC writes, or when using constant alpha
174 */
175#define IBO_ZERO 0
176#define IBO_ONE 1
177#define IBO_SRC 4 /* src alpha */
178#define IBO_ONE_MINUS_SRC 5 /* 1 - src alpha */
179#define IBO_CBR 14 /* alpha from CBR */
180#define IBO_ONE_MINUS_CBR 15 /* 1 - alpha from CBR */
181
182#define SRC(n) ((n) << 4)
183#define DST(n) (n)
184/*
185 * use unbuffered space for cursor registers
186 * The _POS, _INDEX and _DATA registers work exactly like on HCRX
187 */
188
189#define VISFX_CURSOR_POS 0x400000
190#define VISFX_CURSOR_ENABLE 0x80000000
191#define VISFX_CURSOR_INDEX 0x400004
192#define VISFX_CURSOR_DATA 0x400008
193#define VISFX_CURSOR_FG 0x40000c
194#define VISFX_CURSOR_BG 0x400010
195#define VISFX_COLOR_MASK 0x800018
196#define VISFX_COLOR_INDEX 0x800020
197#define VISFX_COLOR_VALUE 0x800024
198#define VISFX_FATTR 0x80003c /* force attribute */
199#define VISFX_MPC 0x80004c
200 #define MPC_VIDEO_ON 0x0c
201 #define MPC_VSYNC_OFF 0x02
202 #define MPC_HSYNC_OFF 0x01
203#define VISFX_CFS0 0x800100 /* colour function select */
204#define VISFX_CFS(n) (VISFX_CFS0 + ((n) << 2))
205/* 0 ... 6 for image planes, 7 or bypass, 16 and 17 for overlay */
206#define CFS_CR 0x80 // enable color recovery
207#define CFS_332 0x00 // R3G3B2
208#define CFS_8I 0x40 // 8bit indexed
209#define CFS_8F 0x70 // ARGB8
210#define CFS_LUT0 0x00 // use LUT 0
211#define CFS_LUT1 0x01 // LUT 1 etc.
212#define CFS_BYPASS 0x07 // bypass LUT
213
214#endif /* SUMMITREG_H */