1/* $NetBSD: mgxreg.h,v 1.7 2021/11/11 19:37:30 macallan Exp $ */
2
3/* register definitions based on OpenBSD's atxxreg.h: */
4
5/*
6 * Copyright (c) 2008 Miodrag Vallat.
7 * Copyright (c) 2014 Michael Lorenz
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 */
21
22/*
23 * Alliance Promotion AP6422, AT24 and AT3D extended register set definitions.
24 *
25 * This has been reconstructed from XFree86 ``apm'' driver, whose authors
26 * apparently do not believe in meaningful constants for numbers. See
27 * apm_regs.h for more madness.
28 */
29
30#ifndef MGX_REG_H
31#define MGX_REG_H
32
33#define MGX_FBOFFSET 0x00000000
34#define MGX_BLTOFFSET 0x00800000
35#define MGX_FLIPOFFSET 0x01000000
36
37#define VGA_BASE 0x3c0
38#define CRTC_INDEX 0x3d4
39#define CRTC_DATA 0x3d5
40#define SEQ_INDEX 0x3c4
41#define SEQ_DATA 0x3c5
42
43/*
44 * some bits from the XFree86 3.x vga256 / apm driver:
45 * - sequencer registers 0x11 - 0x17 contain the chip's ID, 'Pro6424' for AT24
46 */
47
48#define SEQ_APERTURE 0x1c
49 #define AP_SIZE_MASK 0x06
50 #define AP_SIZE_1MB 0x00
51 #define AP_SIZE_2MB 0x02
52 #define AP_SIZE_4MB 0x04
53 #define AP_SIZE_6MB 0x06
54 #define AP_SIMULTANEOUS 0x20 /* sim. access to VRAM? */
55
56/*
57 * Clipping Control
58 */
59
60#define ATR_CLIP_CONTROL 0x0030 /* byte access */
61#define ATR_CLIP_LEFT 0x0038
62#define ATR_CLIP_TOP 0x003a
63#define ATR_CLIP_LEFTTOP 0x0038
64#define ATR_CLIP_RIGHT 0x003c
65#define ATR_CLIP_BOTTOM 0x003e
66#define ATR_CLIP_RIGHTBOTTOM 0x003c
67
68/*
69 * Drawing Engine
70 */
71
72#define ATR_DEC 0x0040
73#define ATR_ROP 0x0046
74#define ATR_BYTEMASK 0x0047
75#define ATR_PATTERN1 0x0048
76#define ATR_PATTERN2 0x004c
77#define ATR_SRC_X 0x0050
78#define ATR_SRC_Y 0x0052
79#define ATR_SRC_XY 0x0050 /* pointer in vram if DEC_SRC_LINEAR */
80#define ATR_DST_X 0x0054
81#define ATR_DST_Y 0x0056
82#define ATR_DST_XY 0x0054
83#define ATR_W 0x0058
84#define ATR_H 0x005a
85#define ATR_WH 0x0058
86#define ATR_OFFSET 0x005c
87#define ATR_SRC_OFFSET 0x005e
88#define ATR_FG 0x0060
89#define ATR_BG 0x0064
90
91/* DEC layout */
92#define DEC_COMMAND_MASK 0x0000003f
93#define DEC_COMMAND_SHIFT 0
94#define DEC_DIR_X_REVERSE 0x00000040
95#define DEC_DIR_Y_REVERSE 0x00000080
96#define DEC_DIR_Y_MAJOR 0x00000100
97#define DEC_SRC_LINEAR 0x00000200
98#define DEC_SRC_CONTIGUOUS 0x00000800
99#define DEC_MONOCHROME 0x00001000
100#define DEC_SRC_TRANSPARENT 0x00002000
101#define DEC_DEPTH_MASK 0x0001c000
102#define DEC_DEPTH_SHIFT 14
103#define DEC_DST_LINEAR 0x00040000
104#define DEC_DST_CONTIGUOUS 0x00080000
105#define DEC_DST_TRANSPARENT 0x00100000
106#define DEC_DST_TRANSPARENT_POLARITY 0x00200000
107#define DEC_PATTERN_MASK 0x00c00000
108#define DEC_PATTERN_SHIFT 22
109#define DEC_WIDTH_MASK 0x07000000
110#define DEC_WIDTH_SHIFT 24
111#define DEC_UPDATE_MASK 0x18000000
112#define DEC_UPDATE_SHIFT 27
113#define DEC_START_MASK 0x60000000
114#define DEC_START_SHIFT 29
115#define DEC_START 0x80000000
116
117/* DEC commands */
118#define DEC_COMMAND_NOP 0x00
119#define DEC_COMMAND_BLT 0x01 /* screen to screen blt */
120#define DEC_COMMAND_RECT 0x02 /* rectangle fill */
121#define DEC_COMMAND_BLT_STRETCH 0x03 /* blt and stretch */
122#define DEC_COMMAND_STRIP 0x04 /* strip pattern */
123#define DEC_COMMAND_HOST_BLT 0x08 /* host to screen blt */
124#define DEC_COMMAND_SCREEN_BLT 0x09 /* screen to host blt */
125#define DEC_COMMAND_VECT_ENDP 0x0c /* vector with end point */
126#define DEC_COMMAND_VECT_NO_ENDP 0x0d /* vector without end point */
127
128/* depth */
129#define DEC_DEPTH_8 0x01
130#define DEC_DEPTH_16 0x02
131#define DEC_DEPTH_32 0x03
132#define DEC_DEPTH_24 0x04
133
134/* width */
135#define DEC_WIDTH_LINEAR 0x00
136#define DEC_WIDTH_640 0x01
137#define DEC_WIDTH_800 0x02
138#define DEC_WIDTH_1024 0x04
139#define DEC_WIDTH_1152 0x05
140#define DEC_WIDTH_1280 0x06
141#define DEC_WIDTH_1600 0x07
142
143/* update mode */
144#define DEC_UPDATE_NONE 0x00
145#define DEC_UPDATE_TOP_RIGHT 0x01
146#define DEC_UPDATE_BOTTOM_LEFT 0x02
147#define DEC_UPDATE_LASTPIX 0x03
148
149/* quickstart mode - operation starts as soon as given register is written to */
150#define DEC_START_DIMX 0x01
151#define DEC_START_SRC 0x02
152#define DEC_START_DST 0x03
153
154/* ROP */
155#define ROP_DST 0x66
156#define ROP_SRC 0xcc
157#define ROP_INV 0x33
158#define ROP_PATTERN 0xf0
159
160/*
161 * Configuration Registers
162 */
163
164#define ATR_PIXEL 0x0080 /* byte access */
165#define PIXEL_DEPTH_MASK 0x0f
166#define PIXEL_DEPTH_SHIFT 0
167
168/* pixel depth */
169#define PIXEL_4 0x01
170#define PIXEL_8 0x02
171#define PIXEL_15 0x0c
172#define PIXEL_16 0x0d
173#define PIXEL_24 0x0e
174#define PIXEL_32 0x0f
175
176#define ATR_APERTURE 0x00c0 /* short access */
177
178/*
179 * DPMS Control
180 */
181
182#define ATR_DPMS 0x00d0 /* byte access */
183#define DPMS_HSYNC_DISABLE 0x01
184#define DPMS_VSYNC_DISABLE 0x02
185#define DPMS_SYNC_DISABLE_ALL 0x03
186
187/*
188 * RAMDAC
189 */
190
191#define ATR_COLOR_CORRECTION 0x00e0
192#define ATR_MCLK 0x00e8
193#define ATR_PCLK 0x00ec
194
195/*
196 * Hardware Cursor
197 *
198 * The position can not become negative; the offset register, encoded as
199 * (signed y delta << 8) | signed x delta, allow the cursor image to
200 * cross the upper-left corner.
201 */
202
203#define ATR_CURSOR_ENABLE 0x0140
204#define ATR_CURSOR_FG 0x0141 /* 3:3:2 */
205#define ATR_CURSOR_BG 0x0142 /* 3:3:2 */
206#define ATR_CURSOR_ADDRESS 0x0144 /* in KB from vram */
207#define ATR_CURSOR_POSITION 0x0148
208#define ATR_CURSOR_HOTSPOT 0x014c /* short access */
209
210/*
211 * Identification Register
212 */
213
214#define ATR_ID 0x0182
215#define ID_AP6422 0x6422
216#define ID_AT24 0x6424
217#define ID_AT3D 0x643d
218
219/*
220 * Status Registers
221 */
222
223#define ATR_FIFO_STATUS 0x01fc
224#define ATR_BLT_STATUS 0x01fd
225#define FIFO_MASK 0x0f
226#define FIFO_SHIFT 0
227#define FIFO_AP6422 4
228#define FIFO_AT24 8
229
230#define BLT_HOST_BUSY 0x01
231#define BLT_ENGINE_BUSY 0x04
232
233#define MGX_REG_ATREG_OFFSET 0x000b0000
234
235#endif /* MGX_REG_H */