1/* $NetBSD: mips1_pte.h,v 1.21 2020/07/26 08:08:41 simonb Exp $ */
2
3/*
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department and Ralph Campbell.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: Utah Hdr: pte.h 1.11 89/09/03
37 *
38 * @(#)pte.h 8.1 (Berkeley) 6/10/93
39 */
40
41#ifndef _MIPS_MIPS1_PTE_H_
42#define _MIPS_MIPS1_PTE_H_
43/*
44 * R2000 hardware page table entry
45 */
46
47#ifndef _LOCORE
48#if 0
49struct mips1_pte {
50#if BYTE_ORDER == BIG_ENDIAN
51unsigned int pg_pfnum:20, /* HW: core page frame number or 0 */
52 pg_n:1, /* HW: non-cacheable bit */
53 pg_m:1, /* HW: dirty bit */
54 pg_v:1, /* HW: valid bit */
55 pg_g:1, /* HW: ignore pid bit */
56 :4,
57 pg_swapm:1, /* SW: page must be forced to swap */
58 pg_fod:1, /* SW: is fill on demand (=0) */
59 pg_prot:2; /* SW: access control */
60#endif
61#if BYTE_ORDER == LITTLE_ENDIAN
62unsigned int pg_prot:2, /* SW: access control */
63 pg_fod:1, /* SW: is fill on demand (=0) */
64 pg_swapm:1, /* SW: page must be forced to swap */
65 :4,
66 pg_g:1, /* HW: ignore pid bit */
67 pg_v:1, /* HW: valid bit */
68 pg_m:1, /* HW: dirty bit */
69 pg_n:1, /* HW: non-cacheable bit */
70 pg_pfnum:20; /* HW: core page frame number or 0 */
71#endif
72};
73#endif
74#endif /* _LOCORE */
75
76#define MIPS1_PG_PROT 0x00000003
77#define MIPS1_PG_RW 0x00000000
78#define MIPS1_PG_RO 0x00000001
79#define MIPS1_PG_WIRED 0x00000002
80#define MIPS1_PG_G 0x00000100
81#define MIPS1_PG_V 0x00000200
82#define MIPS1_PG_NV 0x00000000
83#define MIPS1_PG_D 0x00000400
84#define MIPS1_PG_N 0x00000800
85#define MIPS1_PG_FRAME 0xfffff000
86#define MIPS1_PG_SHIFT 12
87#define MIPS1_PG_PFNUM(x) (((x) & MIPS1_PG_FRAME) >> MIPS1_PG_SHIFT)
88
89#define MIPS1_PG_ROPAGE MIPS1_PG_V
90#define MIPS1_PG_RWPAGE MIPS1_PG_D
91#define MIPS1_PG_CWPAGE 0
92#define MIPS1_PG_RWNCPAGE (MIPS1_PG_D | MIPS1_PG_N)
93#define MIPS1_PG_CWNCPAGE MIPS1_PG_N
94#define MIPS1_PG_IOPAGE (MIPS1_PG_D | MIPS1_PG_N)
95
96#define mips1_tlbpfn_to_paddr(x) ((x) & MIPS1_PG_FRAME)
97#define mips1_paddr_to_tlbpfn(x) (x)
98
99#define MIPS1_PTE_TO_PADDR(pte) ((unsigned)(pte) & MIPS1_PG_FRAME)
100#define MIPS1_PAGE_IS_RDONLY(pte,va) ((int)(pte) & MIPS1_PG_RO)
101
102#endif /* !_MIPS_MIPS1_PTE_H_ */