1/* $NetBSD: reg.h,v 1.10 2022/12/13 22:25:08 skrll Exp $ */
2
3/*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _RISCV_REG_H_
33#define _RISCV_REG_H_
34
35// x0 = 0
36// x1 = ra (return address) Caller
37// x2 = sp (stack pointer) Callee
38// x3 = gp (global pointer)
39// x4 = tp (thread pointer)
40// x5 - x7 = t0 - t2 (temporary) Caller
41// x8 = s0/fp (saved register / frame pointer) Callee
42// x9 = s1 (saved register) Callee
43// x10 - x11 = a0 - a1 (arguments/return values) Caller
44// x12 - x17 = a2 - a7 (arguments) Caller
45// x18 - x27 = s2 - s11 (saved registers) Callee
46// x28 - x31 = t3 - t6 (temporaries) Caller
47
48struct reg { // synced with register_t in <riscv/types.h>
49#ifdef _LP64
50 __uint64_t r_reg[31]; /* x0 is always 0 */
51 __uint64_t r_pc;
52#else
53 __uint32_t r_reg[31]; /* x0 is always 0 */
54 __uint32_t r_pc;
55#endif
56};
57
58#ifdef _LP64
59struct reg32 { // synced with register_t in <riscv/types.h>
60 __uint32_t r_reg[31]; /* x0 is always 0 */
61 __uint32_t r_pc;
62};
63#endif
64
65#define _XREG(n) ((n) - 1)
66#define _X_RA _XREG(1)
67#define _X_SP _XREG(2)
68#define _X_GP _XREG(3)
69#define _X_TP _XREG(4)
70#define _X_T0 _XREG(5)
71#define _X_T1 _XREG(6)
72#define _X_T2 _XREG(7)
73#define _X_S0 _XREG(8)
74#define _X_S1 _XREG(9)
75#define _X_A0 _XREG(10)
76#define _X_A1 _XREG(11)
77#define _X_A2 _XREG(12)
78#define _X_A3 _XREG(13)
79#define _X_A4 _XREG(14)
80#define _X_A5 _XREG(15)
81#define _X_A6 _XREG(16)
82#define _X_A7 _XREG(17)
83#define _X_S2 _XREG(18)
84#define _X_S3 _XREG(19)
85#define _X_S4 _XREG(20)
86#define _X_S5 _XREG(21)
87#define _X_S6 _XREG(22)
88#define _X_S7 _XREG(23)
89#define _X_S8 _XREG(24)
90#define _X_S9 _XREG(25)
91#define _X_S10 _XREG(26)
92#define _X_S11 _XREG(27)
93#define _X_T3 _XREG(28)
94#define _X_T4 _XREG(29)
95#define _X_T5 _XREG(30)
96#define _X_T6 _XREG(31)
97
98// f0 - f7 = ft0 - ft7 (FP temporaries) Caller
99// following layout is similar to integer registers above
100// f8 - f9 = fs0 - fs1 (FP saved registers) Callee
101// f10 - f11 = fa0 - fa1 (FP arguments/return values) Caller
102// f12 - f17 = fa2 - fa7 (FP arguments) Caller
103// f18 - f27 = fs2 - fa11 (FP saved registers) Callee
104// f28 - f31 = ft8 - ft11 (FP temporaries) Caller
105
106/*
107 * This fragment is common to <riscv/mcontext.h> and <riscv/reg.h>
108 */
109#ifndef _BSD_FPREG_T_
110union __fpreg {
111 __uint64_t u_u64;
112 double u_d;
113};
114#define _BSD_FPREG_T_ union __fpreg
115#endif
116
117/*
118 * 32 double precision floating point, 1 CSR
119 */
120struct fpreg {
121 _BSD_FPREG_T_ r_fpreg[33];
122};
123#define r_fcsr r_fpreg[32].u_u64
124
125#endif /* _RISCV_REG_H_ */