1/* $OpenBSD: cache.h,v 1.9 2016/12/21 13:59:57 visa Exp $ */
2
3/*
4 * Copyright (c) 2012 Miodrag Vallat.
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#ifndef _MIPS64_CACHE_H_
20#define _MIPS64_CACHE_H_
21
22/*
23 * Declare canonical cache functions for a given processor.
24 *
25 * The following assumptions are made:
26 * - only L1 has split instruction and data caches.
27 * - L1 I$ is virtually indexed.
28 *
29 * Processor-specific routines will make extra assumptions.
30 */
31
32#define CACHE_PROTOS(chip) \
33/* Figure out cache configuration */ \
34void chip##_ConfigCache(struct cpu_info *); \
35/* Writeback and invalidate all caches */ \
36void chip##_SyncCache(struct cpu_info *); \
37/* Invalidate all I$ for the given range */ \
38void chip##_InvalidateICache(struct cpu_info *, vaddr_t, size_t); \
39/* Register a given page for I$ invalidation */ \
40void chip##_InvalidateICachePage(struct cpu_info *, vaddr_t); \
41/* Perform postponed I$ invalidation */ \
42void chip##_SyncICache(struct cpu_info *); \
43/* Writeback all D$ for the given page */ \
44void chip##_SyncDCachePage(struct cpu_info *, vaddr_t, paddr_t); \
45/* Writeback all D$ for the (currently mapped) given page */ \
46void chip##_HitSyncDCachePage(struct cpu_info *, vaddr_t, paddr_t); \
47/* Writeback all D$ for the given range */ \
48void chip##_HitSyncDCache(struct cpu_info *, vaddr_t, size_t); \
49/* Invalidate all D$ for the given range */ \
50void chip##_HitInvalidateDCache(struct cpu_info *, vaddr_t, size_t); \
51/* Enforce coherency of the given range */ \
52void chip##_IOSyncDCache(struct cpu_info *, vaddr_t, size_t, int);
53
54/*
55 * Cavium Octeon.
56 */
57CACHE_PROTOS(Octeon)
58
59void Octeon_lock_secondary_cache(struct cpu_info *, paddr_t, size_t);
60void Octeon_unlock_secondary_cache(struct cpu_info *, paddr_t, size_t);
61
62/*
63 * STC Loongson 2E and 2F.
64 */
65CACHE_PROTOS(Loongson2)
66
67/*
68 * Loongson 3A and 2Gq.
69 */
70CACHE_PROTOS(Loongson3)
71
72/*
73 * MIPS R4000 and R4400.
74 */
75CACHE_PROTOS(Mips4k)
76
77/*
78 * IDT/QED/PMC-Sierra R4600, R4700, R5000, RM52xx, RM7xxx, RM9xxx.
79 */
80CACHE_PROTOS(Mips5k)
81
82/*
83 * MIPS (SGI, really) R8000.
84 */
85CACHE_PROTOS(tfp)
86
87/*
88 * MIPS/NEC R10000/R120000/R140000/R16000.
89 */
90CACHE_PROTOS(Mips10k)
91
92/*
93 * mips64r2-compliant processors.
94 */
95CACHE_PROTOS(mips64r2)
96
97/*
98 * Values used by the IOSyncDCache routine [which acts as the backend of
99 * bus_dmamap_sync()].
100 */
101#define CACHE_SYNC_R 0 /* WB invalidate, WT invalidate */
102#define CACHE_SYNC_W 1 /* WB writeback, WT unaffected */
103#define CACHE_SYNC_X 2 /* WB writeback + invalidate, WT invalidate */
104
105extern vaddr_t cache_valias_mask;
106
107#endif /* _MIPS64_CACHE_H_ */