1/* $OpenBSD: mips_cpu.h,v 1.11 2022/12/11 05:07:25 visa Exp $ */
2
3/*-
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * Copyright (C) 1989 Digital Equipment Corporation.
35 * Permission to use, copy, modify, and distribute this software and
36 * its documentation for any purpose and without fee is hereby granted,
37 * provided that the above copyright notice appears in all copies.
38 * Digital Equipment Corporation makes no representations about the
39 * suitability of this software for any purpose. It is provided "as is"
40 * without express or implied warranty.
41 *
42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94
43 */
44
45#ifndef _MIPS64_CPUREGS_H_
46#define _MIPS64_CPUREGS_H_
47
48#if defined(_KERNEL) || defined(_STANDALONE)
49
50/*
51 * Status register.
52 */
53
54#define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */
55#define SR_COP_0_BIT 0x10000000
56#define SR_COP_1_BIT 0x20000000
57#define SR_COP_2_BIT 0x40000000
58#define SR_RP 0x08000000
59#define SR_FR_32 0x04000000
60#define SR_RE 0x02000000
61#define SR_DSD 0x01000000 /* Only on R12000 */
62#define SR_BOOT_EXC_VEC 0x00400000
63#define SR_TLB_SHUTDOWN 0x00200000
64#define SR_SOFT_RESET 0x00100000
65#define SR_DIAG_CH 0x00040000
66#define SR_DIAG_CE 0x00020000
67#define SR_DIAG_DE 0x00010000
68#define SR_KX 0x00000080
69#define SR_SX 0x00000040
70#define SR_UX 0x00000020
71#define SR_ERL 0x00000004
72#define SR_EXL 0x00000002
73#define SR_INT_ENAB 0x00000001
74
75#define SOFT_INT_MASK_0 0x00000100
76#define SOFT_INT_MASK_1 0x00000200
77#define SR_INT_MASK_0 0x00000400
78#define SR_INT_MASK_1 0x00000800
79#define SR_INT_MASK_2 0x00001000
80#define SR_INT_MASK_3 0x00002000
81#define SR_INT_MASK_4 0x00004000
82#define SR_INT_MASK_5 0x00008000
83
84#define SR_XX 0x80000000
85#define SR_KSU_MASK 0x00000018
86#define SR_KSU_SUPER 0x00000008
87#define SR_KSU_KERNEL 0x00000000
88#define SR_INT_MASK 0x0000ff00
89/* SR_KSU_USER is in <mips64/cpu.h> for CLKF_USERMODE() */
90#ifndef SR_KSU_USER
91#define SR_KSU_USER 0x00000010
92#endif
93
94#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1)
95
96/*
97 * Cause register.
98 */
99
100#define CR_BR_DELAY 0x80000000
101#define CR_BR_DELAY_SHIFT 31
102#define CR_EXC_CODE 0x0000007c
103#define CR_EXC_CODE_SHIFT 2
104#define CR_COP_ERR 0x30000000
105#define CR_COP1_ERR 0x10000000
106#define CR_COP2_ERR 0x20000000
107#define CR_COP3_ERR 0x20000000
108#define CR_INT_SOFT0 0x00000100
109#define CR_INT_SOFT1 0x00000200
110#define CR_INT_0 0x00000400
111#define CR_INT_1 0x00000800
112#define CR_INT_2 0x00001000
113#define CR_INT_3 0x00002000
114#define CR_INT_4 0x00004000
115#define CR_INT_5 0x00008000
116
117#define CR_INT_MASK 0x003fff00
118
119/*
120 * Config register.
121 */
122
123#define CFGR_CCA_MASK 0x00000007
124#define CFGR_CU 0x00000008
125#define CFGR_ICE 0x0000000200000000
126#define CFGR_SMM 0x0000000400000000
127
128/*
129 * Location of exception vectors.
130 */
131
132#define RESET_EXC_VEC (CKSEG1_BASE + 0x1fc00000)
133#define TLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000000)
134#define XTLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000080)
135#define CACHE_ERR_EXC_VEC (CKSEG1_BASE + 0x00000100)
136#define GEN_EXC_VEC (CKSEG1_BASE + 0x00000180)
137
138/*
139 * Coprocessor 0 registers
140 */
141
142/* Common subset */
143#define COP_0_COUNT $9
144#define COP_0_TLB_HI $10
145#define COP_0_STATUS_REG $12
146#define COP_0_CAUSE_REG $13
147#define COP_0_EXC_PC $14
148#define COP_0_PRID $15
149#define COP_0_CONFIG $16
150
151/* MIPS64 release 2 */
152#define COP_0_USERLOCAL $4, 2
153#define COP_0_TLB_PG_GRAIN $5, 1
154#define COP_0_EBASE $15, 1
155
156/* R4000/5000/10000 */
157#define COP_0_TLB_INDEX $0
158#define COP_0_TLB_RANDOM $1
159#define COP_0_TLB_LO0 $2
160#define COP_0_TLB_LO1 $3
161#define COP_0_TLB_CONTEXT $4
162#define COP_0_TLB_PG_MASK $5
163#define COP_0_TLB_WIRED $6
164#define COP_0_BAD_VADDR $8
165#define COP_0_COMPARE $11
166#define COP_0_LLADDR $17
167#define COP_0_WATCH_LO $18
168#define COP_0_WATCH_HI $19
169#define COP_0_TLB_XCONTEXT $20
170#define COP_0_ECC $26
171#define COP_0_CACHE_ERR $27
172#define COP_0_TAG_LO $28
173#define COP_0_TAG_HI $29
174#define COP_0_ERROR_PC $30
175
176/* Loongson-2 specific */
177#define COP_0_DIAG $22
178
179/* Octeon specific */
180#define COP_0_CVMCTL $9, 7
181#define COP_0_CVMMEMCTL $11, 7
182
183/*
184 * COP_0_COUNT speed divider.
185 */
186#if defined(CPU_OCTEON)
187#define CP0_CYCLE_DIVIDER 1
188#else
189#define CP0_CYCLE_DIVIDER 2
190#endif
191
192/*
193 * The floating point version and status registers.
194 */
195#define FPC_ID $0
196#define FPC_CSR $31
197
198/*
199 * Config1 register
200 */
201#define CONFIG1_M 0x80000000u
202#define CONFIG1_MMUSize1 0x7e000000u
203#define CONFIG1_MMUSize1_SHIFT 25
204#define CONFIG1_IS 0x01c00000u
205#define CONFIG1_IS_SHIFT 22
206#define CONFIG1_IL 0x00380000u
207#define CONFIG1_IL_SHIFT 19
208#define CONFIG1_IA 0x00070000u
209#define CONFIG1_IA_SHIFT 16
210#define CONFIG1_DS 0x0000e000u
211#define CONFIG1_DS_SHIFT 13
212#define CONFIG1_DL 0x00001c00u
213#define CONFIG1_DL_SHIFT 10
214#define CONFIG1_DA 0x00000380u
215#define CONFIG1_DA_SHIFT 7
216#define CONFIG1_C2 0x00000040u
217#define CONFIG1_MD 0x00000020u
218#define CONFIG1_PC 0x00000010u
219#define CONFIG1_WR 0x00000008u
220#define CONFIG1_CA 0x00000004u
221#define CONFIG1_EP 0x00000002u
222#define CONFIG1_FP 0x00000001u
223
224/*
225 * Config3 register
226 */
227#define CONFIG3_M 0x80000000
228#define CONFIG3_BPG 0x40000000
229#define CONFIG3_CMGCR 0x20000000
230#define CONFIG3_IPLW 0x00600000
231#define CONFIG3_MMAR 0x001c0000
232#define CONFIG3_MCU 0x00020000
233#define CONFIG3_ISAOnExc 0x00010000
234#define CONFIG3_ISA 0x0000c000
235#define CONFIG3_ULRI 0x00002000
236#define CONFIG3_RXI 0x00001000
237#define CONFIG3_DSP2P 0x00000800
238#define CONFIG3_DSPP 0x00000400
239#define CONFIG3_CTXTC 0x00000200
240#define CONFIG3_ITL 0x00000100
241#define CONFIG3_LPA 0x00000080
242#define CONFIG3_VEIC 0x00000040
243#define CONFIG3_VInt 0x00000020
244#define CONFIG3_SP 0x00000010
245#define CONFIG3_CDMM 0x00000008
246#define CONFIG3_MT 0x00000004
247#define CONFIG3_SM 0x00000002
248#define CONFIG3_TL 0x00000001
249
250/*
251 * Config4 register
252 */
253#define CONFIG4_M 0x80000000u
254#define CONFIG4_IE 0x60000000u
255#define CONFIG4_AE 0x10000000u
256#define CONFIG4_VTLBSizeExt 0x0f000000u /* when MMUExtDef=3 */
257#define CONFIG4_KScrExist 0x00ff0000u
258#define CONFIG4_MMUExtDef 0x0000c000u
259#define CONFIG4_MMUExtDef_SHIFT 14
260#define CONFIG4_FTLBPageSize 0x00001f00u /* when MMUExtDef=2 or 3 */
261#define CONFIG4_FTLBWays 0x000000f0u /* when MMUExtDef=2 or 3 */
262#define CONFIG4_FTLBSets 0x0000000fu /* when MMUExtDef=2 or 3 */
263#define CONFIG4_MMUSizeExt 0x000000ffu /* when MMUExtDef=1 */
264
265/*
266 * PageGrain register
267 */
268#define PGRAIN_RIE 0x80000000
269#define PGRAIN_XIE 0x40000000
270#define PGRAIN_ELPA 0x20000000
271#define PGRAIN_ESP 0x10000000
272#define PGRAIN_IEC 0x08000000
273
274/*
275 * HWREna register
276 */
277#define HWRENA_ULR 0x20000000u
278#define HWRENA_CC 0x00000004u
279
280#endif /* _KERNEL || _STANDALONE */
281
282#endif /* !_MIPS64_CPUREGS_H_ */