1/* $NetBSD: cacheops_30.h,v 1.10 2023/09/26 12:46:30 tsutsui Exp $ */
2
3/*-
4 * Copyright (c) 1997 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Leo Weppelman
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * Invalidate entire TLB.
34 */
35static __inline void __attribute__((__unused__))
36TBIA_30(void)
37{
38 int tmp = DC_CLEAR;
39
40 __asm volatile (" pflusha;"
41 " movc %0,%%cacr" : : "d" (tmp));
42}
43
44/*
45 * Invalidate any TLB entry for given VA (TB Invalidate Single)
46 */
47static __inline void __attribute__((__unused__))
48TBIS_30(vaddr_t va)
49{
50 __asm volatile (" pflush #0,#0,%0@;"
51 " movc %1,%%cacr" : : "a" (va), "d" (DC_CLEAR));
52}
53
54/*
55 * Invalidate supervisor side of TLB
56 */
57static __inline void __attribute__((__unused__))
58TBIAS_30(void)
59{
60 __asm volatile (" pflush #4,#4;"
61 " movc %0,%%cacr;" :: "d" (DC_CLEAR));
62}
63
64/*
65 * Invalidate user side of TLB
66 */
67static __inline void __attribute__((__unused__))
68TBIAU_30(void)
69{
70 __asm volatile (" pflush #0,#4;"
71 " movc %0,%%cacr;" :: "d" (DC_CLEAR));
72}
73
74/*
75 * Invalidate instruction cache
76 */
77static __inline void __attribute__((__unused__))
78ICIA_30(void)
79{
80 __asm volatile (" movc %0,%%cacr;" : : "d" (IC_CLEAR));
81}
82
83static __inline void __attribute__((__unused__))
84ICPA_30(void)
85{
86 __asm volatile (" movc %0,%%cacr;" : : "d" (IC_CLEAR));
87}
88
89/*
90 * Invalidate data cache.
91 * NOTE: we do not flush 68030/20 on-chip cache as there are no aliasing
92 * problems with DC_WA. The only cases we have to worry about are context
93 * switch and TLB changes, both of which are handled "in-line" in resume
94 * and TBI*.
95 */
96#define DCIA_30()
97#define DCIS_30()
98#define DCIU_30()
99#define DCIAS_30(va)
100#define DCFA_30()
101#define DCPA_30()
102
103static __inline void __attribute__((__unused__))
104PCIA_30(void)
105{
106 __asm volatile (" movc %0,%%cacr;" : : "d" (DC_CLEAR));
107}