1/* $OpenBSD: bus.h,v 1.8 2020/04/14 17:35:28 kettenis Exp $ */
2
3/*
4 * Copyright (c) 2003-2004 Opsycon AB Sweden. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#ifndef _MACHINE_BUS_H_
28#define _MACHINE_BUS_H_
29
30#ifdef __STDC__
31#define CAT(a,b) a##b
32#define CAT3(a,b,c) a##b##c
33#else
34#define CAT(a,b) a/**/b
35#define CAT3(a,b,c) a/**/b/**/c
36#endif
37
38/*
39 * Bus access types.
40 */
41struct mips_bus_space;
42typedef u_long bus_addr_t;
43typedef u_long bus_size_t;
44typedef u_long bus_space_handle_t;
45typedef struct mips_bus_space *bus_space_tag_t;
46typedef struct mips_bus_space bus_space_t;
47
48struct mips_bus_space {
49 bus_addr_t bus_base;
50 void *bus_private;
51 u_int8_t (*_space_read_1)(bus_space_tag_t , bus_space_handle_t,
52 bus_size_t);
53 void (*_space_write_1)(bus_space_tag_t , bus_space_handle_t,
54 bus_size_t, u_int8_t);
55 u_int16_t (*_space_read_2)(bus_space_tag_t , bus_space_handle_t,
56 bus_size_t);
57 void (*_space_write_2)(bus_space_tag_t , bus_space_handle_t,
58 bus_size_t, u_int16_t);
59 u_int32_t (*_space_read_4)(bus_space_tag_t , bus_space_handle_t,
60 bus_size_t);
61 void (*_space_write_4)(bus_space_tag_t , bus_space_handle_t,
62 bus_size_t, u_int32_t);
63 u_int64_t (*_space_read_8)(bus_space_tag_t , bus_space_handle_t,
64 bus_size_t);
65 void (*_space_write_8)(bus_space_tag_t , bus_space_handle_t,
66 bus_size_t, u_int64_t);
67 void (*_space_read_raw_2)(bus_space_tag_t, bus_space_handle_t,
68 bus_addr_t, u_int8_t *, bus_size_t);
69 void (*_space_write_raw_2)(bus_space_tag_t, bus_space_handle_t,
70 bus_addr_t, const u_int8_t *, bus_size_t);
71 void (*_space_read_raw_4)(bus_space_tag_t, bus_space_handle_t,
72 bus_addr_t, u_int8_t *, bus_size_t);
73 void (*_space_write_raw_4)(bus_space_tag_t, bus_space_handle_t,
74 bus_addr_t, const u_int8_t *, bus_size_t);
75 void (*_space_read_raw_8)(bus_space_tag_t, bus_space_handle_t,
76 bus_addr_t, u_int8_t *, bus_size_t);
77 void (*_space_write_raw_8)(bus_space_tag_t, bus_space_handle_t,
78 bus_addr_t, const u_int8_t *, bus_size_t);
79 int (*_space_map)(bus_space_tag_t , bus_addr_t,
80 bus_size_t, int, bus_space_handle_t *);
81 void (*_space_unmap)(bus_space_tag_t, bus_space_handle_t,
82 bus_size_t);
83 int (*_space_subregion)(bus_space_tag_t, bus_space_handle_t,
84 bus_size_t, bus_size_t, bus_space_handle_t *);
85 void * (*_space_vaddr)(bus_space_tag_t, bus_space_handle_t);
86};
87
88#define bus_space_read_1(t, h, o) (*(t)->_space_read_1)((t), (h), (o))
89#define bus_space_read_2(t, h, o) (*(t)->_space_read_2)((t), (h), (o))
90#define bus_space_read_4(t, h, o) (*(t)->_space_read_4)((t), (h), (o))
91#define bus_space_read_8(t, h, o) (*(t)->_space_read_8)((t), (h), (o))
92
93#define bus_space_write_1(t, h, o, v) (*(t)->_space_write_1)((t), (h), (o), (v))
94#define bus_space_write_2(t, h, o, v) (*(t)->_space_write_2)((t), (h), (o), (v))
95#define bus_space_write_4(t, h, o, v) (*(t)->_space_write_4)((t), (h), (o), (v))
96#define bus_space_write_8(t, h, o, v) (*(t)->_space_write_8)((t), (h), (o), (v))
97
98#define bus_space_read_raw_multi_2(t, h, a, b, l) \
99 (*(t)->_space_read_raw_2)((t), (h), (a), (b), (l))
100#define bus_space_read_raw_multi_4(t, h, a, b, l) \
101 (*(t)->_space_read_raw_4)((t), (h), (a), (b), (l))
102#define bus_space_read_raw_multi_8(t, h, a, b, l) \
103 (*(t)->_space_read_raw_8)((t), (h), (a), (b), (l))
104
105#define bus_space_write_raw_multi_2(t, h, a, b, l) \
106 (*(t)->_space_write_raw_2)((t), (h), (a), (b), (l))
107#define bus_space_write_raw_multi_4(t, h, a, b, l) \
108 (*(t)->_space_write_raw_4)((t), (h), (a), (b), (l))
109#define bus_space_write_raw_multi_8(t, h, a, b, l) \
110 (*(t)->_space_write_raw_8)((t), (h), (a), (b), (l))
111
112#define bus_space_map(t, o, s, c, p) (*(t)->_space_map)((t), (o), (s), (c), (p))
113#define bus_space_unmap(t, h, s) (*(t)->_space_unmap)((t), (h), (s))
114#define bus_space_subregion(t, h, o, s, p) \
115 (*(t)->_space_subregion)((t), (h), (o), (s), (p))
116
117#define BUS_SPACE_MAP_CACHEABLE 0x01
118#define BUS_SPACE_MAP_KSEG0 0x02
119#define BUS_SPACE_MAP_LINEAR 0x04
120#define BUS_SPACE_MAP_PREFETCHABLE 0x08
121
122#define bus_space_vaddr(t, h) (*(t)->_space_vaddr)((t), (h))
123
124/*----------------------------------------------------------------------------*/
125#define bus_space_read_multi(n,m) \
126static __inline void \
127CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
128 bus_size_t o, CAT3(u_int,m,_t) *x, size_t cnt) \
129{ \
130 while (cnt--) \
131 *x++ = CAT(bus_space_read_,n)(bst, bsh, o); \
132}
133
134bus_space_read_multi(1,8)
135bus_space_read_multi(2,16)
136bus_space_read_multi(4,32)
137bus_space_read_multi(8,64)
138
139/*----------------------------------------------------------------------------*/
140#define bus_space_read_region(n,m) \
141static __inline void \
142CAT(bus_space_read_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
143 bus_addr_t ba, CAT3(u_int,m,_t) *x, size_t cnt) \
144{ \
145 while (cnt--) { \
146 *x++ = CAT(bus_space_read_,n)(bst, bsh, ba); \
147 ba += (n); \
148 } \
149}
150
151bus_space_read_region(1,8)
152bus_space_read_region(2,16)
153bus_space_read_region(4,32)
154bus_space_read_region(8,64)
155
156/*----------------------------------------------------------------------------*/
157#define bus_space_read_raw_region(n,m) \
158static __inline void \
159CAT(bus_space_read_raw_region_,n)(bus_space_tag_t bst, \
160 bus_space_handle_t bsh, \
161 bus_addr_t ba, u_int8_t *x, size_t cnt) \
162{ \
163 cnt >>= ((n) >> 1); \
164 while (cnt--) { \
165 CAT(bus_space_read_raw_multi_,n)(bst, bsh, ba, x, (n)); \
166 ba += (n); \
167 x += (n); \
168 } \
169}
170
171bus_space_read_raw_region(2,16)
172bus_space_read_raw_region(4,32)
173bus_space_read_raw_region(8,64)
174
175/*----------------------------------------------------------------------------*/
176#define bus_space_write_multi(n,m) \
177static __inline void \
178CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
179 bus_size_t o, const CAT3(u_int,m,_t) *x, size_t cnt) \
180{ \
181 while (cnt--) \
182 CAT(bus_space_write_,n)(bst, bsh, o, *x++); \
183}
184
185bus_space_write_multi(1,8)
186bus_space_write_multi(2,16)
187bus_space_write_multi(4,32)
188bus_space_write_multi(8,64)
189
190/*----------------------------------------------------------------------------*/
191#define bus_space_write_region(n,m) \
192static __inline void \
193CAT(bus_space_write_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
194 bus_addr_t ba, const CAT3(u_int,m,_t) *x, size_t cnt) \
195{ \
196 while (cnt--) { \
197 CAT(bus_space_write_,n)(bst, bsh, ba, *x++); \
198 ba += (n); \
199 } \
200}
201
202bus_space_write_region(1,8)
203bus_space_write_region(2,16)
204bus_space_write_region(4,32)
205bus_space_write_region(8,64)
206
207/*----------------------------------------------------------------------------*/
208#define bus_space_write_raw_region(n,m) \
209static __inline void \
210CAT(bus_space_write_raw_region_,n)(bus_space_tag_t bst, \
211 bus_space_handle_t bsh, \
212 bus_addr_t ba, const u_int8_t *x, size_t cnt) \
213{ \
214 cnt >>= ((n) >> 1); \
215 while (cnt--) { \
216 CAT(bus_space_write_raw_multi_,n)(bst, bsh, ba, x, (n)); \
217 ba += (n); \
218 x += (n); \
219 } \
220}
221
222bus_space_write_raw_region(2,16)
223bus_space_write_raw_region(4,32)
224bus_space_write_raw_region(8,64)
225
226/*----------------------------------------------------------------------------*/
227#define bus_space_set_region(n,m) \
228static __inline void \
229CAT(bus_space_set_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
230 bus_addr_t ba, CAT3(u_int,m,_t) x, size_t cnt) \
231{ \
232 while (cnt--) { \
233 CAT(bus_space_write_,n)(bst, bsh, ba, x); \
234 ba += (n); \
235 } \
236}
237
238bus_space_set_region(1,8)
239bus_space_set_region(2,16)
240bus_space_set_region(4,32)
241bus_space_set_region(8,64)
242
243/*----------------------------------------------------------------------------*/
244static __inline void
245bus_space_copy_1(void *v, bus_space_handle_t h1, bus_size_t o1,
246 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
247{
248 char *s = (char *)(h1 + o1);
249 char *d = (char *)(h2 + o2);
250
251 while (c--)
252 *d++ = *s++;
253}
254
255
256static __inline void
257bus_space_copy_2(void *v, bus_space_handle_t h1, bus_size_t o1,
258 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
259{
260 short *s = (short *)(h1 + o1);
261 short *d = (short *)(h2 + o2);
262
263 while (c--)
264 *d++ = *s++;
265}
266
267static __inline void
268bus_space_copy_4(void *v, bus_space_handle_t h1, bus_size_t o1,
269 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
270{
271 int *s = (int *)(h1 + o1);
272 int *d = (int *)(h2 + o2);
273
274 while (c--)
275 *d++ = *s++;
276}
277
278static __inline void
279bus_space_copy_8(void *v, bus_space_handle_t h1, bus_size_t o1,
280 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
281{
282 int64_t *s = (int64_t *)(h1 + o1);
283 int64_t *d = (int64_t *)(h2 + o2);
284
285 while (c--)
286 *d++ = *s++;
287}
288
289/*----------------------------------------------------------------------------*/
290/*
291 * Bus read/write barrier methods.
292 *
293 * void bus_space_barrier(bus_space_tag_t tag,
294 * bus_space_handle_t bsh, bus_size_t offset,
295 * bus_size_t len, int flags);
296 *
297 */
298static inline void
299bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offset,
300 bus_size_t length, int flags)
301{
302 __asm__ volatile ("sync" ::: "memory");
303}
304#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
305#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
306
307#define BUS_DMA_WAITOK 0x0000
308#define BUS_DMA_NOWAIT 0x0001
309#define BUS_DMA_ALLOCNOW 0x0002
310#define BUS_DMA_COHERENT 0x0008
311#define BUS_DMA_BUS1 0x0010 /* placeholders for bus functions... */
312#define BUS_DMA_BUS2 0x0020
313#define BUS_DMA_BUS3 0x0040
314#define BUS_DMA_BUS4 0x0080
315#define BUS_DMA_READ 0x0100 /* mapping is device -> memory only */
316#define BUS_DMA_WRITE 0x0200 /* mapping is memory -> device only */
317#define BUS_DMA_STREAMING 0x0400 /* hint: sequential, unidirectional */
318#define BUS_DMA_ZERO 0x0800 /* zero memory in dmamem_alloc */
319#define BUS_DMA_NOCACHE 0x1000
320#define BUS_DMA_64BIT 0x2000 /* device handles 64bit dva */
321
322/* Forwards needed by prototypes below. */
323struct mbuf;
324struct proc;
325struct uio;
326
327#define BUS_DMASYNC_POSTREAD 0x0001
328#define BUS_DMASYNC_POSTWRITE 0x0002
329#define BUS_DMASYNC_PREREAD 0x0004
330#define BUS_DMASYNC_PREWRITE 0x0008
331
332typedef struct machine_bus_dma_tag *bus_dma_tag_t;
333typedef struct machine_bus_dmamap *bus_dmamap_t;
334
335/*
336 * bus_dma_segment_t
337 *
338 * Describes a single contiguous DMA transaction. Values
339 * are suitable for programming into DMA registers.
340 */
341struct machine_bus_dma_segment {
342 bus_addr_t ds_addr; /* DMA address */
343 bus_size_t ds_len; /* length of transfer */
344
345 paddr_t _ds_paddr; /* CPU address */
346 vaddr_t _ds_vaddr; /* CPU address */
347};
348typedef struct machine_bus_dma_segment bus_dma_segment_t;
349
350/*
351 * bus_dma_tag_t
352 *
353 * A machine-dependent opaque type describing the implementation of
354 * DMA for a given bus.
355 */
356
357struct machine_bus_dma_tag {
358 void *_cookie; /* cookie used in the guts */
359
360 /*
361 * DMA mapping methods.
362 */
363 int (*_dmamap_create)(bus_dma_tag_t , bus_size_t, int,
364 bus_size_t, bus_size_t, int, bus_dmamap_t *);
365 void (*_dmamap_destroy)(bus_dma_tag_t , bus_dmamap_t);
366 int (*_dmamap_load)(bus_dma_tag_t , bus_dmamap_t, void *,
367 bus_size_t, struct proc *, int);
368 int (*_dmamap_load_mbuf)(bus_dma_tag_t , bus_dmamap_t,
369 struct mbuf *, int);
370 int (*_dmamap_load_uio)(bus_dma_tag_t , bus_dmamap_t,
371 struct uio *, int);
372 int (*_dmamap_load_raw)(bus_dma_tag_t , bus_dmamap_t,
373 bus_dma_segment_t *, int, bus_size_t, int);
374 int (*_dmamap_load_buffer)(bus_dma_tag_t, bus_dmamap_t, void *,
375 bus_size_t, struct proc *, int, paddr_t *, int *, int);
376 void (*_dmamap_unload)(bus_dma_tag_t , bus_dmamap_t);
377 void (*_dmamap_sync)(bus_dma_tag_t , bus_dmamap_t,
378 bus_addr_t, bus_size_t, int);
379
380 /*
381 * DMA memory utility functions.
382 */
383 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
384 bus_size_t, bus_dma_segment_t *, int, int *, int);
385 void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int);
386 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
387 int, size_t, caddr_t *, int);
388 void (*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
389 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
390 int, off_t, int, int);
391
392 /*
393 * internal memory address translation information.
394 */
395 bus_addr_t (*_pa_to_device)(paddr_t);
396 paddr_t (*_device_to_pa)(bus_addr_t);
397 bus_addr_t _dma_mask;
398};
399
400#define bus_dmamap_create(t, s, n, m, b, f, p) \
401 (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
402#define bus_dmamap_destroy(t, p) \
403 (*(t)->_dmamap_destroy)((t), (p))
404#define bus_dmamap_load(t, m, b, s, p, f) \
405 (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
406#define bus_dmamap_load_mbuf(t, m, b, f) \
407 (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
408#define bus_dmamap_load_uio(t, m, u, f) \
409 (*(t)->_dmamap_load_uio)((t), (m), (u), (f))
410#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
411 (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
412#define bus_dmamap_unload(t, p) \
413 (*(t)->_dmamap_unload)((t), (p))
414#define bus_dmamap_sync(t, p, a, l, o) \
415 (void)((t)->_dmamap_sync ? \
416 (*(t)->_dmamap_sync)((t), (p), (a), (l), (o)) : (void)0)
417
418#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
419 (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
420#define bus_dmamem_free(t, sg, n) \
421 (*(t)->_dmamem_free)((t), (sg), (n))
422#define bus_dmamem_map(t, sg, n, s, k, f) \
423 (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
424#define bus_dmamem_unmap(t, k, s) \
425 (*(t)->_dmamem_unmap)((t), (k), (s))
426#define bus_dmamem_mmap(t, sg, n, o, p, f) \
427 (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
428
429int _dmamap_create(bus_dma_tag_t, bus_size_t, int,
430 bus_size_t, bus_size_t, int, bus_dmamap_t *);
431void _dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
432int _dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
433 bus_size_t, struct proc *, int);
434int _dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int);
435int _dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int);
436int _dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
437 bus_dma_segment_t *, int, bus_size_t, int);
438int _dmamap_load_buffer(bus_dma_tag_t, bus_dmamap_t, void *,
439 bus_size_t, struct proc *, int, paddr_t *, int *, int);
440void _dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
441void _dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
442 bus_size_t, int);
443
444int _dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t,
445 bus_size_t, bus_dma_segment_t *, int, int *, int);
446void _dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int);
447int _dmamem_map(bus_dma_tag_t, bus_dma_segment_t *,
448 int, size_t, caddr_t *, int);
449void _dmamem_unmap(bus_dma_tag_t, caddr_t, size_t);
450paddr_t _dmamem_mmap(bus_dma_tag_t, bus_dma_segment_t *, int, off_t, int, int);
451int _dmamem_alloc_range(bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t,
452 bus_dma_segment_t *, int, int *, int, paddr_t, paddr_t);
453
454/*
455 * bus_dmamap_t
456 *
457 * Describes a DMA mapping.
458 */
459struct machine_bus_dmamap {
460 /*
461 * PRIVATE MEMBERS: not for use by machine-independent code.
462 */
463 bus_size_t _dm_size; /* largest DMA transfer mappable */
464 int _dm_segcnt; /* number of segs this map can map */
465 bus_size_t _dm_maxsegsz; /* largest possible segment */
466 bus_size_t _dm_boundary; /* don't cross this */
467 int _dm_flags; /* misc. flags */
468
469 void *_dm_cookie; /* cookie for bus-specific functions */
470
471 /*
472 * PUBLIC MEMBERS: these are used by machine-independent code.
473 */
474 bus_size_t dm_mapsize; /* size of the mapping */
475 int dm_nsegs; /* # valid segments in mapping */
476 bus_dma_segment_t dm_segs[1]; /* segments; variable length */
477};
478
479int generic_space_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
480 bus_space_handle_t *);
481void generic_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
482int generic_space_region(bus_space_tag_t, bus_space_handle_t, bus_size_t,
483 bus_size_t, bus_space_handle_t *);
484void *generic_space_vaddr(bus_space_tag_t, bus_space_handle_t);
485uint8_t generic_space_read_1(bus_space_tag_t, bus_space_handle_t, bus_size_t);
486uint16_t generic_space_read_2(bus_space_tag_t, bus_space_handle_t, bus_size_t);
487uint32_t generic_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);
488uint64_t generic_space_read_8(bus_space_tag_t, bus_space_handle_t, bus_size_t);
489void generic_space_read_raw_2(bus_space_tag_t, bus_space_handle_t,
490 bus_addr_t, uint8_t *, bus_size_t);
491void generic_space_write_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
492 uint8_t);
493void generic_space_write_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
494 uint16_t);
495void generic_space_write_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
496 uint32_t);
497void generic_space_write_8(bus_space_tag_t, bus_space_handle_t, bus_size_t,
498 uint64_t);
499void generic_space_write_raw_2(bus_space_tag_t, bus_space_handle_t,
500 bus_addr_t, const uint8_t *, bus_size_t);
501void generic_space_read_raw_4(bus_space_tag_t, bus_space_handle_t,
502 bus_addr_t, uint8_t *, bus_size_t);
503void generic_space_write_raw_4(bus_space_tag_t, bus_space_handle_t,
504 bus_addr_t, const uint8_t *, bus_size_t);
505void generic_space_read_raw_8(bus_space_tag_t, bus_space_handle_t,
506 bus_addr_t, uint8_t *, bus_size_t);
507void generic_space_write_raw_8(bus_space_tag_t, bus_space_handle_t,
508 bus_addr_t, const uint8_t *, bus_size_t);
509
510#endif /* _MACHINE_BUS_H_ */