1/* $OpenBSD: intr.h,v 1.23 2025/05/10 10:01:03 visa Exp $ */
2
3/*
4 * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29#ifndef _MACHINE_INTR_H_
30#define _MACHINE_INTR_H_
31
32#define __USE_MI_SOFTINTR
33
34#include <sys/softintr.h>
35
36/*
37 * The interrupt level ipl is a logical level; per-platform interrupt
38 * code will turn it into the appropriate hardware interrupt masks
39 * values.
40 *
41 * Interrupt sources on the CPU are kept enabled regardless of the
42 * current ipl value; individual hardware sources interrupting while
43 * logically masked are masked on the fly, remembered as pending, and
44 * unmasked at the first splx() opportunity.
45 *
46 * An exception to this rule is the clock interrupt. Clock interrupts
47 * are always allowed to happen, but will (of course!) not be serviced
48 * if logically masked. The reason for this is that clocks usually sit on
49 * INT5 and cannot be easily masked if external hardware masking is used.
50 */
51
52/* Interrupt priority `levels'; not mutually exclusive. */
53#define IPL_NONE 0 /* nothing */
54#define IPL_SOFTINT 1 /* soft interrupts */
55#define IPL_SOFTCLOCK 1 /* soft clock interrupts */
56#define IPL_SOFTNET 2 /* soft network interrupts */
57#define IPL_SOFTTTY 3 /* soft terminal interrupts */
58#define IPL_SOFTHIGH IPL_SOFTTTY /* highest level of soft interrupts */
59#define IPL_BIO 4 /* block I/O */
60#define IPL_AUDIO IPL_BIO
61#define IPL_NET 5 /* network */
62#define IPL_TTY 6 /* terminal */
63#define IPL_VM 7 /* memory allocation */
64#define IPL_CLOCK 8 /* clock */
65#define IPL_SCHED IPL_CLOCK
66#define IPL_HIGH 9 /* everything */
67#define IPL_IPI 10 /* interprocessor interrupt */
68#define NIPLS 11 /* number of levels */
69
70#define IPL_MPFLOOR IPL_TTY
71
72/* Interrupt priority 'flags'. */
73#define IPL_MPSAFE 0x100
74
75/* Interrupt sharing types. */
76#define IST_NONE 0 /* none */
77#define IST_PULSE 1 /* pulsed */
78#define IST_EDGE 2 /* edge-triggered */
79#define IST_LEVEL 3 /* level-triggered */
80
81#ifndef _LOCORE
82
83void softintr(int);
84
85#define splbio() splraise(IPL_BIO)
86#define splnet() splraise(IPL_NET)
87#define spltty() splraise(IPL_TTY)
88#define splaudio() splraise(IPL_AUDIO)
89#define splvm() splraise(IPL_VM)
90#define splclock() splraise(IPL_CLOCK)
91#define splsched() splraise(IPL_SCHED)
92#define splhigh() splraise(IPL_HIGH)
93
94#define splsoftclock() splraise(IPL_SOFTCLOCK)
95#define splsoftnet() splraise(IPL_SOFTNET)
96#define splstatclock() splhigh()
97
98#define spl0() spllower(0)
99
100void splinit(void);
101
102#ifdef DIAGNOSTIC
103/*
104 * Although this function is implemented in MI code, it must be in this MD
105 * header because we don't want this header to include MI includes.
106 */
107void splassert_fail(int, int, const char *);
108extern int splassert_ctl;
109void splassert_check(int, const char *);
110#define splassert(__wantipl) do { \
111 if (splassert_ctl > 0) { \
112 splassert_check(__wantipl, __func__); \
113 } \
114} while (0)
115#define splsoftassert(wantipl) splassert(wantipl)
116#else
117#define splassert(X)
118#define splsoftassert(X)
119#endif
120
121void register_splx_handler(void (*)(int));
122int splraise(int);
123void splx(int);
124int spllower(int);
125
126void intr_barrier(void *);
127
128/*
129 * Low level interrupt dispatcher registration data.
130 */
131
132/* Schedule priorities for base interrupts (CPU) */
133#define INTPRI_IPI 0
134#define INTPRI_CLOCK 1
135/* other values are system-specific */
136
137#define NLOWINT 16 /* Number of low level registrations possible */
138
139extern uint32_t idle_mask;
140
141struct trapframe;
142void set_intr(int, uint32_t, uint32_t(*)(uint32_t, struct trapframe *));
143
144uint32_t updateimask(uint32_t);
145void dosoftint(void);
146
147struct intr_controller {
148 void *ic_cookie;
149 void (*ic_init)(void);
150 void *(*ic_establish)(int, int, int (*)(void *), void *,
151 const char *);
152 void *(*ic_establish_fdt_idx)(void *, int, int, int,
153 int (*)(void *), void *, const char *);
154 void (*ic_disestablish)(void *);
155 void (*ic_intr_barrier)(void *);
156
157#ifdef MULTIPROCESSOR
158 int (*ic_ipi_establish)(int (*)(void *), cpuid_t);
159 void (*ic_ipi_set)(cpuid_t);
160 void (*ic_ipi_clear)(cpuid_t);
161#endif /* MULTIPROCESSOR */
162
163 int ic_node;
164 int ic_phandle;
165 LIST_ENTRY(intr_controller) ic_list;
166};
167
168#ifdef MULTIPROCESSOR
169#define ENABLEIPI() updateimask(~CR_INT_1) /* enable IPI interrupt level */
170#endif
171
172void *octeon_intr_establish(int, int, int (*)(void *),
173 void *, const char *);
174void octeon_intr_disestablish(void *);
175void octeon_intr_init(void);
176void octeon_intr_register(struct intr_controller *);
177
178void *octeon_intr_establish_fdt(int, int, int (*)(void *),
179 void *, const char *);
180void *octeon_intr_establish_fdt_idx(int, int, int, int (*)(void *),
181 void *, const char *);
182void octeon_intr_disestablish_fdt(void *);
183
184#endif /* _LOCORE */
185
186#endif /* _MACHINE_INTR_H_ */