1/* $OpenBSD: octeonreg.h,v 1.11 2020/07/11 15:18:08 visa Exp $ */
2
3/*
4 * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.com).
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29#ifndef _MACHINE_OCTEONREG_H_
30#define _MACHINE_OCTEONREG_H_
31
32#define OCTEON_CF_BASE 0x1D000800ULL
33#define OCTEON_CIU3_BASE 0x1010000000000ULL
34#define OCTEON_CIU_BASE 0x1070000000000ULL
35#define OCTEON_CIU_SIZE 0x7000
36#define OCTEON_MIO_BOOT_BASE 0x1180000000000ULL
37#define OCTEON_UART0_BASE 0x1180000000800ULL
38#define OCTEON_UART1_BASE 0x1180000000C00ULL
39#define OCTEON_RNG_BASE 0x1400000000000ULL
40#define OCTEON_AMDCF_BASE 0x1dc00000ULL
41
42#define MIO_BOOT_REG_CFG0 0x0
43#define MIO_BOOT_REG_CFG(x) (MIO_BOOT_REG_CFG0+((x)*8))
44#define BOOT_CFG_BASE_MASK 0xFFFF
45#define BOOT_CFG_BASE_SHIFT 16
46#define BOOT_CFG_WIDTH_MASK 0x10000000
47#define BOOT_CFG_WIDTH_SHIFT 28
48
49#define CIU_INT_WORKQ0 0
50#define CIU_INT_WORKQ1 1
51#define CIU_INT_WORKQ2 2
52#define CIU_INT_WORKQ3 3
53#define CIU_INT_WORKQ4 4
54#define CIU_INT_WORKQ5 5
55#define CIU_INT_WORKQ6 6
56#define CIU_INT_WORKQ7 7
57#define CIU_INT_WORKQ8 8
58#define CIU_INT_WORKQ9 9
59#define CIU_INT_WORKQ10 10
60#define CIU_INT_WORKQ11 11
61#define CIU_INT_WORKQ12 12
62#define CIU_INT_WORKQ13 13
63#define CIU_INT_WORKQ14 14
64#define CIU_INT_WORKQ15 15
65#define CIU_INT_GPIO0 16
66#define CIU_INT_GPIO1 17
67#define CIU_INT_GPIO2 18
68#define CIU_INT_GPIO3 19
69#define CIU_INT_GPIO4 20
70#define CIU_INT_GPIO5 21
71#define CIU_INT_GPIO6 22
72#define CIU_INT_GPIO7 23
73#define CIU_INT_GPIO8 24
74#define CIU_INT_GPIO9 25
75#define CIU_INT_GPIO10 26
76#define CIU_INT_GPIO11 27
77#define CIU_INT_GPIO12 28
78#define CIU_INT_GPIO13 29
79#define CIU_INT_GPIO14 30
80#define CIU_INT_GPIO15 31
81#define CIU_INT_MBOX0 32
82#define CIU_INT_MBOX1 33
83#define CIU_INT_MBOX(x) (CIU_INT_MBOX0+(x))
84#define CIU_INT_UART0 34
85#define CIU_INT_UART1 35
86#define CIU_INT_PCI_INTA 36
87#define CIU_INT_PCI_INTB 37
88#define CIU_INT_PCI_INTC 38
89#define CIU_INT_PCI_INTD 39
90#define CIU_INT_PCI_MSIA 40
91#define CIU_INT_PCI_MSIB 41
92#define CIU_INT_PCI_MSIC 42
93#define CIU_INT_PCI_MSID 43
94#define CIU_INT_44 44
95#define CIU_INT_TWSI 45
96#define CIU_INT_RML 46
97#define CIU_INT_TRACE 47
98#define CIU_INT_GMX_DRP0 48
99#define CIU_INT_GMX_DRP1 49
100#define CIU_INT_IPD_DRP 50
101#define CIU_INT_KEY_ZERO 51
102#define CIU_INT_TIMER0 52
103#define CIU_INT_TIMER1 53
104#define CIU_INT_TIMER2 54
105#define CIU_INT_TIMER3 55
106#define CIU_INT_USB 56
107#define CIU_INT_PCM 57
108#define CIU_INT_MPI 58
109#define CIU_INT_TWSI2 59
110#define CIU_INT_POWIQ 60
111#define CIU_INT_IPDPPTHR 61
112#define CIU_INT_MII0 62
113#define CIU_INT_BOOTDMA 63
114
115#define CIU_INT0_SUM0 0x00000000
116#define CIU_INT1_SUM0 0x00000008
117#define CIU_INT2_SUM0 0x00000010
118#define CIU_INT3_SUM0 0x00000018
119#define CIU_IP2_SUM0(x) (CIU_INT0_SUM0+(0x10 * (x)))
120#define CIU_IP3_SUM0(x) (CIU_INT1_SUM0+(0x10 * (x)))
121#define CIU_INT32_SUM0 0x00000100
122#define CIU_INT32_SUM1 0x00000108
123#define CIU_INT0_EN0 0x00000200
124#define CIU_INT1_EN0 0x00000210
125#define CIU_INT2_EN0 0x00000220
126#define CIU_INT3_EN0 0x00000230
127#define CIU_IP2_EN0(x) (CIU_INT0_EN0+(0x20 * (x)))
128#define CIU_IP3_EN0(x) (CIU_INT1_EN0+(0x20 * (x)))
129#define CIU_INT32_EN0 0x00000400
130#define CIU_INT0_EN1 0x00000208
131#define CIU_INT1_EN1 0x00000218
132#define CIU_INT2_EN1 0x00000228
133#define CIU_INT3_EN1 0x00000238
134#define CIU_INT32_EN1 0x00000408
135#define CIU_IP2_EN1(x) (CIU_INT0_EN1+(0x20 * (x)))
136#define CIU_IP3_EN1(x) (CIU_INT1_EN1+(0x20 * (x)))
137#define CIU_TIM0 0x00000480
138#define CIU_TIM1 0x00000488
139#define CIU_TIM2 0x00000490
140#define CIU_TIM3 0x00000498
141#define CIU_WDOG0 0x00000500
142#define CIU_WDOG1 0x00000508
143#define CIU_PP_POKE0 0x00000580
144#define CIU_PP_POKE1 0x00000588
145#define CIU_MBOX_SET0 0x00000600
146#define CIU_MBOX_SET1 0x00000608
147#define CIU_MBOX_SET(x) (CIU_MBOX_SET0+(0x08 * (x)))
148#define CIU_MBOX_CLR0 0x00000680
149#define CIU_MBOX_CLR1 0x00000688
150#define CIU_MBOX_CLR(x) (CIU_MBOX_CLR0+(0x08 * (x)))
151#define CIU_PP_RST 0x00000700
152#define CIU_PP_DBG 0x00000708
153#define CIU_GSTOP 0x00000710
154#define CIU_NMI 0x00000718
155#define CIU_DINT 0x00000720
156#define CIU_FUSE 0x00000728
157#define CIU_BIST 0x00000730
158#define CIU_SOFT_BIST 0x00000738
159#define CIU_SOFT_RST 0x00000740
160#define CIU_SOFT_PRST 0x00000748
161#define CIU_PCI_INTA 0x00000750
162#define CIU_INT0_SUM4 0x00000C00
163#define CIU_INT1_SUM4 0x00000C08
164#define CIU_INT0_EN4_0 0x00000C80
165#define CIU_INT1_EN4_0 0x00000C90
166#define CIU_INT0_EN4_1 0x00000C88
167#define CIU_INT1_EN4_1 0x00000C98
168#define CIU_IP4_SUM2(x) (0x00008c00 + 8 * (x))
169#define CIU_IP4_EN2(x) (0x0000a400 + 8 * (x))
170
171#define CIU3_FUSE 0x000001a0
172
173#define FPA3_CLK_COUNT 0x12800000000f0ULL
174
175/* OCTEON II */
176#define MIO_RST_BOOT 0x1180000001600ULL
177#define MIO_RST_BOOT_C_MUL_SHIFT 30
178#define MIO_RST_BOOT_C_MUL_MASK 0x7f
179#define MIO_RST_BOOT_PNR_MUL_SHIFT 24
180#define MIO_RST_BOOT_PNR_MUL_MASK 0x3f
181
182#define MIO_RST_CTL(x) (0x1180000001618ULL + 8 * (x))
183#define MIO_RST_CTL_PRTMODE 0x0000000000000030ULL
184
185/* OCTEON III */
186#define RST_BOOT 0x1180006001600ULL
187#define RST_BOOT_C_MUL_SHIFT 30
188#define RST_BOOT_C_MUL_MASK 0x7f
189#define RST_BOOT_PNR_MUL_SHIFT 24
190#define RST_BOOT_PNR_MUL_MASK 0x3f
191#define RST_CTL(x) (0x1180006001640ULL + 8 * (x))
192#define RST_CTL_RST_DONE 0x0000000000000100ULL
193#define RST_CTL_HOST_MODE 0x0000000000000040ULL
194#define RST_SOFT_RST 0x1180006001680ULL
195
196#define OCTEON_IO_REF_CLOCK 50000000 /* 50MHz */
197
198#endif /* !_MACHINE_OCTEONREG_H_ */