1/* $NetBSD: fenv.h,v 1.8 2024/10/30 15:56:11 riastradh Exp $ */
2
3/*-
4 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: head/lib/msun/powerpc/fenv.h 226218 2011-10-10 15:43:09Z das $
29 */
30
31#ifndef _POWERPC_FENV_H_
32#define _POWERPC_FENV_H_
33
34#include <sys/featuretest.h>
35#include <sys/stdint.h>
36
37/* Exception flags */
38#define FE_INEXACT 0x02000000
39#define FE_DIVBYZERO 0x04000000
40#define FE_UNDERFLOW 0x08000000
41#define FE_OVERFLOW 0x10000000
42#define FE_INVALID 0x20000000 /* all types of invalid FP ops */
43
44/*
45 * The PowerPC architecture has extra invalid flags that indicate the
46 * specific type of invalid operation occurred. These flags may be
47 * tested, set, and cleared---but not masked---separately. All of
48 * these bits are cleared when FE_INVALID is cleared, but only
49 * FE_VXSOFT is set when FE_INVALID is explicitly set in software.
50 */
51#define FE_VXCVI 0x00000100 /* invalid integer convert */
52#define FE_VXSQRT 0x00000200 /* square root of a negative */
53#define FE_VXSOFT 0x00000400 /* software-requested exception */
54#define FE_VXVC 0x00080000 /* ordered comparison involving NaN */
55#define FE_VXIMZ 0x00100000 /* inf * 0 */
56#define FE_VXZDZ 0x00200000 /* 0 / 0 */
57#define FE_VXIDI 0x00400000 /* inf / inf */
58#define FE_VXISI 0x00800000 /* inf - inf */
59#define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */
60#define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \
61 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \
62 FE_VXSNAN | FE_INVALID)
63#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
64 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
65
66/* Rounding modes */
67#define FE_TONEAREST 0x0000
68#define FE_TOWARDZERO 0x0001
69#define FE_UPWARD 0x0002
70#define FE_DOWNWARD 0x0003
71#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
72 FE_UPWARD | FE_TOWARDZERO)
73
74#ifndef _SOFT_FLOAT
75
76#ifndef __fenv_static
77#define __fenv_static static
78#endif
79
80typedef uint32_t fenv_t;
81typedef uint32_t fexcept_t;
82
83#ifndef _KERNEL
84__BEGIN_DECLS
85
86/* Default floating-point environment */
87extern const fenv_t __fe_dfl_env;
88#define FE_DFL_ENV (&__fe_dfl_env)
89
90/* We need to be able to map status flag positions to mask flag positions */
91#define _FPUSW_SHIFT 22
92#define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
93 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT)
94
95#ifndef _SOFT_FLOAT
96#define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env)))
97#define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env))
98
99static __inline uint32_t
100__mfmsr(void)
101{
102 uint32_t __msr;
103
104 __asm volatile ("mfmsr %0" : "=r"(__msr));
105 return __msr;
106}
107
108static __inline void
109__mtmsr(uint32_t __msr)
110{
111
112 __asm volatile ("mtmsr %0" : : "r"(__msr));
113}
114
115#define __MSR_FE_MASK (0x00000800 | 0x00000100)
116#define __MSR_FE_DIS (0)
117#define __MSR_FE_PREC (0x00000800 | 0x00000100)
118
119static __inline void
120__updatemsr(uint32_t __reg)
121{
122 uint32_t __msr;
123
124 __msr = __mfmsr() & ~__MSR_FE_MASK;
125 if (__reg != 0) {
126 __msr |= __MSR_FE_PREC;
127 } else {
128 __msr |= __MSR_FE_DIS;
129 }
130 __mtmsr(__msr);
131}
132
133#else
134#define __mffs(__env)
135#define __mtfsf(__env)
136#define __updatemsr(__reg)
137#endif
138
139union __fpscr {
140 double __d;
141 struct {
142 uint32_t __junk;
143 fenv_t __reg;
144 } __bits;
145};
146
147#if __GNUC_PREREQ__(8, 0)
148#pragma GCC diagnostic push
149#pragma GCC diagnostic ignored "-Wshadow"
150#endif
151
152__fenv_static __inline int
153feclearexcept(int __excepts)
154{
155 union __fpscr __r;
156
157 if (__excepts & FE_INVALID)
158 __excepts |= FE_ALL_INVALID;
159 __mffs(&__r.__d);
160 __r.__bits.__reg &= ~__excepts;
161 __mtfsf(__r.__d);
162 return (0);
163}
164
165__fenv_static __inline int
166fegetexceptflag(fexcept_t *__flagp, int __excepts)
167{
168 union __fpscr __r;
169
170 __mffs(&__r.__d);
171 *__flagp = __r.__bits.__reg & __excepts;
172 return (0);
173}
174
175__fenv_static __inline int
176fesetexceptflag(const fexcept_t *__flagp, int __excepts)
177{
178 union __fpscr __r;
179
180 if (__excepts & FE_INVALID)
181 __excepts |= FE_ALL_INVALID;
182 __mffs(&__r.__d);
183 __r.__bits.__reg &= ~__excepts;
184 __r.__bits.__reg |= *__flagp & __excepts;
185 __mtfsf(__r.__d);
186 return (0);
187}
188
189__fenv_static __inline int
190feraiseexcept(int __excepts)
191{
192 union __fpscr __r;
193
194 if (__excepts & FE_INVALID)
195 __excepts |= FE_VXSOFT;
196 __mffs(&__r.__d);
197 __r.__bits.__reg |= __excepts;
198 __mtfsf(__r.__d);
199 return (0);
200}
201
202__fenv_static __inline int
203fetestexcept(int __excepts)
204{
205 union __fpscr __r;
206
207 __mffs(&__r.__d);
208 return (__r.__bits.__reg & __excepts);
209}
210
211__fenv_static __inline int
212fegetround(void)
213{
214 union __fpscr __r;
215
216 __mffs(&__r.__d);
217 return (__r.__bits.__reg & _ROUND_MASK);
218}
219
220__fenv_static __inline int
221fesetround(int __round)
222{
223 union __fpscr __r;
224
225 if (__round & ~_ROUND_MASK)
226 return (-1);
227 __mffs(&__r.__d);
228 __r.__bits.__reg &= ~_ROUND_MASK;
229 __r.__bits.__reg |= __round;
230 __mtfsf(__r.__d);
231 return (0);
232}
233
234__fenv_static __inline int
235fegetenv(fenv_t *__envp)
236{
237 union __fpscr __r;
238
239 __mffs(&__r.__d);
240 *__envp = __r.__bits.__reg;
241 return (0);
242}
243
244__fenv_static __inline int
245feholdexcept(fenv_t *__envp)
246{
247 union __fpscr __r;
248 uint32_t msr;
249
250 __mffs(&__r.__d);
251 *__envp = __r.__bits.__reg;
252 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
253 __mtfsf(__r.__d);
254 __updatemsr(__r.__bits.__reg);
255 return (0);
256}
257
258__fenv_static __inline int
259fesetenv(const fenv_t *__envp)
260{
261 union __fpscr __r;
262
263 __r.__bits.__reg = *__envp;
264 __mtfsf(__r.__d);
265 __updatemsr(__r.__bits.__reg);
266 return (0);
267}
268
269__fenv_static __inline int
270feupdateenv(const fenv_t *__envp)
271{
272 union __fpscr __r;
273
274 __mffs(&__r.__d);
275 __r.__bits.__reg &= FE_ALL_EXCEPT;
276 __r.__bits.__reg |= *__envp;
277 __mtfsf(__r.__d);
278 __updatemsr(__r.__bits.__reg);
279 return (0);
280}
281
282#if __GNUC_PREREQ__(8, 0)
283#pragma GCC diagnostic pop
284#endif
285
286#if defined(_NETBSD_SOURCE) || defined(_GNU_SOURCE)
287
288__fenv_static __inline int
289feenableexcept(int __mask)
290{
291 union __fpscr __r;
292 fenv_t __oldmask;
293
294 __mffs(&__r.__d);
295 __oldmask = __r.__bits.__reg;
296 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT;
297 __mtfsf(__r.__d);
298 __updatemsr(__r.__bits.__reg);
299 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
300}
301
302__fenv_static __inline int
303fedisableexcept(int __mask)
304{
305 union __fpscr __r;
306 fenv_t __oldmask;
307
308 __mffs(&__r.__d);
309 __oldmask = __r.__bits.__reg;
310 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT);
311 __mtfsf(__r.__d);
312 __updatemsr(__r.__bits.__reg);
313 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
314}
315
316__fenv_static __inline int
317fegetexcept(void)
318{
319 union __fpscr __r;
320
321 __mffs(&__r.__d);
322 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT);
323}
324
325#endif /* _NETBSD_SOURCE || _GNU_SOURCE */
326
327__END_DECLS
328
329#endif
330#endif /* _SOFT_FLOAT */
331
332#endif /* !_POWERPC_FENV_H_ */