1/* $OpenBSD: z8530var.h,v 1.11 2024/05/22 05:51:49 jsg Exp $ */
2/* $NetBSD: z8530var.h,v 1.5 2002/03/17 19:40:45 atatat Exp $ */
3
4/*
5 * Copyright (c) 1994 Gordon W. Ross
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
8 *
9 * This software was developed by the Computer Systems Engineering group
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
11 * contributed to Berkeley.
12 *
13 * All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Lawrence Berkeley Laboratory.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
20 * are met:
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. Neither the name of the University nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * SUCH DAMAGE.
41 *
42 * @(#)zsvar.h 8.1 (Berkeley) 6/11/93
43 */
44
45#include <dev/ic/z8530sc.h>
46#include <macppc/dev/dbdma.h>
47
48/*
49 * Clock source info structure, added here so xzs_chanstate works
50 */
51struct zsclksrc {
52 long clk; /* clock rate, in MHz, present on signal line */
53 int flags; /* Specifies how this source can be used
54 (RTxC divided, RTxC BRG, PCLK BRG, TRxC divided)
55 and also if the source is "external" and if it
56 is changeable (by an ioctl ex.). The
57 source usage flags are used by the tty
58 child. The other bits tell zsloadchannelregs
59 if it should call an md signal source
60 changing routine. ZSC_VARIABLE says if
61 an ioctl should be able to change the
62 clock rate.*/
63};
64#define ZSC_PCLK 0x01
65#define ZSC_RTXBRG 0x02
66#define ZSC_RTXDIV 0x04
67#define ZSC_TRXDIV 0x08
68#define ZSC_VARIABLE 0x40
69#define ZSC_EXTERN 0x80
70
71#define ZSC_BRG 0x03
72#define ZSC_DIV 0x0c
73
74
75/*
76 * These are the machine-dependent (extended) variants of
77 * struct zs_chanstate and struct zsc_softc
78 */
79struct xzs_chanstate {
80 /* machine-independent part (First!)*/
81 struct zs_chanstate xzs_cs;
82 /* machine-dependent extensions */
83 int cs_hwflags;
84 int cs_chip; /* type of chip */
85 /* Clock source info... */
86 int cs_clock_count; /* how many signal sources available */
87 struct zsclksrc cs_clocks[4]; /* info on available signal sources */
88 long cs_cclk_flag; /* flag for current clock source */
89 long cs_pclk_flag; /* flag for pending clock source */
90 int cs_csource; /* current source # */
91 int cs_psource; /* pending source # */
92};
93
94struct zsc_softc {
95 struct device zsc_dev; /* base device */
96 struct zs_chanstate *zsc_cs[2]; /* channel A and B soft state */
97 /* Machine-dependent part follows... */
98 void *zsc_softintr;
99 struct xzs_chanstate xzsc_xcs_store[2];
100 dbdma_regmap_t *zsc_txdmareg[2];
101 dbdma_command_t *zsc_txdmacmd[2];
102 /* XXX tx only, for now */
103};
104
105/*
106 * Functions to read and write individual registers in a channel.
107 * The ZS chip requires a 1.6 uSec. recovery time between accesses,
108 * and the Sun3 hardware does NOT take care of this for you.
109 * MacII hardware DOES take care of the delay for us. :-)
110 * XXX - Then these should be inline functions! -gwr
111 * Some clock-chirped macs lose serial ports. It could be that the
112 * hardware delay is tied to the CPU speed, and that the minimum delay
113 * no longer's respected. For them, ZS_DELAY might help.
114 * XXX - no one seems to want to try and check this -wrs
115 */
116
117u_char zs_read_reg(struct zs_chanstate *cs, u_char reg);
118u_char zs_read_csr(struct zs_chanstate *cs);
119u_char zs_read_data(struct zs_chanstate *cs);
120
121void zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val);
122void zs_write_csr(struct zs_chanstate *cs, u_char val);
123void zs_write_data(struct zs_chanstate *cs, u_char val);
124
125/* XXX - Could define splzs() here instead of in psl.h */
126#define splzs spltty
127
128/* Hook for MD ioctl support */
129int zsmdioctl(struct zs_chanstate *cs, u_long cmd, caddr_t data);
130/* XXX - This is a bit gross... */
131/*
132#define ZS_MD_IOCTL(cs, cmd, data) zsmdioctl(cs, cmd, data)
133*/
134
135/* Callback for "external" clock sources */
136void zsmd_setclock(struct zs_chanstate *cs);
137#define ZS_MD_SETCLK(cs) zsmd_setclock(cs)
138
139#define PCLK (9600 * 384) /* PCLK pin input clock rate */
140
141/* The layout of this is hardware-dependent (padding, order). */
142struct zschan {
143 volatile u_char zc_csr; /* ctrl,status, and indirect access */
144 u_char zc_xxx0[15];
145 volatile u_char zc_data; /* data */
146 u_char zc_xxx1[15];
147};
148
149#ifndef ZSCCF_CHANNEL
150#define ZSCCF_CHANNEL 0
151#define ZSCCF_CHANNEL_DEFAULT -1
152#endif