1/* $OpenBSD: trap.h,v 1.9 2022/10/22 00:58:56 gkoehler Exp $ */
2/* $NetBSD: trap.h,v 1.1 1996/09/30 16:34:35 ws Exp $ */
3
4/*
5 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6 * Copyright (C) 1995, 1996 TooLs GmbH.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by TooLs GmbH.
20 * 4. The name of TooLs GmbH may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34#ifndef _POWERPC_TRAP_H_
35#define _POWERPC_TRAP_H_
36
37#define EXC_RSVD 0x0000 /* Reserved */
38#define EXC_RST 0x0100 /* Reset */
39#define EXC_MCHK 0x0200 /* Machine Check */
40#define EXC_DSI 0x0300 /* Data Storage Interrupt */
41#define EXC_ISI 0x0400 /* Instruction Storage Interrupt */
42#define EXC_EXI 0x0500 /* External Interrupt */
43#define EXC_ALI 0x0600 /* Alignment Interrupt */
44#define EXC_PGM 0x0700 /* Program Interrupt */
45#define EXC_FPU 0x0800 /* Floating-point Unavailable */
46#define EXC_DECR 0x0900 /* Decrementer Interrupt */
47#define EXC_SC 0x0c00 /* System Call */
48#define EXC_TRC 0x0d00 /* Trace */
49#define EXC_FPA 0x0e00 /* Floating-point Assist */
50#define EXC_PERF 0x0f00 /* Performance Monitoring */
51#define EXC_VEC 0x0f20 /* AltiVec Unavailable */
52#define EXC_BPT 0x1300 /* Instruction Breakpoint */
53#define EXC_SMI 0x1400 /* System Management Interrupt */
54#define EXC_VECAST_G4 0x1600 /* AltiVec Assist */
55#define EXC_VECAST_G5 0x1700 /* AltiVec Assist */
56
57/* And these are only on the 603: */
58#define EXC_IMISS 0x1000 /* Instruction translation miss */
59#define EXC_DLMISS 0x1100 /* Data load translation miss */
60#define EXC_DSMISS 0x1200 /* Data store translation miss */
61
62#define EXC_END 0x3000 /* End of exception vectors */
63
64#define EXC_AST 0x3000 /* Fake AST vector */
65
66/* Trap was in user mode */
67#define EXC_USER 0x10000
68
69/*
70 * EXC_ALI sets bits in the DSISR and DAR to provide enough
71 * information to recover from the unaligned access without needing to
72 * parse the offending instruction. This includes certain bits of the
73 * opcode, and information about what registers are used. The opcode
74 * indicator values below come from Appendix F of Book III of "The
75 * PowerPC Architecture".
76 */
77
78#define EXC_ALI_OPCODE_INDICATOR(dsisr) ((dsisr >> 10) & 0x7f)
79#define EXC_ALI_LFD 0x09
80#define EXC_ALI_STFD 0x0b
81#define EXC_ALI_DCBZ 0x5f
82
83/* Macros to extract register information */
84#define EXC_ALI_RST(dsisr) ((dsisr >> 5) & 0x1f) /* source or target */
85#define EXC_ALI_RA(dsisr) (dsisr & 0x1f)
86
87#endif /* _POWERPC_TRAP_H_ */