1/*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (C) 1995-1997 Wolfgang Solfrank.
5 * Copyright (C) 1995-1997 TooLs GmbH.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by TooLs GmbH.
19 * 4. The name of TooLs GmbH may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $NetBSD: cpu.h,v 1.11 2000/05/26 21:19:53 thorpej Exp $
34 */
35
36#ifndef _MACHINE_CPU_H_
37#define _MACHINE_CPU_H_
38
39#include <machine/frame.h>
40#include <machine/pcb.h>
41#include <machine/psl.h>
42
43/*
44 * CPU Feature Attributes
45 *
46 * These are defined in the PowerPC ELF ABI for the AT_HWCAP vector,
47 * and are exported to userland via the machdep.cpu_features
48 * sysctl.
49 */
50
51extern u_long cpu_features;
52extern u_long cpu_features2;
53
54#define PPC_FEATURE_32 0x80000000 /* Always true */
55#define PPC_FEATURE_64 0x40000000 /* Defined on a 64-bit CPU */
56#define PPC_FEATURE_601_INSTR 0x20000000 /* Defined on a 64-bit CPU */
57#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
58#define PPC_FEATURE_HAS_FPU 0x08000000
59#define PPC_FEATURE_HAS_MMU 0x04000000
60#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
61#define PPC_FEATURE_HAS_SPE 0x00800000
62#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
63#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
64#define PPC_FEATURE_NO_TB 0x00100000
65#define PPC_FEATURE_POWER4 0x00080000
66#define PPC_FEATURE_POWER5 0x00040000
67#define PPC_FEATURE_POWER5_PLUS 0x00020000
68#define PPC_FEATURE_CELL 0x00010000
69#define PPC_FEATURE_BOOKE 0x00008000
70#define PPC_FEATURE_SMT 0x00004000
71#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
72#define PPC_FEATURE_ARCH_2_05 0x00001000
73#define PPC_FEATURE_HAS_DFP 0x00000400
74#define PPC_FEATURE_POWER6_EXT 0x00000200
75#define PPC_FEATURE_ARCH_2_06 0x00000100
76#define PPC_FEATURE_HAS_VSX 0x00000080
77#define PPC_FEATURE_TRUE_LE 0x00000002
78#define PPC_FEATURE_PPC_LE 0x00000001
79
80#define PPC_FEATURE2_ARCH_2_07 0x80000000
81#define PPC_FEATURE2_HTM 0x40000000
82#define PPC_FEATURE2_DSCR 0x20000000
83#define PPC_FEATURE2_EBB 0x10000000
84#define PPC_FEATURE2_ISEL 0x08000000
85#define PPC_FEATURE2_TAR 0x04000000
86#define PPC_FEATURE2_HAS_VEC_CRYPTO 0x02000000
87#define PPC_FEATURE2_HTM_NOSC 0x01000000
88#define PPC_FEATURE2_ARCH_3_00 0x00800000
89#define PPC_FEATURE2_HAS_IEEE128 0x00400000
90#define PPC_FEATURE2_DARN 0x00200000
91#define PPC_FEATURE2_SCV 0x00100000
92#define PPC_FEATURE2_HTM_NOSUSPEND 0x00080000
93#define PPC_FEATURE2_ARCH_3_1 0x00040000
94#define PPC_FEATURE2_MMA 0x00020000
95
96#define PPC_FEATURE_BITMASK \
97 "\20" \
98 "\040PPC32\037PPC64\036PPC601\035ALTIVEC\034FPU\033MMU\031UNIFIEDCACHE" \
99 "\030SPE\027SPESFP\026DPESFP\025NOTB\024POWER4\023POWER5\022P5PLUS\021CELL"\
100 "\020BOOKE\017SMT\016ISNOOP\015ARCH205\013DFP\011ARCH206\010VSX"\
101 "\002TRUELE\001PPCLE"
102#define PPC_FEATURE2_BITMASK \
103 "\20" \
104 "\040ARCH207\037HTM\036DSCR\034ISEL\033TAR\032VCRYPTO\031HTMNOSC" \
105 "\030ARCH300\027IEEE128\026DARN\025SCV\024HTMNOSUSP"
106
107#define TRAPF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0)
108#define TRAPF_PC(frame) ((frame)->srr0)
109
110/*
111 * CTL_MACHDEP definitions.
112 */
113#define CPU_CACHELINE 1
114
115static __inline u_int64_t
116get_cyclecount(void)
117{
118 u_int32_t _upper, _lower;
119 u_int64_t _time;
120
121 __asm __volatile(
122 "mftb %0\n"
123 "mftbu %1"
124 : "=r" (_lower), "=r" (_upper));
125
126 _time = (u_int64_t)_upper;
127 _time = (_time << 32) + _lower;
128 return (_time);
129}
130
131#define cpu_getstack(td) ((td)->td_frame->fixreg[1])
132#define cpu_spinwait() __asm __volatile("or 27,27,27") /* yield */
133#define cpu_lock_delay() DELAY(1)
134
135extern char btext[];
136extern char etext[];
137
138struct thread;
139
140#ifdef __powerpc64__
141extern void enter_idle_powerx(void);
142extern uint64_t can_wakeup;
143extern register_t lpcr;
144#endif
145
146void cpu_halt(void);
147void cpu_reset(void);
148void flush_disable_caches(void);
149void fork_trampoline(void);
150int cpu_machine_check(struct thread *, struct trapframe *, int *);
151
152
153#ifndef __powerpc64__
154void mpc745x_sleep(void);
155#endif
156
157#endif /* _MACHINE_CPU_H_ */