1/*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * from NetBSD: openpicreg.h,v 1.3 2001/08/30 03:08:52 briggs Exp
29 */
30
31/*
32 * Size of OpenPIC register space
33 */
34#define OPENPIC_SIZE 0x40000
35
36/*
37 * Per Processor Registers [private access] (0x00000 - 0x00fff)
38 */
39
40/* IPI dispatch command reg */
41#define OPENPIC_IPI_DISPATCH(ipi) (0x40 + (ipi) * 0x10)
42
43/* current task priority reg */
44#define OPENPIC_TPR 0x80
45#define OPENPIC_TPR_MASK 0x0000000f
46
47#define OPENPIC_WHOAMI 0x90
48
49/* interrupt acknowledge reg */
50#define OPENPIC_IACK 0xa0
51
52/* end of interrupt reg */
53#define OPENPIC_EOI 0xb0
54
55/*
56 * Global registers (0x01000-0x0ffff)
57 */
58
59/* feature reporting reg 0 */
60#define OPENPIC_FEATURE 0x1000
61#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff
62#define OPENPIC_FEATURE_LAST_CPU_MASK 0x00001f00
63#define OPENPIC_FEATURE_LAST_CPU_SHIFT 8
64#define OPENPIC_FEATURE_LAST_IRQ_MASK 0x07ff0000
65#define OPENPIC_FEATURE_LAST_IRQ_SHIFT 16
66
67/* global config reg 0 */
68#define OPENPIC_CONFIG 0x1020
69#define OPENPIC_CONFIG_RESET 0x80000000
70#define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000
71
72/* interrupt configuration mode (direct or serial) */
73#define OPENPIC_ICR 0x1030
74#define OPENPIC_ICR_SERIAL_MODE (1 << 27)
75#define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28)
76#define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28
77
78/* vendor ID */
79#define OPENPIC_VENDOR_ID 0x1080
80
81/* processor initialization reg */
82#define OPENPIC_PROC_INIT 0x1090
83
84/* IPI vector/priority reg */
85#define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10)
86
87/* spurious intr. vector */
88#define OPENPIC_SPURIOUS_VECTOR 0x10e0
89
90/* Timer registers */
91#define OPENPIC_TIMERS 4
92#define OPENPIC_TFREQ 0x10f0
93#define OPENPIC_TCNT(t) (0x1100 + (t) * 0x40)
94#define OPENPIC_TBASE(t) (0x1110 + (t) * 0x40)
95#define OPENPIC_TVEC(t) (0x1120 + (t) * 0x40)
96#define OPENPIC_TDST(t) (0x1130 + (t) * 0x40)
97
98/*
99 * Interrupt Source Configuration Registers (0x10000 - 0x1ffff)
100 */
101
102/* interrupt vector/priority reg */
103#define OPENPIC_SRC_VECTOR_COUNT 64
104#ifndef OPENPIC_SRC_VECTOR
105#define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20)
106#endif
107#define OPENPIC_SENSE_LEVEL 0x00400000
108#define OPENPIC_SENSE_EDGE 0x00000000
109#define OPENPIC_POLARITY_POSITIVE 0x00800000
110#define OPENPIC_POLARITY_NEGATIVE 0x00000000
111#define OPENPIC_IMASK 0x80000000
112#define OPENPIC_ACTIVITY 0x40000000
113#define OPENPIC_PRIORITY_MASK 0x000f0000
114#define OPENPIC_PRIORITY_SHIFT 16
115#define OPENPIC_VECTOR_MASK 0x000000ff
116
117/* interrupt destination cpu */
118#ifndef OPENPIC_IDEST
119#define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20)
120#endif
121
122/*
123 * Per Processor Registers [global access] (0x20000 - 0x3ffff)
124 */
125
126#define OPENPIC_PCPU_BASE(cpu) (0x20000 + (cpu) * 0x1000)
127
128#define OPENPIC_PCPU_IPI_DISPATCH(cpu, ipi) \
129 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_IPI_DISPATCH(ipi))
130
131#define OPENPIC_PCPU_TPR(cpu) \
132 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_TPR)
133
134#define OPENPIC_PCPU_WHOAMI(cpu) \
135 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_WHOAMI)
136
137#define OPENPIC_PCPU_IACK(cpu) \
138 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_IACK)
139
140#define OPENPIC_PCPU_EOI(cpu) \
141 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_EOI)