1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2002 Benno Rice.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifndef _POWERPC_OPENPICVAR_H_
29#define _POWERPC_OPENPICVAR_H_
30
31#define OPENPIC_DEVSTR "OpenPIC Interrupt Controller"
32
33#define OPENPIC_IRQMAX 256 /* h/w allows more */
34
35#define OPENPIC_QUIRK_SINGLE_BIND 1 /* Bind interrupts to only 1 CPU */
36#define OPENPIC_QUIRK_HIDDEN_IRQS 2 /* May have IRQs beyond FRR[NIRQ] */
37
38/* Names match the macros in openpicreg.h. */
39struct openpic_timer {
40 uint32_t tcnt;
41 uint32_t tbase;
42 uint32_t tvec;
43 uint32_t tdst;
44};
45
46struct openpic_softc {
47 device_t sc_dev;
48 struct resource *sc_memr;
49 struct resource *sc_intr;
50 bus_space_tag_t sc_bt;
51 bus_space_handle_t sc_bh;
52 char *sc_version;
53 int sc_rid;
54 int sc_irq;
55 void *sc_icookie;
56 u_int sc_ncpu;
57 u_int sc_nirq;
58 int sc_psim;
59 u_int sc_quirks;
60
61 /* Saved states. */
62 uint32_t sc_saved_config;
63 uint32_t sc_saved_ipis[4];
64 uint32_t sc_saved_prios[4];
65 struct openpic_timer sc_saved_timers[OPENPIC_TIMERS];
66 uint32_t sc_saved_vectors[OPENPIC_SRC_VECTOR_COUNT];
67
68};
69
70/*
71 * Bus-independent attach i/f
72 */
73int openpic_common_attach(device_t, uint32_t);
74
75/*
76 * PIC interface.
77 */
78void openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **);
79void openpic_config(device_t, u_int, enum intr_trigger, enum intr_polarity);
80void openpic_dispatch(device_t, struct trapframe *);
81void openpic_enable(device_t, u_int, u_int, void **);
82void openpic_eoi(device_t, u_int, void *);
83void openpic_ipi(device_t, u_int);
84void openpic_mask(device_t, u_int, void *);
85void openpic_unmask(device_t, u_int, void *);
86
87int openpic_suspend(device_t dev);
88int openpic_resume(device_t dev);
89
90#endif /* _POWERPC_OPENPICVAR_H_ */