1/*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (C) 2006-2012 Semihalf.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
24 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
25 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef _MACHINE_TLB_H_
31#define _MACHINE_TLB_H_
32
33#if defined(BOOKE_E500)
34
35/* PowerPC E500 MAS registers */
36#define MAS0_TLBSEL(x) ((x << 28) & 0x10000000)
37#define MAS0_ESEL(x) ((x << 16) & 0x003F0000)
38
39#define MAS0_TLBSEL1 0x10000000
40#define MAS0_TLBSEL0 0x00000000
41#define MAS0_ESEL_TLB1MASK 0x000F0000
42#define MAS0_ESEL_TLB0MASK 0x00030000
43#define MAS0_ESEL_SHIFT 16
44#define MAS0_NV_MASK 0x00000003
45#define MAS0_NV_SHIFT 0
46
47#define MAS1_VALID 0x80000000
48#define MAS1_IPROT 0x40000000
49#define MAS1_TID_MASK 0x00FF0000
50#define MAS1_TID_SHIFT 16
51#define MAS1_TS_MASK 0x00001000
52#define MAS1_TS_SHIFT 12
53#define MAS1_TSIZE_MASK 0x00000F00
54#define MAS1_TSIZE_SHIFT 8
55
56#define TLB_SIZE_4K 1
57#define TLB_SIZE_16K 2
58#define TLB_SIZE_64K 3
59#define TLB_SIZE_256K 4
60#define TLB_SIZE_1M 5
61#define TLB_SIZE_4M 6
62#define TLB_SIZE_16M 7
63#define TLB_SIZE_64M 8
64#define TLB_SIZE_256M 9
65#define TLB_SIZE_1G 10
66#define TLB_SIZE_4G 11
67
68#ifdef __powerpc64__
69#define MAS2_EPN_MASK 0xFFFFFFFFFFFFF000UL
70#else
71#define MAS2_EPN_MASK 0xFFFFF000
72#endif
73#define MAS2_EPN_SHIFT 12
74#define MAS2_X0 0x00000040
75#define MAS2_X1 0x00000020
76#define MAS2_W 0x00000010
77#define MAS2_I 0x00000008
78#define MAS2_M 0x00000004
79#define MAS2_G 0x00000002
80#define MAS2_E 0x00000001
81#define MAS2_WIMGE_MASK 0x0000007F
82
83#define MAS3_RPN 0xFFFFF000
84#define MAS3_RPN_SHIFT 12
85#define MAS3_U0 0x00000200
86#define MAS3_U1 0x00000100
87#define MAS3_U2 0x00000080
88#define MAS3_U3 0x00000040
89#define MAS3_UX 0x00000020
90#define MAS3_SX 0x00000010
91#define MAS3_UW 0x00000008
92#define MAS3_SW 0x00000004
93#define MAS3_UR 0x00000002
94#define MAS3_SR 0x00000001
95
96#define MAS4_TLBSELD1 0x10000000
97#define MAS4_TLBSELD0 0x00000000
98#define MAS4_TIDSELD_MASK 0x00030000
99#define MAS4_TIDSELD_SHIFT 16
100#define MAS4_TSIZED_MASK 0x00000F00
101#define MAS4_TSIZED_SHIFT 8
102#define MAS4_X0D 0x00000040
103#define MAS4_X1D 0x00000020
104#define MAS4_WD 0x00000010
105#define MAS4_ID 0x00000008
106#define MAS4_MD 0x00000004
107#define MAS4_GD 0x00000002
108#define MAS4_ED 0x00000001
109
110#define MAS6_SPID0_MASK 0x00FF0000
111#define MAS6_SPID0_SHIFT 16
112#define MAS6_SAS 0x00000001
113
114#define MAS7_RPN 0x0000000F
115
116#define MAS1_GETTID(mas1) (((mas1) & MAS1_TID_MASK) >> MAS1_TID_SHIFT)
117
118#define MAS2_TLB0_ENTRY_IDX_MASK 0x0007f000
119#define MAS2_TLB0_ENTRY_IDX_SHIFT 12
120
121/*
122 * Maximum number of TLB1 entries used for a permanent mapping of kernel
123 * region (kernel image plus statically allocated data).
124 */
125#define KERNEL_REGION_MAX_TLB_ENTRIES 4
126
127/*
128 * Use MAS2_X0 to mark entries which will be copied
129 * to AP CPUs during SMP bootstrap. As result entries
130 * marked with _TLB_ENTRY_SHARED will be shared by all CPUs.
131 */
132#define _TLB_ENTRY_SHARED (MAS2_X0) /* XXX under SMP? */
133#define _TLB_ENTRY_IO (MAS2_I | MAS2_G)
134#define _TLB_ENTRY_MEM (MAS2_M)
135
136#define TLB1_MAX_ENTRIES 64
137
138#if !defined(LOCORE)
139typedef struct tlb_entry {
140 vm_paddr_t phys;
141 vm_offset_t virt;
142 vm_size_t size;
143 uint32_t mas1;
144#ifdef __powerpc64__
145 uint64_t mas2;
146#else
147 uint32_t mas2;
148#endif
149 uint32_t mas3;
150 uint32_t mas7;
151} tlb_entry_t;
152
153void tlb1_inval_entry(unsigned int);
154void tlb1_init(void);
155#endif /* !LOCORE */
156
157#endif /* BOOKE_E500 */
158
159#define TID_KERNEL 0 /* TLB TID to use for kernel (shared) translations */
160#define TID_KRESERVED 1 /* Number of TIDs reserved for kernel */
161#define TID_URESERVED 0 /* Number of TIDs reserved for user */
162#define TID_MIN (TID_KRESERVED + TID_URESERVED)
163#define TID_MAX 255
164#define TID_NONE -1
165
166#define TLB_UNLOCKED 0
167
168#if !defined(LOCORE)
169
170typedef int tlbtid_t;
171
172struct pmap;
173
174void tlb_lock(uintptr_t *);
175void tlb_unlock(uintptr_t *);
176void tlb1_ap_prep(void);
177int tlb1_set_entry(vm_offset_t, vm_paddr_t, vm_size_t, uint32_t);
178
179#endif /* !LOCORE */
180
181#endif /* _MACHINE_TLB_H_ */