1/* $OpenBSD: bus.h,v 1.5 2020/11/15 23:13:00 kettenis Exp $ */
2/*
3 * Copyright (c) 2003-2004 Opsycon AB Sweden. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26#ifndef _MACHINE_BUS_H_
27#define _MACHINE_BUS_H_
28
29#define CAT(a,b) a##b
30#define CAT3(a,b,c) a##b##c
31
32/*
33 * Bus access types.
34 */
35struct bus_space;
36typedef u_long bus_addr_t;
37typedef u_long bus_size_t;
38typedef u_long bus_space_handle_t;
39typedef struct bus_space *bus_space_tag_t;
40typedef struct bus_space bus_space_t;
41
42struct bus_space {
43 bus_addr_t bus_base;
44 void *bus_private;
45 uint8_t (*_space_read_1)(bus_space_tag_t , bus_space_handle_t,
46 bus_size_t);
47 void (*_space_write_1)(bus_space_tag_t , bus_space_handle_t,
48 bus_size_t, uint8_t);
49 uint16_t (*_space_read_2)(bus_space_tag_t , bus_space_handle_t,
50 bus_size_t);
51 void (*_space_write_2)(bus_space_tag_t , bus_space_handle_t,
52 bus_size_t, uint16_t);
53 uint32_t (*_space_read_4)(bus_space_tag_t , bus_space_handle_t,
54 bus_size_t);
55 void (*_space_write_4)(bus_space_tag_t , bus_space_handle_t,
56 bus_size_t, uint32_t);
57 uint64_t (*_space_read_8)(bus_space_tag_t , bus_space_handle_t,
58 bus_size_t);
59 void (*_space_write_8)(bus_space_tag_t , bus_space_handle_t,
60 bus_size_t, uint64_t);
61 void (*_space_read_raw_2)(bus_space_tag_t, bus_space_handle_t,
62 bus_addr_t, uint8_t *, bus_size_t);
63 void (*_space_write_raw_2)(bus_space_tag_t, bus_space_handle_t,
64 bus_addr_t, const uint8_t *, bus_size_t);
65 void (*_space_read_raw_4)(bus_space_tag_t, bus_space_handle_t,
66 bus_addr_t, uint8_t *, bus_size_t);
67 void (*_space_write_raw_4)(bus_space_tag_t, bus_space_handle_t,
68 bus_addr_t, const uint8_t *, bus_size_t);
69 void (*_space_read_raw_8)(bus_space_tag_t, bus_space_handle_t,
70 bus_addr_t, uint8_t *, bus_size_t);
71 void (*_space_write_raw_8)(bus_space_tag_t, bus_space_handle_t,
72 bus_addr_t, const uint8_t *, bus_size_t);
73 int (*_space_map)(bus_space_tag_t , bus_addr_t,
74 bus_size_t, int, bus_space_handle_t *);
75 void (*_space_unmap)(bus_space_tag_t, bus_space_handle_t,
76 bus_size_t);
77 int (*_space_subregion)(bus_space_tag_t, bus_space_handle_t,
78 bus_size_t, bus_size_t, bus_space_handle_t *);
79 void * (*_space_vaddr)(bus_space_tag_t, bus_space_handle_t);
80 paddr_t (*_space_mmap)(bus_space_tag_t, bus_addr_t, off_t,
81 int, int);
82};
83
84#define bus_space_read_1(t, h, o) (*(t)->_space_read_1)((t), (h), (o))
85#define bus_space_read_2(t, h, o) (*(t)->_space_read_2)((t), (h), (o))
86#define bus_space_read_4(t, h, o) (*(t)->_space_read_4)((t), (h), (o))
87#define bus_space_read_8(t, h, o) (*(t)->_space_read_8)((t), (h), (o))
88
89#define bus_space_write_1(t, h, o, v) (*(t)->_space_write_1)((t), (h), (o), (v))
90#define bus_space_write_2(t, h, o, v) (*(t)->_space_write_2)((t), (h), (o), (v))
91#define bus_space_write_4(t, h, o, v) (*(t)->_space_write_4)((t), (h), (o), (v))
92#define bus_space_write_8(t, h, o, v) (*(t)->_space_write_8)((t), (h), (o), (v))
93
94#define bus_space_read_raw_2(t, h, o) \
95 generic_space_read_2((t), (h), (o))
96#define bus_space_read_raw_4(t, h, o) \
97 generic_space_read_4((t), (h), (o))
98#define bus_space_read_raw_8(t, h, o) \
99 generic_space_read_8((t), (h), (o))
100
101#define bus_space_write_raw_2(t, h, o, v) \
102 generic_space_write_2((t), (h), (o), (v))
103#define bus_space_write_raw_4(t, h, o, v) \
104 generic_space_write_4((t), (h), (o), (v))
105#define bus_space_write_raw_8(t, h, o, v) \
106 generic_space_write_8((t), (h), (o), (v))
107
108#define bus_space_read_raw_multi_2(t, h, a, b, l) \
109 (*(t)->_space_read_raw_2)((t), (h), (a), (b), (l))
110#define bus_space_read_raw_multi_4(t, h, a, b, l) \
111 (*(t)->_space_read_raw_4)((t), (h), (a), (b), (l))
112#define bus_space_read_raw_multi_8(t, h, a, b, l) \
113 (*(t)->_space_read_raw_8)((t), (h), (a), (b), (l))
114
115#define bus_space_write_raw_multi_2(t, h, a, b, l) \
116 (*(t)->_space_write_raw_2)((t), (h), (a), (b), (l))
117#define bus_space_write_raw_multi_4(t, h, a, b, l) \
118 (*(t)->_space_write_raw_4)((t), (h), (a), (b), (l))
119#define bus_space_write_raw_multi_8(t, h, a, b, l) \
120 (*(t)->_space_write_raw_8)((t), (h), (a), (b), (l))
121
122#define bus_space_map(t, o, s, c, p) (*(t)->_space_map)((t), (o), (s), (c), (p))
123#define bus_space_unmap(t, h, s) (*(t)->_space_unmap)((t), (h), (s))
124#define bus_space_subregion(t, h, o, s, p) \
125 (*(t)->_space_subregion)((t), (h), (o), (s), (p))
126
127#define BUS_SPACE_MAP_CACHEABLE 0x01
128#define BUS_SPACE_MAP_KSEG0 0x02
129#define BUS_SPACE_MAP_LINEAR 0x04
130#define BUS_SPACE_MAP_PREFETCHABLE 0x08
131
132#define bus_space_vaddr(t, h) (*(t)->_space_vaddr)((t), (h))
133#define bus_space_mmap(t, a, o, p, f) \
134 (*(t)->_space_mmap)((t), (a), (o), (p), (f))
135
136/*----------------------------------------------------------------------------*/
137#define bus_space_read_multi(n,m) \
138static __inline void \
139CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
140 bus_size_t o, CAT3(uint,m,_t) *x, size_t cnt) \
141{ \
142 while (cnt--) \
143 *x++ = CAT(bus_space_read_,n)(bst, bsh, o); \
144}
145
146bus_space_read_multi(1,8)
147bus_space_read_multi(2,16)
148bus_space_read_multi(4,32)
149bus_space_read_multi(8,64)
150
151/*----------------------------------------------------------------------------*/
152#define bus_space_read_region(n,m) \
153static __inline void \
154CAT(bus_space_read_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
155 bus_addr_t ba, CAT3(uint,m,_t) *x, size_t cnt) \
156{ \
157 while (cnt--) { \
158 *x++ = CAT(bus_space_read_,n)(bst, bsh, ba); \
159 ba += (n); \
160 } \
161}
162
163bus_space_read_region(1,8)
164bus_space_read_region(2,16)
165bus_space_read_region(4,32)
166bus_space_read_region(8,64)
167
168/*----------------------------------------------------------------------------*/
169#define bus_space_read_raw_region(n,m) \
170static __inline void \
171CAT(bus_space_read_raw_region_,n)(bus_space_tag_t bst, \
172 bus_space_handle_t bsh, \
173 bus_addr_t ba, uint8_t *x, size_t cnt) \
174{ \
175 cnt >>= ((n) >> 1); \
176 while (cnt--) { \
177 CAT(bus_space_read_raw_multi_,n)(bst, bsh, ba, x, (n)); \
178 ba += (n); \
179 x += (n); \
180 } \
181}
182
183bus_space_read_raw_region(2,16)
184bus_space_read_raw_region(4,32)
185bus_space_read_raw_region(8,64)
186
187/*----------------------------------------------------------------------------*/
188#define bus_space_write_multi(n,m) \
189static __inline void \
190CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
191 bus_size_t o, const CAT3(uint,m,_t) *x, size_t cnt) \
192{ \
193 while (cnt--) \
194 CAT(bus_space_write_,n)(bst, bsh, o, *x++); \
195}
196
197bus_space_write_multi(1,8)
198bus_space_write_multi(2,16)
199bus_space_write_multi(4,32)
200bus_space_write_multi(8,64)
201
202/*----------------------------------------------------------------------------*/
203#define bus_space_write_region(n,m) \
204static __inline void \
205CAT(bus_space_write_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
206 bus_addr_t ba, const CAT3(uint,m,_t) *x, size_t cnt) \
207{ \
208 while (cnt--) { \
209 CAT(bus_space_write_,n)(bst, bsh, ba, *x++); \
210 ba += (n); \
211 } \
212}
213
214bus_space_write_region(1,8)
215bus_space_write_region(2,16)
216bus_space_write_region(4,32)
217bus_space_write_region(8,64)
218
219/*----------------------------------------------------------------------------*/
220#define bus_space_write_raw_region(n,m) \
221static __inline void \
222CAT(bus_space_write_raw_region_,n)(bus_space_tag_t bst, \
223 bus_space_handle_t bsh, \
224 bus_addr_t ba, const uint8_t *x, size_t cnt) \
225{ \
226 cnt >>= ((n) >> 1); \
227 while (cnt--) { \
228 CAT(bus_space_write_raw_multi_,n)(bst, bsh, ba, x, (n)); \
229 ba += (n); \
230 x += (n); \
231 } \
232}
233
234bus_space_write_raw_region(2,16)
235bus_space_write_raw_region(4,32)
236bus_space_write_raw_region(8,64)
237
238/*----------------------------------------------------------------------------*/
239#define bus_space_set_region(n,m) \
240static __inline void \
241CAT(bus_space_set_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
242 bus_addr_t ba, CAT3(uint,m,_t) x, size_t cnt) \
243{ \
244 while (cnt--) { \
245 CAT(bus_space_write_,n)(bst, bsh, ba, x); \
246 ba += (n); \
247 } \
248}
249
250bus_space_set_region(1,8)
251bus_space_set_region(2,16)
252bus_space_set_region(4,32)
253bus_space_set_region(8,64)
254
255/*----------------------------------------------------------------------------*/
256static __inline void
257bus_space_copy_1(void *v, bus_space_handle_t h1, bus_size_t o1,
258 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
259{
260 char *s = (char *)(h1 + o1);
261 char *d = (char *)(h2 + o2);
262
263 while (c--)
264 *d++ = *s++;
265}
266
267
268static __inline void
269bus_space_copy_2(void *v, bus_space_handle_t h1, bus_size_t o1,
270 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
271{
272 short *s = (short *)(h1 + o1);
273 short *d = (short *)(h2 + o2);
274
275 while (c--)
276 *d++ = *s++;
277}
278
279static __inline void
280bus_space_copy_4(void *v, bus_space_handle_t h1, bus_size_t o1,
281 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
282{
283 int *s = (int *)(h1 + o1);
284 int *d = (int *)(h2 + o2);
285
286 while (c--)
287 *d++ = *s++;
288}
289
290static __inline void
291bus_space_copy_8(void *v, bus_space_handle_t h1, bus_size_t o1,
292 bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
293{
294 int64_t *s = (int64_t *)(h1 + o1);
295 int64_t *d = (int64_t *)(h2 + o2);
296
297 while (c--)
298 *d++ = *s++;
299}
300
301/*----------------------------------------------------------------------------*/
302/*
303 * Bus read/write barrier methods.
304 *
305 * void bus_space_barrier(bus_space_tag_t tag,
306 * bus_space_handle_t bsh, bus_size_t offset,
307 * bus_size_t len, int flags);
308 *
309 */
310static inline void
311bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offset,
312 bus_size_t length, int flags)
313{
314 __asm__ volatile ("eieio" ::: "memory");
315}
316#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
317#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
318
319#define BUS_DMA_WAITOK 0x0000
320#define BUS_DMA_NOWAIT 0x0001
321#define BUS_DMA_ALLOCNOW 0x0002
322#define BUS_DMA_COHERENT 0x0008
323#define BUS_DMA_BUS1 0x0010 /* placeholders for bus functions... */
324#define BUS_DMA_BUS2 0x0020
325#define BUS_DMA_BUS3 0x0040
326#define BUS_DMA_BUS4 0x0080
327#define BUS_DMA_READ 0x0100 /* mapping is device -> memory only */
328#define BUS_DMA_WRITE 0x0200 /* mapping is memory -> device only */
329#define BUS_DMA_STREAMING 0x0400 /* hint: sequential, unidirectional */
330#define BUS_DMA_ZERO 0x0800 /* zero memory in dmamem_alloc */
331#define BUS_DMA_NOCACHE 0x1000
332#define BUS_DMA_64BIT 0x2000 /* device handles 64bit dva */
333
334/* Forwards needed by prototypes below. */
335struct mbuf;
336struct proc;
337struct uio;
338
339#define BUS_DMASYNC_POSTREAD 0x0001
340#define BUS_DMASYNC_POSTWRITE 0x0002
341#define BUS_DMASYNC_PREREAD 0x0004
342#define BUS_DMASYNC_PREWRITE 0x0008
343
344typedef struct machine_bus_dma_tag *bus_dma_tag_t;
345typedef struct machine_bus_dmamap *bus_dmamap_t;
346
347/*
348 * bus_dma_segment_t
349 *
350 * Describes a single contiguous DMA transaction. Values
351 * are suitable for programming into DMA registers.
352 */
353struct machine_bus_dma_segment {
354 bus_addr_t ds_addr; /* DMA address */
355 bus_size_t ds_len; /* length of transfer */
356
357 paddr_t _ds_paddr; /* CPU address */
358 vaddr_t _ds_vaddr; /* CPU address */
359};
360typedef struct machine_bus_dma_segment bus_dma_segment_t;
361
362/*
363 * bus_dma_tag_t
364 *
365 * A machine-dependent opaque type describing the implementation of
366 * DMA for a given bus.
367 */
368
369struct machine_bus_dma_tag {
370 void *_cookie; /* cookie used in the guts */
371 int _flags; /* misc. flags */
372
373 /*
374 * DMA mapping methods.
375 */
376 int (*_dmamap_create)(bus_dma_tag_t , bus_size_t, int,
377 bus_size_t, bus_size_t, int, bus_dmamap_t *);
378 void (*_dmamap_destroy)(bus_dma_tag_t , bus_dmamap_t);
379 int (*_dmamap_load)(bus_dma_tag_t , bus_dmamap_t, void *,
380 bus_size_t, struct proc *, int);
381 int (*_dmamap_load_mbuf)(bus_dma_tag_t , bus_dmamap_t,
382 struct mbuf *, int);
383 int (*_dmamap_load_uio)(bus_dma_tag_t , bus_dmamap_t,
384 struct uio *, int);
385 int (*_dmamap_load_raw)(bus_dma_tag_t , bus_dmamap_t,
386 bus_dma_segment_t *, int, bus_size_t, int);
387 int (*_dmamap_load_buffer)(bus_dma_tag_t, bus_dmamap_t, void *,
388 bus_size_t, struct proc *, int, paddr_t *, int *, int);
389 void (*_dmamap_unload)(bus_dma_tag_t , bus_dmamap_t);
390 void (*_dmamap_sync)(bus_dma_tag_t , bus_dmamap_t,
391 bus_addr_t, bus_size_t, int);
392
393 /*
394 * DMA memory utility functions.
395 */
396 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
397 bus_size_t, bus_dma_segment_t *, int, int *, int);
398 void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int);
399 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
400 int, size_t, caddr_t *, int);
401 void (*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
402 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
403 int, off_t, int, int);
404
405 /*
406 * internal memory address translation information.
407 */
408 bus_addr_t _dma_mask;
409};
410
411#define bus_dmamap_create(t, s, n, m, b, f, p) \
412 (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
413#define bus_dmamap_destroy(t, p) \
414 (*(t)->_dmamap_destroy)((t), (p))
415#define bus_dmamap_load(t, m, b, s, p, f) \
416 (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
417#define bus_dmamap_load_mbuf(t, m, b, f) \
418 (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
419#define bus_dmamap_load_uio(t, m, u, f) \
420 (*(t)->_dmamap_load_uio)((t), (m), (u), (f))
421#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
422 (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
423#define bus_dmamap_unload(t, p) \
424 (*(t)->_dmamap_unload)((t), (p))
425#define bus_dmamap_sync(t, p, a, l, o) \
426 (void)((t)->_dmamap_sync ? \
427 (*(t)->_dmamap_sync)((t), (p), (a), (l), (o)) : (void)0)
428
429#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
430 (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
431#define bus_dmamem_free(t, sg, n) \
432 (*(t)->_dmamem_free)((t), (sg), (n))
433#define bus_dmamem_map(t, sg, n, s, k, f) \
434 (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
435#define bus_dmamem_unmap(t, k, s) \
436 (*(t)->_dmamem_unmap)((t), (k), (s))
437#define bus_dmamem_mmap(t, sg, n, o, p, f) \
438 (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
439
440int _dmamap_create(bus_dma_tag_t, bus_size_t, int,
441 bus_size_t, bus_size_t, int, bus_dmamap_t *);
442void _dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
443int _dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
444 bus_size_t, struct proc *, int);
445int _dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int);
446int _dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int);
447int _dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
448 bus_dma_segment_t *, int, bus_size_t, int);
449int _dmamap_load_buffer(bus_dma_tag_t, bus_dmamap_t, void *,
450 bus_size_t, struct proc *, int, paddr_t *, int *, int);
451void _dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
452void _dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
453 bus_size_t, int);
454
455int _dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t,
456 bus_size_t, bus_dma_segment_t *, int, int *, int);
457void _dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int);
458int _dmamem_map(bus_dma_tag_t, bus_dma_segment_t *,
459 int, size_t, caddr_t *, int);
460void _dmamem_unmap(bus_dma_tag_t, caddr_t, size_t);
461paddr_t _dmamem_mmap(bus_dma_tag_t, bus_dma_segment_t *, int, off_t, int, int);
462int _dmamem_alloc_range(bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t,
463 bus_dma_segment_t *, int, int *, int, paddr_t, paddr_t);
464
465/*
466 * bus_dmamap_t
467 *
468 * Describes a DMA mapping.
469 */
470struct machine_bus_dmamap {
471 /*
472 * PRIVATE MEMBERS: not for use by machine-independent code.
473 */
474 bus_size_t _dm_size; /* largest DMA transfer mappable */
475 int _dm_segcnt; /* number of segs this map can map */
476 bus_size_t _dm_maxsegsz; /* largest possible segment */
477 bus_size_t _dm_boundary; /* don't cross this */
478 int _dm_flags; /* misc. flags */
479
480 void *_dm_cookie; /* cookie for bus-specific functions */
481
482 /*
483 * PUBLIC MEMBERS: these are used by machine-independent code.
484 */
485 bus_size_t dm_mapsize; /* size of the mapping */
486 int dm_nsegs; /* # valid segments in mapping */
487 bus_dma_segment_t dm_segs[1]; /* segments; variable length */
488};
489
490int generic_space_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
491 bus_space_handle_t *);
492void generic_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
493int generic_space_region(bus_space_tag_t, bus_space_handle_t, bus_size_t,
494 bus_size_t, bus_space_handle_t *);
495void *generic_space_vaddr(bus_space_tag_t, bus_space_handle_t);
496paddr_t generic_space_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
497uint8_t generic_space_read_1(bus_space_tag_t, bus_space_handle_t, bus_size_t);
498uint16_t generic_space_read_2(bus_space_tag_t, bus_space_handle_t, bus_size_t);
499uint32_t generic_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);
500uint64_t generic_space_read_8(bus_space_tag_t, bus_space_handle_t, bus_size_t);
501void generic_space_write_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
502 uint8_t);
503void generic_space_write_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
504 uint16_t);
505void generic_space_write_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
506 uint32_t);
507void generic_space_write_8(bus_space_tag_t, bus_space_handle_t, bus_size_t,
508 uint64_t);
509void generic_space_read_raw_2(bus_space_tag_t, bus_space_handle_t,
510 bus_addr_t, uint8_t *, bus_size_t);
511void generic_space_write_raw_2(bus_space_tag_t, bus_space_handle_t,
512 bus_addr_t, const uint8_t *, bus_size_t);
513void generic_space_read_raw_4(bus_space_tag_t, bus_space_handle_t,
514 bus_addr_t, uint8_t *, bus_size_t);
515void generic_space_write_raw_4(bus_space_tag_t, bus_space_handle_t,
516 bus_addr_t, const uint8_t *, bus_size_t);
517void generic_space_read_raw_8(bus_space_tag_t, bus_space_handle_t,
518 bus_addr_t, uint8_t *, bus_size_t);
519void generic_space_write_raw_8(bus_space_tag_t, bus_space_handle_t,
520 bus_addr_t, const uint8_t *, bus_size_t);
521
522uint16_t little_space_read_2(bus_space_tag_t, bus_space_handle_t, bus_size_t);
523uint32_t little_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);
524uint64_t little_space_read_8(bus_space_tag_t, bus_space_handle_t, bus_size_t);
525void little_space_write_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
526 uint16_t);
527void little_space_write_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
528 uint32_t);
529void little_space_write_8(bus_space_tag_t, bus_space_handle_t, bus_size_t,
530 uint64_t);
531
532#endif /* _MACHINE_BUS_H_ */