1/* $OpenBSD: opal.h,v 1.19 2021/01/23 12:10:08 kettenis Exp $ */
2
3/*
4 * Copyright (c) 2020 Mark Kettenis <kettenis@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#ifndef _MACHINE_OPAL_H_
20#define _MACHINE_OPAL_H_
21
22/* Tokens. */
23#define OPAL_TEST 0
24#define OPAL_CONSOLE_WRITE 1
25#define OPAL_CONSOLE_READ 2
26#define OPAL_RTC_READ 3
27#define OPAL_RTC_WRITE 4
28#define OPAL_CEC_POWER_DOWN 5
29#define OPAL_CEC_REBOOT 6
30#define OPAL_HANDLE_INTERRUPT 9
31#define OPAL_POLL_EVENTS 10
32#define OPAL_PCI_CONFIG_READ_WORD 15
33#define OPAL_PCI_CONFIG_WRITE_WORD 18
34#define OPAL_SET_XIVE 19
35#define OPAL_GET_XIVE 20
36#define OPAL_PCI_EEH_FREEZE_STATUS 23
37#define OPAL_PCI_EEH_FREEZE_CLEAR 26
38#define OPAL_PCI_PHB_MMIO_ENABLE 27
39#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
40#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
41#define OPAL_PCI_SET_PE 31
42#define OPAL_PCI_SET_XIVE_PE 37
43#define OPAL_GET_MSI_32 39
44#define OPAL_GET_MSI_64 40
45#define OPAL_START_CPU 41
46#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
47#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
48#define OPAL_PCI_RESET 49
49#define OPAL_REINIT_CPUS 70
50#define OPAL_CHECK_TOKEN 80
51#define OPAL_SENSOR_READ 88
52#define OPAL_IPMI_SEND 107
53#define OPAL_IPMI_RECV 108
54#define OPAL_CONSOLE_FLUSH 117
55#define OPAL_XIVE_RESET 128
56#define OPAL_XIVE_GET_IRQ_INFO 129
57#define OPAL_XIVE_GET_IRQ_CONFIG 131
58#define OPAL_XIVE_SET_IRQ_CONFIG 131
59#define OPAL_XIVE_GET_QUEUE_INFO 132
60#define OPAL_XIVE_SET_QUEUE_INFO 133
61#define OPAL_XIVE_GET_VP_INFO 137
62#define OPAL_XIVE_SET_VP_INFO 138
63#define OPAL_XIVE_DUMP 142
64#define OPAL_SENSOR_READ_U64 162
65
66/* Return codes. */
67#define OPAL_SUCCESS 0
68#define OPAL_PARAMETER -1
69#define OPAL_BUSY -2
70#define OPAL_PARTIAL -3
71#define OPAL_CONSTRAINED -4
72#define OPAL_CLOSED -5
73#define OPAL_HARDWARE -6
74#define OPAL_UNSUPPORTED -7
75#define OPAL_PERMISSION -8
76#define OPAL_NO_MEM -9
77#define OPAL_RESOURCE -10
78#define OPAL_INTERNAL_ERROR -11
79#define OPAL_BUSY_EVENT -12
80#define OPAL_HARDWARE_FROZEN -13
81#define OPAL_WRONG_STATE -14
82#define OPAL_ASYNC_COMPLETION -15
83#define OPAL_EMPTY -16
84
85/* OPAL_POLL_EVENT */
86#define OPAL_EVENT_CONSOLE_OUTPUT 0x00000008
87#define OPAL_EVENT_CONSOLE_INPUT 0x00000010
88
89/* OPAL_PCI_EEH_FREEZE_CLEAR */
90#define OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO 1
91#define OPAL_EEH_ACTION_CLEAR_FREEZE_DMA 2
92#define OPAL_EEH_ACTION_CLEAR_FREEZE_ALL 3
93
94/* OPAL_PCI_PHB_MMIO_ENABLE */
95#define OPAL_M32_WINDOW_TYPE 1
96#define OPAL_M64_WINDOW_TYPE 2
97#define OPAL_IO_WINDOW_TYPE 3
98#define OPAL_DISABLE_M64 0
99#define OPAL_ENABLE_M64_SPLIT 1
100#define OPAL_ENABLE_M64_NON_SPLIT 2
101
102/* OPAL_PCIE_SET_PE */
103#define OPAL_IGNORE_RID_BUS_NUMBER 0
104#define OPAL_IGNORE_RID_DEVICE_NUMBER 0
105#define OPAL_COMPARE_RID_DEVICE_NUMBER 1
106#define OPAL_IGNORE_RID_FUNCTION_NUMBER 0
107#define OPAL_COMPARE_RID_FUNCTION_NUMBER 1
108#define OPAL_UNMAP_PE 0
109#define OPAL_MAP_PE 1
110
111/* OPAL_PCI_RESET */
112#define OPAL_RESET_PHB_COMPLETE 1
113#define OPAL_RESET_PCI_LINK 2
114#define OPAL_RESET_PHB_ERROR 3
115#define OPAL_RESET_PCI_HOT 4
116#define OPAL_RESET_PCI_FUNDAMENTAL 5
117#define OPAL_RESET_PCI_IODA_TABLE 6
118#define OPAL_DEASSERT_RESET 0
119#define OPAL_ASSERT_RESET 1
120
121/* OPAL_REINIT_CPUS */
122#define OPAL_REINIT_CPUS_HILE_BE 0x00000001
123#define OPAL_REINIT_CPUS_HILE_LE 0x00000002
124#define OPAL_REINIT_CPUS_MMU_HASH 0x00000004
125#define OPAL_REINIT_CPUS_MMU_RADIX 0x00000008
126#define OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED 0x00000010
127
128/* OPAL_CHECK_TOKEN */
129#define OPAL_TOKEN_ABSENT 0
130#define OPAL_TOKEN_PRESENT 1
131
132/* OPAL_IPMI_SEND/RECV */
133#define OPAL_IPMI_MSG_FORMAT_VERSION_1 1
134
135#ifndef _LOCORE
136struct opal_ipmi_msg {
137 uint8_t version;
138 uint8_t netfn;
139 uint8_t cmd;
140 uint8_t data[0];
141};
142#endif
143
144/* OPAL_XIVE_RESET */
145#define OPAL_XIVE_MODE_EMU 0
146#define OPAL_XIVE_MODE_EXPL 1
147
148/* OPAL_XIVE_GET_IRQ_INFO */
149#define OPAL_XIVE_IRQ_TRIGGER_PAGE 0x00000001
150#define OPAL_XIVE_IRQ_STORE_EOI 0x00000002
151#define OPAL_XIVE_IRQ_LSI 0x00000004
152#define OPAL_XIVE_IRQ_SHIFT_BUG 0x00000008
153#define OPAL_XIVE_IRQ_MASK_VIA_FW 0x00000010
154#define OPAL_XIVE_IRQ_EOI_VIA_FW 0x00000020
155
156/* OPAL_XIVE_GET_QUEUE_INFO */
157#define OPAL_XIVE_EQ_ENABLED 0x00000001
158#define OPAL_XIVE_EQ_ALWAYS_NOTIFY 0x00000002
159#define OPAL_XIVE_EQ_ESCALATE 0x00000004
160
161/* OPAL_XIVE_GET_VP_INFO */
162#define OPAL_XIVE_VP_ENABLED 0x00000001
163#define OPAL_XIVE_VP_SINGLE_ESCALATION 0x00000002
164
165/* OPAL_XIVE_DUMP */
166#define XIVE_DUMP_TM_HYP 0x00000000
167#define XIVE_DUMP_TM_POOL 0x00000001
168#define XIVE_DUMP_TM_OS 0x00000002
169#define XIVE_DUMP_TM_USER 0x00000003
170#define XIVE_DUMP_VP 0x00000004
171#define XIVE_DUMP_EMU_STATE 0x00000005
172
173#ifndef _LOCORE
174
175void *opal_phys(void *);
176
177int64_t opal_test(uint64_t);
178int64_t opal_console_write(int64_t, int64_t *, const uint8_t *);
179int64_t opal_console_read(int64_t, int64_t *, uint8_t *);
180int64_t opal_rtc_read(uint32_t *, uint64_t *);
181int64_t opal_rtc_write(uint32_t, uint64_t);
182int64_t opal_cec_power_down(uint64_t);
183int64_t opal_cec_reboot(void);
184int64_t opal_handle_interrupt(uint32_t, uint64_t *);
185int64_t opal_poll_events(uint64_t *);
186int64_t opal_pci_config_read_word(uint64_t, uint64_t, uint64_t, uint32_t *);
187int64_t opal_pci_config_write_word(uint64_t, uint64_t, uint64_t, uint32_t);
188int64_t opal_set_xive(uint32_t, uint16_t, uint8_t);
189int64_t opal_get_xive(uint32_t, uint16_t *, uint8_t *);
190int64_t opal_pci_eeh_freeze_status(uint64_t, uint64_t, uint8_t *,
191 uint16_t *, uint64_t *);
192int64_t opal_pci_eeh_freeze_clear(uint64_t, uint64_t, uint64_t);
193int64_t opal_pci_phb_mmio_enable(uint64_t, uint16_t, uint16_t, uint16_t);
194int64_t opal_pci_set_phb_mem_window(uint64_t, uint16_t, uint16_t,
195 uint64_t, uint64_t, uint64_t);
196int64_t opal_pci_map_pe_mmio_window(uint64_t, uint64_t, uint16_t,
197 uint16_t, uint16_t);
198int64_t opal_pci_set_pe(uint64_t, uint64_t, uint64_t, uint8_t, uint8_t,
199 uint8_t, uint8_t);
200int64_t opal_pci_set_xive_pe(uint64_t, uint64_t, uint32_t);
201int64_t opal_get_msi_32(uint64_t, uint32_t, uint32_t, uint8_t,
202 uint32_t *, uint32_t *);
203int64_t opal_get_msi_64(uint64_t, uint32_t, uint32_t, uint8_t,
204 uint64_t *, uint32_t *);
205int64_t opal_start_cpu(uint64_t, uint64_t);
206int64_t opal_pci_map_pe_dma_window(uint64_t, uint64_t, uint16_t, uint16_t,
207 uint64_t, uint64_t, uint64_t);
208int64_t opal_pci_map_pe_dma_window_real(uint64_t, uint64_t, uint16_t,
209 uint64_t, uint64_t);
210int64_t opal_pci_reset(uint64_t, uint8_t, uint8_t);
211int64_t opal_reinit_cpus(uint64_t);
212int64_t opal_check_token(uint64_t);
213int64_t opal_sensor_read(uint32_t, int, uint32_t *);
214int64_t opal_ipmi_send(uint64_t, struct opal_ipmi_msg *, uint64_t);
215int64_t opal_ipmi_recv(uint64_t, struct opal_ipmi_msg *, uint64_t *);
216int64_t opal_console_flush(uint64_t);
217int64_t opal_xive_reset(uint64_t);
218int64_t opal_xive_get_irq_info(uint32_t, uint64_t *, uint64_t *,
219 uint64_t *, uint32_t *, uint32_t *);
220int64_t opal_xive_get_irq_config(uint32_t, uint64_t *, uint8_t *, uint32_t *);
221int64_t opal_xive_set_irq_config(uint32_t, uint64_t, uint8_t, uint32_t);
222int64_t opal_xive_get_queue_info(uint64_t, uint8_t, uint64_t *,
223 uint64_t *, uint64_t *, uint32_t *, uint64_t *);
224int64_t opal_xive_set_queue_info(uint64_t, uint8_t, uint64_t,
225 uint64_t, uint64_t);
226int64_t opal_xive_get_vp_info(uint64_t, uint64_t *, uint64_t *,
227 uint64_t *, uint32_t *);
228int64_t opal_xive_set_vp_info(uint64_t, uint64_t, uint64_t);
229int64_t opal_xive_dump(uint32_t, uint32_t);
230int64_t opal_sensor_read_u64(uint32_t, int, uint64_t *);
231
232void opal_printf(const char *fmt, ...);
233
234void *opal_intr_establish(uint64_t, int, int (*)(void *), void *);
235
236#endif
237
238#endif /* _MACHINE_OPAL_H_ */