1/* $OpenBSD: smbiosvar.h,v 1.3 2025/07/15 01:09:32 jsg Exp $ */
2/*
3 * Copyright (c) 2006 Gordon Willem Klok <gklok@cogeco.ca>
4 * Copyright (c) 2005 Jordan Hargrave
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR
20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef _MACHINE_SMBIOSVAR_
30#define _MACHINE_SMBIOSVAR_
31
32#define SMBIOS_UUID_NPRESENT 0x1
33#define SMBIOS_UUID_NSET 0x2
34
35/*
36 * Section 3.5 of "UUIDs and GUIDs" found at
37 * http://www.opengroup.org/dce/info/draft-leach-uuids-guids-01.txt
38 * specifies the string representation of a UUID.
39 */
40#define SMBIOS_UUID_REP "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x"
41#define SMBIOS_UUID_REPLEN 37 /* 16 zero padded values, 4 hyphens, 1 null */
42
43struct smbios_entry {
44 uint8_t mjr;
45 uint8_t min;
46 uint8_t *addr;
47 uint16_t len;
48 uint16_t count;
49};
50
51struct smbhdr {
52 uint32_t sig; /* "_SM_" */
53 uint8_t checksum; /* Entry point checksum */
54 uint8_t len; /* Entry point structure length */
55 uint8_t majrev; /* Specification major revision */
56 uint8_t minrev; /* Specification minor revision */
57 uint16_t mss; /* Maximum Structure Size */
58 uint8_t epr; /* Entry Point Revision */
59 uint8_t fa[5]; /* value determined by EPR */
60 uint8_t sasig[5]; /* Secondary Anchor "_DMI_" */
61 uint8_t sachecksum; /* Secondary Checksum */
62 uint16_t size; /* Length of structure table in bytes */
63 uint32_t addr; /* Structure table address */
64 uint16_t count; /* Number of SMBIOS structures */
65 uint8_t rev; /* BCD revision */
66} __packed;
67
68struct smb3hdr {
69 uint8_t sig[5]; /* "_SM3_" */
70 uint8_t checksum; /* Entry point structure checksum */
71 uint8_t len; /* Entry point length */
72 uint8_t majrev; /* SMBIOS major version */
73 uint8_t minrev; /* SMBIOS minor version */
74 uint8_t docrev; /* SMBIOS docrev */
75 uint8_t epr; /* Entry point revision */
76 uint8_t reserved; /* Reserved */
77 uint32_t size; /* Structure table maximum size */
78 uint64_t addr; /* Structure table address */
79} __packed;
80
81struct smbtblhdr {
82 uint8_t type;
83 uint8_t size;
84 uint16_t handle;
85} __packed;
86
87struct smbtable {
88 struct smbtblhdr *hdr;
89 void *tblhdr;
90 uint32_t cookie;
91};
92
93#define SMBIOS_TYPE_BIOS 0
94#define SMBIOS_TYPE_SYSTEM 1
95#define SMBIOS_TYPE_BASEBOARD 2
96#define SMBIOS_TYPE_ENCLOSURE 3
97#define SMBIOS_TYPE_PROCESSOR 4
98#define SMBIOS_TYPE_MEMCTRL 5
99#define SMBIOS_TYPE_MEMMOD 6
100#define SMBIOS_TYPE_CACHE 7
101#define SMBIOS_TYPE_PORT 8
102#define SMBIOS_TYPE_SLOTS 9
103#define SMBIOS_TYPE_OBD 10
104#define SMBIOS_TYPE_OEM 11
105#define SMBIOS_TYPE_SYSCONFOPT 12
106#define SMBIOS_TYPE_BIOSLANG 13
107#define SMBIOS_TYPE_GROUPASSOC 14
108#define SMBIOS_TYPE_SYSEVENTLOG 15
109#define SMBIOS_TYPE_PHYMEM 16
110#define SMBIOS_TYPE_MEMDEV 17
111#define SMBIOS_TYPE_ECCINFO32 18
112#define SMBIOS_TYPE_MEMMAPARRAYADDR 19
113#define SMBIOS_TYPE_MEMMAPDEVADDR 20
114#define SMBIOS_TYPE_INBUILTPOINT 21
115#define SMBIOS_TYPE_PORTBATT 22
116#define SMBIOS_TYPE_SYSRESET 23
117#define SMBIOS_TYPE_HWSECUIRTY 24
118#define SMBIOS_TYPE_PWRCTRL 25
119#define SMBIOS_TYPE_VOLTPROBE 26
120#define SMBIOS_TYPE_COOLING 27
121#define SMBIOS_TYPE_TEMPPROBE 28
122#define SMBIOS_TYPE_CURRENTPROBE 29
123#define SMBIOS_TYPE_OOB_REMOTEACCESS 30
124#define SMBIOS_TYPE_BIS 31
125#define SMBIOS_TYPE_SBI 32
126#define SMBIOS_TYPE_ECCINFO64 33
127#define SMBIOS_TYPE_MGMTDEV 34
128#define SMBIOS_TYPE_MGTDEVCOMP 35
129#define SMBIOS_TYPE_MGTDEVTHRESH 36
130#define SMBIOS_TYPE_MEMCHANNEL 37
131#define SMBIOS_TYPE_IPMIDEV 38
132#define SMBIOS_TYPE_SPS 39
133#define SMBIOS_TYPE_INACTIVE 126
134#define SMBIOS_TYPE_EOT 127
135
136/*
137 * SMBIOS Structure Type 0 "BIOS Information"
138 * DMTF Specification DSP0134 Section: 3.3.1 p.g. 34
139 */
140struct smbios_struct_bios {
141 uint8_t vendor; /* string */
142 uint8_t version; /* string */
143 uint16_t startaddr;
144 uint8_t release; /* string */
145 uint8_t romsize;
146 uint64_t characteristics;
147 uint32_t charext;
148 uint8_t major_rel;
149 uint8_t minor_rel;
150 uint8_t ecf_mjr_rel; /* embedded controller firmware */
151 uint8_t ecf_min_rel; /* embedded controller firmware */
152} __packed;
153
154/*
155 * SMBIOS Structure Type 1 "System Information"
156 * DMTF Specification DSP0134 Section 3.3.2 p.g. 35
157 */
158
159struct smbios_sys {
160/* SMBIOS spec 2.0+ */
161 uint8_t vendor; /* string */
162 uint8_t product; /* string */
163 uint8_t version; /* string */
164 uint8_t serial; /* string */
165/* SMBIOS spec 2.1+ */
166 uint8_t uuid[16];
167 uint8_t wakeup;
168/* SMBIOS spec 2.4+ */
169 uint8_t sku; /* string */
170 uint8_t family; /* string */
171} __packed;
172
173/*
174 * SMBIOS Structure Type 2 "Base Board (Module) Information"
175 * DMTF Specification DSP0134 Section 3.3.3 p.g. 37
176 */
177struct smbios_board {
178 uint8_t vendor; /* string */
179 uint8_t product; /* string */
180 uint8_t version; /* string */
181 uint8_t serial; /* string */
182 uint8_t asset; /* string */
183 uint8_t feature; /* feature flags */
184 uint8_t location; /* location in chassis */
185 uint16_t handle; /* chassis handle */
186 uint8_t type; /* board type */
187 uint8_t noc; /* number of contained objects */
188} __packed;
189
190/*
191 * SMBIOS Structure Type 3 "System Enclosure or Chassis"
192 * DMTF Specification DSP0134
193 */
194struct smbios_enclosure {
195 /* SMBIOS spec 2.0+ */
196 uint8_t vendor; /* string */
197 uint8_t type;
198 uint8_t version; /* string */
199 uint8_t serial; /* string */
200 uint8_t asset_tag; /* string */
201 /* SMBIOS spec 2.1+ */
202 uint8_t boot_state;
203 uint8_t psu_state;
204 uint8_t thermal_state;
205 uint8_t security_status;
206 /* SMBIOS spec 2.3+ */
207 uint16_t oem_defined;
208 uint8_t height;
209 uint8_t no_power_cords;
210 uint8_t no_contained_element;
211 uint8_t reclen_contained_element;
212 uint8_t contained_elements;
213 /* SMBIOS spec 2.7+ */
214 uint8_t sku; /* string */
215} __packed;
216
217/*
218 * SMBIOS Structure Type 4 "processor Information"
219 * DMTF Specification DSP0134 v2.5 Section 3.3.5 p.g. 24
220 */
221struct smbios_cpu {
222 uint8_t cpu_socket_designation; /* string */
223 uint8_t cpu_type;
224 uint8_t cpu_family;
225 uint8_t cpu_mfg; /* string */
226 uint32_t cpu_id_eax;
227 uint32_t cpu_id_edx;
228 uint8_t cpu_version; /* string */
229 uint8_t cpu_voltage;
230 uint16_t cpu_clock;
231 uint16_t cpu_max_speed;
232 uint16_t cpu_current_speed;
233 uint8_t cpu_status;
234#define SMBIOS_CPUST_POPULATED (1<<6)
235#define SMBIOS_CPUST_STATUSMASK (0x07)
236 uint8_t cpu_upgrade;
237 uint16_t cpu_l1_handle;
238 uint16_t cpu_l2_handle;
239 uint16_t cpu_l3_handle;
240 uint8_t cpu_serial; /* string */
241 uint8_t cpu_asset_tag; /* string */
242 uint8_t cpu_part_nr; /* string */
243 /* following fields were added in smbios 2.5 */
244 uint8_t cpu_core_count;
245 uint8_t cpu_core_enabled;
246 uint8_t cpu_thread_count;
247 uint16_t cpu_characteristics;
248} __packed;
249
250/*
251 * SMBIOS Structure Type 38 "IPMI Information"
252 * DMTF Specification DSP0134 Section 3.3.39 p.g. 91
253 */
254struct smbios_ipmi {
255 uint8_t smipmi_if_type; /* IPMI Interface Type */
256 uint8_t smipmi_if_rev; /* BCD IPMI Revision */
257 uint8_t smipmi_i2c_address; /* I2C address of BMC */
258 uint8_t smipmi_nvram_address; /* I2C address of NVRAM
259 * storage */
260 uint64_t smipmi_base_address; /* Base address of BMC (BAR
261 * format */
262 uint8_t smipmi_base_flags; /* Flags field:
263 * bit 7:6 : register spacing
264 * 00 = byte
265 * 01 = dword
266 * 02 = word
267 * bit 4 : Lower bit BAR
268 * bit 3 : IRQ valid
269 * bit 2 : N/A
270 * bit 1 : Interrupt polarity
271 * bit 0 : Interrupt trigger */
272 uint8_t smipmi_irq; /* IRQ if applicable */
273} __packed;
274
275int smbios_find_table(uint8_t, struct smbtable *);
276char *smbios_get_string(struct smbtable *, uint8_t, char *, size_t);
277
278#endif