| 1 | /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ |
| 2 | /* |
| 3 | * Copyright (C) 2012 ARM Ltd. |
| 4 | * Copyright (C) 2015 Regents of the University of California |
| 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_RISCV_AUXVEC_H |
| 8 | #define _ASM_RISCV_AUXVEC_H |
| 9 | |
| 10 | /* vDSO location */ |
| 11 | #define AT_SYSINFO_EHDR 33 |
| 12 | |
| 13 | /* |
| 14 | * The set of entries below represent more extensive information |
| 15 | * about the caches, in the form of two entry per cache type, |
| 16 | * one entry containing the cache size in bytes, and the other |
| 17 | * containing the cache line size in bytes in the bottom 16 bits |
| 18 | * and the cache associativity in the next 16 bits. |
| 19 | * |
| 20 | * The associativity is such that if N is the 16-bit value, the |
| 21 | * cache is N way set associative. A value if 0xffff means fully |
| 22 | * associative, a value of 1 means directly mapped. |
| 23 | * |
| 24 | * For all these fields, a value of 0 means that the information |
| 25 | * is not known. |
| 26 | */ |
| 27 | #define AT_L1I_CACHESIZE 40 |
| 28 | #define AT_L1I_CACHEGEOMETRY 41 |
| 29 | #define AT_L1D_CACHESIZE 42 |
| 30 | #define AT_L1D_CACHEGEOMETRY 43 |
| 31 | #define AT_L2_CACHESIZE 44 |
| 32 | #define AT_L2_CACHEGEOMETRY 45 |
| 33 | #define AT_L3_CACHESIZE 46 |
| 34 | #define AT_L3_CACHEGEOMETRY 47 |
| 35 | |
| 36 | /* entries in ARCH_DLINFO */ |
| 37 | #define AT_VECTOR_SIZE_ARCH 10 |
| 38 | #define AT_MINSIGSTKSZ 51 |
| 39 | |
| 40 | #endif /* _ASM_RISCV_AUXVEC_H */ |