1/* $OpenBSD: intr.h,v 1.10 2025/05/19 02:13:15 jsg Exp $ */
2
3/*
4 * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29#ifndef _MACHINE_INTR_H_
30#define _MACHINE_INTR_H_
31
32/*
33 * The interrupt level ipl is a logical level; per-platform interrupt
34 * code will turn it into the appropriate hardware interrupt masks
35 * values.
36 *
37 * Interrupt sources on the CPU are kept enabled regardless of the
38 * current ipl value; individual hardware sources interrupting while
39 * logically masked are masked on the fly, remembered as pending, and
40 * unmasked at the first splx() opportunity.
41 */
42#ifdef _KERNEL
43
44/* Interrupt priority `levels'; not mutually exclusive. */
45#define IPL_NONE 0 /* nothing */
46#define IPL_SOFTCLOCK 2 /* soft clock interrupts */
47#define IPL_SOFTNET 3 /* soft network interrupts */
48#define IPL_SOFTTTY 4 /* soft terminal interrupts */
49#define IPL_BIO 5 /* block I/O */
50#define IPL_NET 6 /* network */
51#define IPL_TTY 7 /* terminal */
52#define IPL_VM 8 /* memory allocation */
53#define IPL_AUDIO 9 /* audio */
54#define IPL_CLOCK 10 /* clock */
55#define IPL_SCHED IPL_CLOCK
56#define IPL_STATCLOCK IPL_CLOCK
57#define IPL_HIGH 11 /* everything */
58#define IPL_IPI 12 /* interprocessor interrupt */
59#define NIPL 13 /* number of levels */
60
61#define IPL_MPFLOOR IPL_TTY
62/* Interrupt priority 'flags'. */
63#define IPL_IRQMASK 0xf /* priority only */
64#define IPL_FLAGMASK 0xf00 /* flags only*/
65#define IPL_MPSAFE 0x100 /* 'mpsafe' interrupt, no kernel lock */
66
67/* Interrupt sharing types. */
68#define IST_NONE 0 /* none */
69#define IST_PULSE 1 /* pulsed */
70#define IST_EDGE 2 /* edge-triggered */
71#define IST_LEVEL 3 /* level-triggered */
72
73#define IST_LEVEL_LOW IST_LEVEL
74#define IST_LEVEL_HIGH 4
75#define IST_EDGE_FALLING IST_EDGE
76#define IST_EDGE_RISING 5
77#define IST_EDGE_BOTH 6
78
79enum {
80 IRQ_SOFTWARE_USER,
81 IRQ_SOFTWARE_SUPERVISOR,
82 IRQ_SOFTWARE_HYPERVISOR,
83 IRQ_SOFTWARE_MACHINE,
84 IRQ_TIMER_USER,
85 IRQ_TIMER_SUPERVISOR,
86 IRQ_TIMER_HYPERVISOR,
87 IRQ_TIMER_MACHINE,
88 IRQ_EXTERNAL_USER,
89 IRQ_EXTERNAL_SUPERVISOR,
90 IRQ_EXTERNAL_HYPERVISOR,
91 IRQ_EXTERNAL_MACHINE,
92 INTC_NIRQS
93};
94
95#define __USE_MI_SOFTINTR
96
97#include <sys/softintr.h>
98
99#ifndef _LOCORE
100#include <sys/queue.h>
101
102void softintr(int);
103
104int splraise(int);
105int spllower(int);
106void splx(int);
107
108void riscv_cpu_intr(void *);
109void riscv_do_pending_intr(int);
110void riscv_set_intr_func(int (*raise)(int), int (*lower)(int),
111 void (*x)(int), void (*setipl)(int));
112void riscv_set_intr_handler(void (*intr_handle)(void *));
113
114struct machine_intr_handle {
115 struct interrupt_controller *ih_ic;
116 void *ih_ih;
117};
118
119struct riscv_intr_func {
120 int (*raise)(int);
121 int (*lower)(int);
122 void (*x)(int);
123 void (*setipl)(int);
124};
125
126extern struct riscv_intr_func riscv_intr_func;
127
128#define splraise(cpl) (riscv_intr_func.raise(cpl))
129#define _splraise(cpl) (riscv_intr_func.raise(cpl))
130#define spllower(cpl) (riscv_intr_func.lower(cpl))
131#define splx(cpl) (riscv_intr_func.x(cpl))
132
133#define splsoftclock() splraise(IPL_SOFTCLOCK)
134#define splsoftnet() splraise(IPL_SOFTNET)
135#define splsofttty() splraise(IPL_SOFTTTY)
136#define splbio() splraise(IPL_BIO)
137#define splnet() splraise(IPL_NET)
138#define spltty() splraise(IPL_TTY)
139#define splvm() splraise(IPL_VM)
140#define splaudio() splraise(IPL_AUDIO)
141#define splclock() splraise(IPL_CLOCK)
142#define splsched() splraise(IPL_SCHED)
143#define splstatclock() splraise(IPL_STATCLOCK)
144#define splhigh() splraise(IPL_HIGH)
145
146#define spl0() spllower(IPL_NONE)
147
148void intr_barrier(void *);
149
150void riscv_init_smask(void); /* XXX */
151extern uint32_t riscv_smask[NIPL];
152
153void riscv_clock_register(void (*)(void), void (*)(u_int), void (*)(int),
154 void (*)(void));
155
156/*
157 **** interrupt controller structure and routines ****
158 */
159struct cpu_info;
160struct interrupt_controller {
161 int ic_node;
162 void *ic_cookie;
163 void *(*ic_establish)(void *, int *, int, struct cpu_info *,
164 int (*)(void *), void *, char *);
165 void *(*ic_establish_msi)(void *, uint64_t *, uint64_t *, int,
166 struct cpu_info *, int (*)(void *), void *, char *);
167 void (*ic_disestablish)(void *);
168 void (*ic_enable)(void *);
169 void (*ic_disable)(void *);
170 void (*ic_route)(void *, int, struct cpu_info *);
171 void (*ic_cpu_enable)(void);
172 void (*ic_barrier)(void *);
173
174 LIST_ENTRY(interrupt_controller) ic_list;
175 uint32_t ic_phandle;
176 uint32_t ic_cells;
177};
178
179void riscv_intr_init_fdt(void);
180void riscv_intr_register_fdt(struct interrupt_controller *);
181void *riscv_intr_establish_fdt(int, int, int (*)(void *),
182 void *, char *);
183void *riscv_intr_establish_fdt_idx(int, int, int, int (*)(void *),
184 void *, char *);
185void *riscv_intr_establish_fdt_idx_cpu(int, int, int, struct cpu_info *,
186 int (*)(void *), void *, char *);
187void *riscv_intr_establish_fdt_imap_cpu(int, int *, int, int,
188 struct cpu_info *, int (*)(void *), void *, char *);
189void *riscv_intr_establish_fdt_msi(int, uint64_t *, uint64_t *, int,
190 int (*)(void *), void *, char *);
191void *riscv_intr_establish_fdt_msi_cpu(int, uint64_t *, uint64_t *, int,
192 struct cpu_info *, int (*)(void *), void *, char *);
193void riscv_intr_disestablish_fdt(void *);
194void riscv_intr_enable(void *);
195void riscv_intr_disable(void *);
196void riscv_intr_route(void *, int, struct cpu_info *);
197void riscv_intr_cpu_enable(void);
198
199#define IPI_NOP 0
200#define IPI_DDB (1 << 0)
201
202void intr_send_ipi(struct cpu_info *, int);
203
204#ifdef DIAGNOSTIC
205/*
206 * Although this function is implemented in MI code, it must be in this MD
207 * header because we don't want this header to include MI includes.
208 */
209void splassert_fail(int, int, const char *);
210extern int splassert_ctl;
211void riscv_splassert_check(int, const char *);
212#define splassert(__wantipl) do { \
213 if (splassert_ctl > 0) { \
214 riscv_splassert_check(__wantipl, __func__); \
215 } \
216} while (0)
217#define splsoftassert(wantipl) splassert(wantipl)
218#else
219#define splassert(wantipl) do { /* nothing */ } while (0)
220#define splsoftassert(wantipl) do { /* nothing */ } while (0)
221#endif
222
223#endif /* ! _LOCORE */
224
225#endif /* _KERNEL */
226
227#endif /* _MACHINE_INTR_H_ */