1/* $OpenBSD: bus.h,v 1.38 2024/10/22 22:01:58 jsg Exp $ */
2/* $NetBSD: bus.h,v 1.31 2001/09/21 15:30:41 wiz Exp $ */
3
4/*-
5 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34/*
35 * Copyright (c) 1997-1999, 2001 Eduardo E. Horvath. All rights reserved.
36 * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
37 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * 2. Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in the
46 * documentation and/or other materials provided with the distribution.
47 * 3. All advertising materials mentioning features or use of this software
48 * must display the following acknowledgement:
49 * This product includes software developed by Christopher G. Demetriou
50 * for the NetBSD Project.
51 * 4. The name of the author may not be used to endorse or promote products
52 * derived from this software without specific prior written permission
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 */
65
66#ifndef _MACHINE_BUS_H_
67#define _MACHINE_BUS_H_
68
69#include <sys/atomic.h>
70
71#ifdef _KERNEL
72
73/*
74 * Debug hooks
75 */
76
77#define BSDB_ACCESS 0x01
78#define BSDB_MAP 0x02
79#define BSDB_ASSERT 0x04
80#define BSDB_MAPDETAIL 0x08
81#define BSDB_ALL_ACCESS 0x10
82extern int bus_space_debug;
83
84#define BSHDB_ACCESS 0x01
85#define BSHDB_NO_ACCESS 0x02
86
87#if defined(BUS_SPACE_DEBUG)
88#include <sys/systm.h>
89#define BUS_SPACE_PRINTF(l, s) do { \
90 if(bus_space_debug & (l)) printf s; \
91} while(0)
92#define BUS_SPACE_TRACE(t, h, s) do { \
93 if ( (((bus_space_debug & BSDB_ALL_ACCESS) != 0) && \
94 (((h).bh_flags & BSHDB_NO_ACCESS) == 0)) || \
95 (((bus_space_debug & BSDB_ACCESS) != 0) && \
96 (((h).bh_flags & BSHDB_ACCESS) != 0))) \
97 printf s; \
98 } while(0)
99#define BUS_SPACE_SET_FLAGS(t, h, f) ((h).bh_flags |= (f))
100#define BUS_SPACE_CLEAR_FLAGS(t, h, f) ((h).bh_flags &= ~(f))
101#define BUS_SPACE_FLAG_DECL(s) int s
102#define BUS_SPACE_SAVE_FLAGS(t, h, s) (s = (h).bh_flags)
103#define BUS_SPACE_RESTORE_FLAGS(t, h, s) (s = (h).bh_flags)
104#define BUS_SPACE_ASSERT(t, h, o, n) do { \
105 if (bus_space_debug & BSDB_ASSERT) \
106 bus_space_assert(t, &(h), o, n); \
107 } while(0)
108#else /* BUS_SPACE_DEBUG */
109#define BUS_SPACE_PRINTF(l, s)
110#define BUS_SPACE_TRACE(t, h, s)
111#define BUS_SPACE_SET_FLAGS(t, h, f)
112#define BUS_SPACE_CLEAR_FLAGS(t, h, f)
113#define BUS_SPACE_FLAG_DECL(s)
114#define BUS_SPACE_SAVE_FLAGS(t, h, s)
115#define BUS_SPACE_RESTORE_FLAGS(t, h, s)
116#define BUS_SPACE_ASSERT(t, h, o, n)
117#endif /* BUS_SPACE_DEBUG */
118
119
120/*
121 * UPA and SBus spaces are non-cached and big endian
122 * (except for RAM and PROM)
123 *
124 * PCI spaces are non-cached and little endian
125 */
126
127enum sparc_bus_type {
128 UPA_BUS_SPACE,
129 SBUS_BUS_SPACE,
130 PCI_CONFIG_BUS_SPACE,
131 PCI_IO_BUS_SPACE,
132 PCI_MEMORY_BUS_SPACE,
133 LAST_BUS_SPACE
134};
135/* For backwards compatibility */
136#define SPARC_BUS_SPACE UPA_BUS_SPACE
137
138/*
139 * Bus address and size types
140 */
141typedef const struct sparc_bus_space_tag *bus_space_tag_t;
142typedef u_long bus_addr_t;
143typedef u_long bus_size_t;
144
145
146typedef struct _bus_space_handle {
147 paddr_t bh_ptr;
148#ifdef BUS_SPACE_DEBUG
149 bus_space_tag_t bh_tag;
150 bus_size_t bh_size;
151 int bh_flags;
152#endif
153} bus_space_handle_t;
154
155/* For buses which have an iospace. */
156#define BUS_ADDR_IOSPACE(x) ((x)>>32)
157#define BUS_ADDR_PADDR(x) ((x)&0xffffffff)
158#define BUS_ADDR(io, pa) ((((bus_addr_t)io)<<32)|(pa))
159
160/*
161 * Access methods for bus resources and address space.
162 */
163
164struct sparc_bus_space_tag {
165 void *cookie;
166 bus_space_tag_t parent;
167 enum sparc_bus_type default_type;
168 u_int8_t asi;
169 u_int8_t sasi;
170 char name[32];
171
172 int (*sparc_bus_alloc)(bus_space_tag_t,
173 bus_space_tag_t,
174 bus_addr_t, bus_addr_t,
175 bus_size_t, bus_size_t, bus_size_t,
176 int, bus_addr_t *, bus_space_handle_t *);
177
178 void (*sparc_bus_free)(bus_space_tag_t,
179 bus_space_tag_t,
180 bus_space_handle_t, bus_size_t);
181
182 int (*sparc_bus_map)(bus_space_tag_t,
183 bus_space_tag_t,
184 bus_addr_t, bus_size_t,
185 int, bus_space_handle_t *);
186
187 int (*sparc_bus_protect)(bus_space_tag_t,
188 bus_space_tag_t,
189 bus_space_handle_t, bus_size_t, int);
190
191 int (*sparc_bus_unmap)(bus_space_tag_t,
192 bus_space_tag_t,
193 bus_space_handle_t, bus_size_t);
194
195 int (*sparc_bus_subregion)(bus_space_tag_t,
196 bus_space_tag_t,
197 bus_space_handle_t, bus_size_t,
198 bus_size_t, bus_space_handle_t *);
199
200 paddr_t (*sparc_bus_mmap)(bus_space_tag_t,
201 bus_space_tag_t,
202 bus_addr_t, off_t, int, int);
203
204 void *(*sparc_intr_establish)(bus_space_tag_t,
205 bus_space_tag_t,
206 int, int, int,
207 int (*)(void *), void *,
208 const char *);
209 void *(*sparc_intr_establish_cpu)(bus_space_tag_t,
210 bus_space_tag_t,
211 int, int, int,
212 struct cpu_info *,
213 int (*)(void *), void *,
214 const char *);
215
216 bus_addr_t (*sparc_bus_addr)(bus_space_tag_t,
217 bus_space_tag_t, bus_space_handle_t);
218};
219
220/*
221 * Bus space function prototypes.
222 */
223int bus_space_alloc(
224 bus_space_tag_t,
225 bus_addr_t, /* reg start */
226 bus_addr_t, /* reg end */
227 bus_size_t, /* size */
228 bus_size_t, /* alignment */
229 bus_size_t, /* boundary */
230 int, /* flags */
231 bus_addr_t *,
232 bus_space_handle_t *);
233void bus_space_free(
234 bus_space_tag_t,
235 bus_space_handle_t,
236 bus_size_t);
237int bus_space_map(
238 bus_space_tag_t,
239 bus_addr_t,
240 bus_size_t,
241 int, /*flags*/
242 bus_space_handle_t *);
243int bus_space_protect(
244 bus_space_tag_t,
245 bus_space_handle_t,
246 bus_size_t,
247 int); /*flags*/
248int bus_space_unmap(
249 bus_space_tag_t,
250 bus_space_handle_t,
251 bus_size_t);
252int bus_space_subregion(
253 bus_space_tag_t,
254 bus_space_handle_t,
255 bus_size_t,
256 bus_size_t,
257 bus_space_handle_t *);
258static void bus_space_barrier(
259 bus_space_tag_t,
260 bus_space_handle_t,
261 bus_size_t,
262 bus_size_t,
263 int);
264paddr_t bus_space_mmap(
265 bus_space_tag_t,
266 bus_addr_t, /*addr*/
267 off_t, /*offset*/
268 int, /*prot*/
269 int); /*flags*/
270void *bus_intr_establish(
271 bus_space_tag_t,
272 int, /*bus-specific intr*/
273 int, /*device class level,
274 see machine/intr.h*/
275 int, /*flags*/
276 int (*)(void *), /*handler*/
277 void *, /*handler arg*/
278 const char *); /*what*/
279void *bus_intr_establish_cpu(
280 bus_space_tag_t,
281 int, /*bus-specific intr*/
282 int, /*device class level,
283 see machine/intr.h*/
284 int, /*flags*/
285 struct cpu_info *, /*cpu*/
286 int (*)(void *), /*handler*/
287 void *, /*handler arg*/
288 const char *); /*what*/
289void *bus_intr_allocate(
290 bus_space_tag_t,
291 int (*)(void *), /*handler*/
292 void *, /*handler arg*/
293 int, /*number*/
294 int, /*pil*/
295 volatile u_int64_t *, /*map*/
296 volatile u_int64_t *, /*clr*/
297 const char *); /*what*/
298void bus_intr_free(void *);
299void bus_space_render_tag(
300 bus_space_tag_t,
301 char *,
302 size_t);
303void *bus_space_vaddr(
304 bus_space_tag_t,
305 bus_space_handle_t);
306
307#ifdef BUS_SPACE_DEBUG
308void bus_space_assert(bus_space_tag_t,
309 const bus_space_handle_t *,
310 bus_size_t, int);
311void bus_space_render_tag(bus_space_tag_t, char*, size_t);
312#endif /* BUS_SPACE_DEBUG */
313
314
315#define _BS_PRECALL(t,f) \
316 while (t->f == NULL) \
317 t = t->parent;
318#define _BS_POSTCALL
319
320#define _BS_CALL(t,f) \
321 (*(t)->f)
322
323/* flags for bus_space_barrier() */
324#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
325#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
326
327static inline void
328bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
329 bus_size_t s, int f)
330{
331#ifdef notyet
332 switch (f) {
333 case (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE):
334 __membar("#LoadLoad|#StoreStore");
335 break;
336 case BUS_SPACE_BARRIER_READ:
337 membar("#LoadLoad");
338 break;
339 case BUS_SPACE_BARRIER_WRITE:
340 membar("#StoreStore");
341 break;
342 default:
343 break;
344 }
345#else
346 __membar("#Sync");
347#endif
348}
349
350#include <sparc64/sparc64/busop.h>
351
352/* flags for bus space map functions */
353#define BUS_SPACE_MAP_CACHEABLE 0x0001
354#define BUS_SPACE_MAP_LINEAR 0x0002
355#define BUS_SPACE_MAP_READONLY 0x0004
356#define BUS_SPACE_MAP_PREFETCHABLE 0x0008
357#define BUS_SPACE_MAP_PROMADDRESS 0x0010
358#define BUS_SPACE_MAP_BUS1 0x0100 /* placeholders for bus functions... */
359#define BUS_SPACE_MAP_BUS2 0x0200
360#define BUS_SPACE_MAP_BUS3 0x0400
361#define BUS_SPACE_MAP_BUS4 0x0800
362
363
364/* flags for bus_intr_establish() */
365#define BUS_INTR_ESTABLISH_MPSAFE 0x0001
366#define BUS_INTR_ESTABLISH_SOFTINTR 0x0002
367
368/*
369 * Flags used in various bus DMA methods.
370 */
371#define BUS_DMA_WAITOK 0x0000 /* safe to sleep (pseudo-flag) */
372#define BUS_DMA_NOWAIT 0x0001 /* not safe to sleep */
373#define BUS_DMA_ALLOCNOW 0x0002 /* perform resource allocation now */
374#define BUS_DMA_COHERENT 0x0004 /* hint: map memory DMA coherent */
375#define BUS_DMA_NOWRITE 0x0008 /* I suppose the following two should default on */
376#define BUS_DMA_BUS1 0x0010 /* placeholders for bus functions... */
377#define BUS_DMA_BUS2 0x0020
378#define BUS_DMA_BUS3 0x0040
379#define BUS_DMA_BUS4 0x0080
380#define BUS_DMA_STREAMING 0x0100 /* hint: sequential, unidirectional */
381#define BUS_DMA_READ 0x0200 /* mapping is device -> memory only */
382#define BUS_DMA_WRITE 0x0400 /* mapping is memory -> device only */
383#define BUS_DMA_ZERO 0x0800 /* zero memory in dmamem_alloc */
384#define BUS_DMA_OVERRUN 0x1000 /* tolerate DMA overruns */
385#define BUS_DMA_64BIT 0x2000 /* device handles 64bit dva */
386
387#define BUS_DMA_NOCACHE BUS_DMA_BUS1
388#define BUS_DMA_DVMA BUS_DMA_BUS2 /* Don't bother with alignment */
389#define BUS_DMA_24BIT BUS_DMA_BUS3 /* 24bit device */
390
391#define BUS_DMA_RAW BUS_DMA_STREAMING
392
393/* Forwards needed by prototypes below. */
394struct mbuf;
395struct uio;
396
397/*
398 * Operations performed by bus_dmamap_sync().
399 */
400#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
401#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
402#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
403#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
404
405typedef struct sparc_bus_dma_tag *bus_dma_tag_t;
406typedef struct sparc_bus_dmamap *bus_dmamap_t;
407
408/*
409 * bus_dma_segment_t
410 *
411 * Describes a single contiguous DMA transaction. Values
412 * are suitable for programming into DMA registers.
413 */
414struct sparc_bus_dma_segment {
415 bus_addr_t ds_addr; /* DVMA address */
416 bus_size_t ds_len; /* length of transfer */
417 /*
418 * The following is to support bus_dmamem_alloc()'s
419 * odd interface. Only the values in the first
420 * segment are used. This means that 3/5ths of
421 * most segments are useless space (and mbufs use 1024
422 * segments).
423 */
424 bus_size_t _ds_boundary; /* don't cross this */
425 bus_size_t _ds_align; /* align to this */
426 void *_ds_mlist; /* XXX - dmamap_alloc'ed pages */
427};
428typedef struct sparc_bus_dma_segment bus_dma_segment_t;
429
430
431/*
432 * bus_dma_tag_t
433 *
434 * A machine-dependent opaque type describing the implementation of
435 * DMA for a given bus.
436 */
437struct sparc_bus_dma_tag {
438 void *_cookie; /* cookie used in the guts */
439 struct sparc_bus_dma_tag* _parent;
440
441 /*
442 * DMA mapping methods.
443 */
444 int (*_dmamap_create)(bus_dma_tag_t, bus_dma_tag_t, bus_size_t,
445 int, bus_size_t, bus_size_t, int, bus_dmamap_t *);
446 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t);
447 int (*_dmamap_load)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t,
448 void *, bus_size_t, struct proc *, int);
449 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dma_tag_t,
450 bus_dmamap_t, struct mbuf *, int);
451 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t,
452 struct uio *, int);
453 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t,
454 bus_dma_segment_t *, int, bus_size_t, int);
455 void (*_dmamap_unload)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t);
456 void (*_dmamap_sync)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t,
457 bus_addr_t, bus_size_t, int);
458
459 /*
460 * DMA memory utility functions.
461 */
462 int (*_dmamem_alloc)(bus_dma_tag_t, bus_dma_tag_t, bus_size_t,
463 bus_size_t, bus_size_t, bus_dma_segment_t *, int, int *,
464 int);
465 void (*_dmamem_free)(bus_dma_tag_t, bus_dma_tag_t,
466 bus_dma_segment_t *, int);
467 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_tag_t,
468 bus_dma_segment_t *, int, size_t, caddr_t *, int);
469 void (*_dmamem_unmap)(bus_dma_tag_t, bus_dma_tag_t, caddr_t,
470 size_t);
471 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_tag_t,
472 bus_dma_segment_t *, int, off_t, int, int);
473};
474
475#define _BD_PRECALL(t,f) \
476 while (t->f == NULL) { \
477 t = t->_parent; \
478 }
479#define _BD_CALL(t,f) \
480 (*(t)->f)
481#define _BD_POSTCALL
482
483static inline int
484bus_dmamap_create(bus_dma_tag_t t, bus_size_t s, int n, bus_size_t m,
485 bus_size_t b, int f, bus_dmamap_t *p)
486{
487 int r;
488 const bus_dma_tag_t t0 = t;
489 _BD_PRECALL(t, _dmamap_create);
490 r = _BD_CALL(t, _dmamap_create)(t, t0, s, n, m, b, f, p);
491 _BD_POSTCALL;
492 return (r);
493}
494static inline void
495bus_dmamap_destroy(bus_dma_tag_t t, bus_dmamap_t p)
496{
497 const bus_dma_tag_t t0 = t;
498 _BD_PRECALL(t, _dmamap_destroy);
499 _BD_CALL(t, _dmamap_destroy)(t, t0, p);
500 _BD_POSTCALL;
501}
502static inline int
503bus_dmamap_load(bus_dma_tag_t t, bus_dmamap_t m, void *b, bus_size_t s,
504 struct proc *p, int f)
505{
506 const bus_dma_tag_t t0 = t;
507 int r;
508 _BD_PRECALL(t, _dmamap_load);
509 r = _BD_CALL(t, _dmamap_load)(t, t0, m, b, s, p, f);
510 _BD_POSTCALL;
511 return (r);
512}
513static inline int
514bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t m, struct mbuf *b,
515 int f)
516{
517 const bus_dma_tag_t t0 = t;
518 int r;
519 _BD_PRECALL(t, _dmamap_load_mbuf);
520 r = _BD_CALL(t, _dmamap_load_mbuf)(t, t0, m, b, f);
521 _BD_POSTCALL;
522 return (r);
523}
524static inline int
525bus_dmamap_load_uio(bus_dma_tag_t t, bus_dmamap_t m, struct uio * u, int f)
526{
527 const bus_dma_tag_t t0 = t;
528 int r;
529 _BD_PRECALL(t, _dmamap_load_uio);
530 r = _BD_CALL(t, _dmamap_load_uio)(t, t0, m, u, f);
531 _BD_POSTCALL;
532 return (r);
533}
534static inline int
535bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t m, bus_dma_segment_t *sg,
536 int n, bus_size_t s, int f)
537{
538 const bus_dma_tag_t t0 = t;
539 int r;
540 _BD_PRECALL(t, _dmamap_load_raw);
541 r = _BD_CALL(t, _dmamap_load_raw)(t, t0, m, sg, n, s, f);
542 _BD_POSTCALL;
543 return (r);
544}
545static inline void
546bus_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t p)
547{
548 const bus_dma_tag_t t0 = t;
549 _BD_PRECALL(t, _dmamap_unload);
550 _BD_CALL(t, _dmamap_unload)(t, t0, p);
551 _BD_POSTCALL;
552}
553static inline void
554bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t p, bus_addr_t o, bus_size_t l,
555 int ops)
556{
557 const bus_dma_tag_t t0 = t;
558 _BD_PRECALL(t, _dmamap_sync);
559 _BD_CALL(t, _dmamap_sync)(t, t0, p, o, l, ops);
560 _BD_POSTCALL;
561}
562static inline int
563bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t s, bus_size_t a, bus_size_t b,
564 bus_dma_segment_t *sg, int n, int *r, int f)
565{
566 const bus_dma_tag_t t0 = t;
567 int ret;
568 _BD_PRECALL(t, _dmamem_alloc);
569 ret = _BD_CALL(t, _dmamem_alloc)(t, t0, s, a, b, sg, n, r, f);
570 _BD_POSTCALL;
571 return (ret);
572}
573static inline void
574bus_dmamem_free(bus_dma_tag_t t, bus_dma_segment_t *sg, int n)
575{
576 const bus_dma_tag_t t0 = t;
577 _BD_PRECALL(t, _dmamem_free);
578 _BD_CALL(t, _dmamem_free)(t, t0, sg, n);
579 _BD_POSTCALL;
580}
581static inline int
582bus_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *sg, int n, size_t s,
583 caddr_t *k, int f)
584{
585 const bus_dma_tag_t t0 = t;
586 int r;
587 _BD_PRECALL(t, _dmamem_map);
588 r = _BD_CALL(t, _dmamem_map)(t, t0, sg, n, s, k, f);
589 _BD_POSTCALL;
590 return (r);
591}
592static inline void
593bus_dmamem_unmap(bus_dma_tag_t t, caddr_t k, size_t s)
594{
595 const bus_dma_tag_t t0 = t;
596 _BD_PRECALL(t, _dmamem_unmap);
597 _BD_CALL(t, _dmamem_unmap)(t, t0, k, s);
598 _BD_POSTCALL;
599}
600static inline paddr_t
601bus_dmamem_mmap(bus_dma_tag_t t, bus_dma_segment_t *sg, int n, off_t o, int p,
602 int f)
603{
604 const bus_dma_tag_t t0 = t;
605 int r;
606 _BD_PRECALL(t, _dmamem_mmap);
607 r = _BD_CALL(t, _dmamem_mmap)(t, t0, sg, n, o, p, f);
608 _BD_POSTCALL;
609 return (r);
610}
611
612/*
613 * bus_dmamap_t
614 *
615 * Describes a DMA mapping.
616 */
617struct sparc_bus_dmamap {
618 /*
619 * PRIVATE MEMBERS: not for use by machine-independent code.
620 */
621 bus_addr_t _dm_dvmastart; /* start and size of allocated */
622 bus_size_t _dm_dvmasize; /* DVMA segment for this map */
623
624 bus_size_t _dm_size; /* largest DMA transfer mappable */
625 bus_size_t _dm_maxsegsz; /* largest possible segment */
626 bus_size_t _dm_boundary; /* don't cross this */
627 int _dm_segcnt; /* number of segs this map can map */
628 int _dm_flags; /* misc. flags */
629#define _DM_TYPE_LOAD 0
630#define _DM_TYPE_SEGS 1
631#define _DM_TYPE_UIO 2
632#define _DM_TYPE_MBUF 3
633 int _dm_type; /* mapping type: raw, uio, mbuf, etc */
634 void *_dm_source; /* source mbuf/uio/etc. for unload */
635
636 void *_dm_cookie; /* cookie for bus-specific functions */
637
638 /*
639 * PUBLIC MEMBERS: these are used by machine-independent code.
640 */
641 bus_size_t dm_mapsize; /* size of the mapping */
642 int dm_nsegs; /* # valid segments in mapping */
643
644 bus_dma_segment_t dm_segs[1]; /* segments; variable length */
645};
646
647#endif /* _KERNEL */
648
649#endif /* _MACHINE_BUS_H_ */