| 1 | /* $OpenBSD: fsr.h,v 1.2 2003/06/02 23:27:56 millert Exp $ */ |
| 2 | /* $NetBSD: fsr.h,v 1.1.1.1 1998/06/20 04:58:51 eeh Exp $ */ |
| 3 | |
| 4 | /* |
| 5 | * Copyright (c) 1992, 1993 |
| 6 | * The Regents of the University of California. All rights reserved. |
| 7 | * |
| 8 | * This software was developed by the Computer Systems Engineering group |
| 9 | * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and |
| 10 | * contributed to Berkeley. |
| 11 | * |
| 12 | * All advertising materials mentioning features or use of this software |
| 13 | * must display the following acknowledgement: |
| 14 | * This product includes software developed by the University of |
| 15 | * California, Lawrence Berkeley Laboratory. |
| 16 | * |
| 17 | * Redistribution and use in source and binary forms, with or without |
| 18 | * modification, are permitted provided that the following conditions |
| 19 | * are met: |
| 20 | * 1. Redistributions of source code must retain the above copyright |
| 21 | * notice, this list of conditions and the following disclaimer. |
| 22 | * 2. Redistributions in binary form must reproduce the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer in the |
| 24 | * documentation and/or other materials provided with the distribution. |
| 25 | * 3. Neither the name of the University nor the names of its contributors |
| 26 | * may be used to endorse or promote products derived from this software |
| 27 | * without specific prior written permission. |
| 28 | * |
| 29 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
| 30 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 31 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 32 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
| 33 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 34 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 35 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 36 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 37 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 38 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 39 | * SUCH DAMAGE. |
| 40 | * |
| 41 | * @(#)fsr.h 8.1 (Berkeley) 6/11/93 |
| 42 | */ |
| 43 | |
| 44 | #ifndef _MACHINE_FSR_H_ |
| 45 | #define _MACHINE_FSR_H_ |
| 46 | |
| 47 | /* |
| 48 | * Bits in FPRS |
| 49 | */ |
| 50 | #define FPRS_FEF 0x04 /* Enable FP -- must be set to enable FP regs */ |
| 51 | #define FPRS_DU 0x02 /* Dirty upper -- upper fp regs are dirty */ |
| 52 | #define FPRS_DL 0x01 /* Dirty lower -- lower fp regs are dirty */ |
| 53 | |
| 54 | /* |
| 55 | * Bits in FSR. |
| 56 | */ |
| 57 | |
| 58 | #define FSR_RD 0xc0000000 /* rounding direction */ |
| 59 | #define FSR_RD_RN 0 /* round to nearest */ |
| 60 | #define FSR_RD_RZ 1 /* round towards 0 */ |
| 61 | #define FSR_RD_RP 2 /* round towards +inf */ |
| 62 | #define FSR_RD_RM 3 /* round towards -inf */ |
| 63 | #define FSR_RD_SHIFT 30 |
| 64 | #define FSR_RD_MASK 0x03 |
| 65 | |
| 66 | #define FSR_RP 0x30000000 /* extended rounding precision */ |
| 67 | #define FSR_RP_X 0 /* extended stays extended */ |
| 68 | #define FSR_RP_S 1 /* extended => single */ |
| 69 | #define FSR_RP_D 2 /* extended => double */ |
| 70 | #define FSR_RP_80 3 /* extended => 80-bit */ |
| 71 | #define FSR_RP_SHIFT 28 |
| 72 | #define FSR_RP_MASK 0x03 |
| 73 | |
| 74 | #define FSR_TEM 0x0f800000 /* trap enable mask */ |
| 75 | #define FSR_TEM_SHIFT 23 |
| 76 | #define FSR_TEM_MASK 0x1f |
| 77 | |
| 78 | #define FSR_NS 0x00400000 /* ``nonstandard mode'' */ |
| 79 | #define FSR_AU 0x00400000 /* aka abrupt underflow mode */ |
| 80 | #define FSR_MBZ 0x00300000 /* reserved; must be zero */ |
| 81 | |
| 82 | #define FSR_VER 0x000e0000 /* version bits */ |
| 83 | #define FSR_VER_SHIFT 17 |
| 84 | #define FSR_VER_MASK 0x07 |
| 85 | |
| 86 | #define FSR_FTT 0x0001c000 /* FP trap type */ |
| 87 | #define FSR_TT_NONE 0 /* no trap */ |
| 88 | #define FSR_TT_IEEE 1 /* IEEE exception */ |
| 89 | #define FSR_TT_UNFIN 2 /* unfinished operation */ |
| 90 | #define FSR_TT_UNIMP 3 /* unimplemented operation */ |
| 91 | #define FSR_TT_SEQ 4 /* sequence error */ |
| 92 | #define FSR_TT_HWERR 5 /* hardware error (unrecoverable) */ |
| 93 | #define FSR_FTT_SHIFT 14 |
| 94 | #define FSR_FTT_MASK 0x03 |
| 95 | |
| 96 | #define FSR_QNE 0x00002000 /* queue not empty */ |
| 97 | #define FSR_PR 0x00001000 /* partial result */ |
| 98 | |
| 99 | #define FSR_FCC 0x00000c00 /* FP condition codes */ |
| 100 | #define FSR_CC_EQ 0 /* f1 = f2 */ |
| 101 | #define FSR_CC_LT 1 /* f1 < f2 */ |
| 102 | #define FSR_CC_GT 2 /* f1 > f2 */ |
| 103 | #define FSR_CC_UO 3 /* (f1,f2) unordered */ |
| 104 | #define FSR_FCC_SHIFT 10 |
| 105 | #define FSR_FCC_MASK 0x03 |
| 106 | |
| 107 | #define FSR_AX 0x000003e0 /* accrued exceptions */ |
| 108 | #define FSR_AX_SHIFT 5 |
| 109 | #define FSR_AX_MASK 0x1f |
| 110 | #define FSR_CX 0x0000001f /* current exceptions */ |
| 111 | #define FSR_CX_SHIFT 0 |
| 112 | #define FSR_CX_MASK 0x1f |
| 113 | |
| 114 | /* These are the 3 new v9 fcc's */ |
| 115 | #define FSR_FCC3 0x06000000000 /* FP condition codes */ |
| 116 | #define FSR_FCC3_SHIFT 36 |
| 117 | |
| 118 | #define FSR_FCC2 0x0c00000000 /* FP condition codes */ |
| 119 | #define FSR_FCC2_SHIFT 34 |
| 120 | |
| 121 | #define FSR_FCC1 0x0600000000 /* FP condition codes */ |
| 122 | #define FSR_FCC1_SHIFT 32 |
| 123 | |
| 124 | |
| 125 | /* The following exceptions apply to TEM, AX, and CX. */ |
| 126 | #define FSR_NV 0x10 /* invalid operand */ |
| 127 | #define FSR_OF 0x08 /* overflow */ |
| 128 | #define FSR_UF 0x04 /* underflow */ |
| 129 | #define FSR_DZ 0x02 /* division by zero */ |
| 130 | #define FSR_NX 0x01 /* inexact result */ |
| 131 | |
| 132 | #endif /* _MACHINE_FSR_H_ */ |