1/* $OpenBSD: pte.h,v 1.17 2024/04/14 19:08:09 miod Exp $ */
2/* $NetBSD: pte.h,v 1.7 2001/07/31 06:55:46 eeh Exp $ */
3
4/*
5 * Copyright (c) 1996-1999 Eduardo Horvath
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 */
26
27#ifndef _MACHINE_PTE_H_
28#define _MACHINE_PTE_H_
29
30/* virtual address to virtual page number */
31#define VA_SUN4U_VPG(va) (((int)(va) >> 13) & 31)
32
33/* virtual address to offset within page */
34#define VA_SUN4U_OFF(va) (((int)(va)) & 0x1FFF)
35
36/* When we go to 64-bit VAs we need to handle the hole */
37#define VA_VPG(va) VA_SUN4U_VPG(va)
38#define VA_OFF(va) VA_SUN4U_OFF(va)
39
40#define PG_SHIFT4U 13
41#define MMU_PAGE_ALIGN 8192
42
43/* If you know where a tte is in the tsb, how do you find its va? */
44#define TSBVA(i) ((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000))
45
46#ifndef _LOCORE
47/*
48 * This is the spitfire TTE.
49 */
50#if 0 /* We don't use bitfields anyway. */
51struct sun4u_tag_fields {
52 u_int64_t tag_g:1, /* global flag */
53 tag_ctxt:15, /* context for mapping */
54 tag_unassigned:6,
55 tag_va:42; /* virtual address bits<64:22> */
56};
57union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; };
58struct sun4u_data_fields {
59 u_int64_t data_v:1, /* valid bit */
60 data_size:2, /* page size [8K*8**<SIZE>] */
61 data_nfo:1, /* no-fault only */
62 data_ie:1, /* invert endianness [inefficient] */
63 data_soft2:2, /* reserved for S/W */
64 data_pa:36, /* physical address */
65 data_accessed:1,/* S/W accessed bit */
66 data_modified:1,/* S/W modified bit */
67 data_realw:1, /* S/W real writable bit (to manage modified) */
68 data_tsblock:1, /* S/W TSB locked entry */
69 data_exec:1, /* S/W Executable */
70 data_onlyexec:1,/* S/W Executable only */
71 data_lock:1, /* lock into TLB */
72 data_cacheable:2, /* cacheability control */
73 data_e:1, /* explicit accesses only */
74 data_priv:1, /* privileged page */
75 data_w:1, /* writeable */
76 data_g:1; /* same as tag_g */
77};
78union sun4u_data { struct sun4u_data_fields f; int64_t data; };
79struct sun4u_tte {
80 union sun4u_tag tag;
81 union sun4u_data data;
82};
83#else
84struct sun4u_tte {
85 int64_t tag;
86 int64_t data;
87};
88#endif
89typedef struct sun4u_tte pte_t;
90
91/* Assembly routine to flush a mapping */
92extern void (*sp_tlb_flush_pte)(vaddr_t, uint64_t);
93extern void (*sp_tlb_flush_ctx)(uint64_t);
94
95#if defined(MULTIPROCESSOR)
96void smp_tlb_flush_pte(vaddr_t, uint64_t);
97void smp_tlb_flush_ctx(uint64_t);
98#define tlb_flush_pte(va,ctx) smp_tlb_flush_pte(va, ctx)
99#define tlb_flush_ctx(ctx) smp_tlb_flush_ctx(ctx)
100#else
101#define tlb_flush_pte(va,ctx) (*sp_tlb_flush_pte)(va, ctx)
102#define tlb_flush_ctx(ctx) (*sp_tlb_flush_ctx)(ctx)
103#endif
104
105#endif /* _LOCORE */
106
107/* TSB tag masks */
108#define CTX_MASK ((1<<13)-1)
109#define TSB_TAG_CTX_SHIFT 48
110#define TSB_TAG_VA_SHIFT 22
111
112#define TSB_TAG_LOCKED 0x0000040000000000LL
113
114#define TSB_TAG_G 0x8000000000000000LL
115#define TSB_TAG_CTX(t) ((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK)
116#define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT))
117#define TSB_TAG(g,ctx,va) ((((u_int64_t)((g)!=0))<<63)|(((u_int64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((u_int64_t)va)>>TSB_TAG_VA_SHIFT))
118
119/* Page sizes */
120#define PGSZ_8K 0
121#define PGSZ_64K 1
122#define PGSZ_512K 2
123#define PGSZ_4M 3
124
125#define SUN4U_PGSZ_SHIFT 61
126#define SUN4U_TLB_SZ(s) (((uint64_t)(s)) << SUN4U_PGSZ_SHIFT)
127
128/* TLB data masks */
129#define SUN4U_TLB_V 0x8000000000000000LL
130#define SUN4U_TLB_8K SUN4U_TLB_SZ(PGSZ_8K)
131#define SUN4U_TLB_64K SUN4U_TLB_SZ(PGSZ_64K)
132#define SUN4U_TLB_512K SUN4U_TLB_SZ(PGSZ_512K)
133#define SUN4U_TLB_4M SUN4U_TLB_SZ(PGSZ_4M)
134#define SUN4U_TLB_SZ_MASK 0x6000000000000000LL
135#define SUN4U_TLB_NFO 0x1000000000000000LL
136#define SUN4U_TLB_IE 0x0800000000000000LL
137#define SUN4U_TLB_SOFT2_MASK 0x07fc000000000000LL
138#define SUN4U_TLB_RESERVED_MASK 0x0003800000000000LL
139#define SUN4U_TLB_PA_MASK 0x00007fffffffe000LL
140#define SUN4U_TLB_SOFT_MASK 0x0000000000001f80LL
141/* S/W bits */
142#define SUN4U_TLB_ACCESS 0x0000000000000200LL
143#define SUN4U_TLB_MODIFY 0x0000000000000800LL
144#define SUN4U_TLB_REAL_W 0x0000000000000400LL
145#define SUN4U_TLB_TSB_LOCK 0x0000000000001000LL
146#define SUN4U_TLB_EXEC 0x0000000000000100LL
147#define SUN4U_TLB_EXEC_ONLY 0x0000000000000080LL
148/* H/W bits */
149#define SUN4U_TLB_L 0x0000000000000040LL
150#define SUN4U_TLB_CACHE_MASK 0x0000000000000030LL
151#define SUN4U_TLB_CP 0x0000000000000020LL
152#define SUN4U_TLB_CV 0x0000000000000010LL
153#define SUN4U_TLB_E 0x0000000000000008LL
154#define SUN4U_TLB_P 0x0000000000000004LL
155#define SUN4U_TLB_W 0x0000000000000002LL
156#define SUN4U_TLB_G 0x0000000000000001LL
157
158#define SUN4U_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
159(((valid)?SUN4U_TLB_V:0LL)|SUN4U_TLB_SZ(sz)|\
160(((u_int64_t)(pa))&SUN4U_TLB_PA_MASK)|\
161((cache)?((aliased)?SUN4U_TLB_CP:SUN4U_TLB_CACHE_MASK):SUN4U_TLB_E)|\
162((priv)?SUN4U_TLB_P:0LL)|((write)?SUN4U_TLB_W:0LL)|((g)?SUN4U_TLB_G:0LL)|\
163((ie)?SUN4U_TLB_IE:0LL))
164
165#define SUN4V_PGSZ_SHIFT 0
166#define SUN4V_TLB_SZ(s) (((uint64_t)(s))<<SUN4V_PGSZ_SHIFT)
167
168/* TLB data masks */
169#define SUN4V_TLB_V 0x8000000000000000LL
170#define SUN4V_TLB_8K SUN4V_TLB_SZ(PGSZ_8K)
171#define SUN4V_TLB_64K SUN4V_TLB_SZ(PGSZ_64K)
172#define SUN4V_TLB_512K SUN4V_TLB_SZ(PGSZ_512K)
173#define SUN4V_TLB_4M SUN4V_TLB_SZ(PGSZ_4M)
174#define SUN4V_TLB_SZ_MASK 0x000000000000000fLL
175#define SUN4V_TLB_NFO 0x4000000000000000LL
176#define SUN4V_TLB_IE 0x0000000000001000LL
177#define SUN4V_TLB_SOFT2_MASK 0x3f00000000000000LL
178#define SUN4V_TLB_PA_MASK 0x00ffffffffffe000LL
179#define SUN4V_TLB_SOFT_MASK 0x0000000000000030LL
180/* S/W bits */
181#define SUN4V_TLB_ACCESS 0x0000000000000010LL
182#define SUN4V_TLB_MODIFY 0x0000000000000020LL
183#define SUN4V_TLB_REAL_W 0x2000000000000000LL
184#define SUN4V_TLB_TSB_LOCK 0x1000000000000000LL
185#define SUN4V_TLB_EXEC SUN4V_TLB_X
186#define SUN4V_TLB_EXEC_ONLY 0x0200000000000000LL
187/* H/W bits */
188#define SUN4V_TLB_CACHE_MASK 0x0000000000000600LL
189#define SUN4V_TLB_CP 0x0000000000000400LL
190#define SUN4V_TLB_CV 0x0000000000000200LL
191#define SUN4V_TLB_E 0x0000000000000800LL
192#define SUN4V_TLB_P 0x0000000000000100LL
193#define SUN4V_TLB_X 0x0000000000000080LL
194#define SUN4V_TLB_W 0x0000000000000040LL
195#define SUN4V_TLB_G 0x0000000000000000LL
196
197#define SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
198(((valid)?SUN4V_TLB_V:0LL)|SUN4V_TLB_SZ(sz)|\
199(((u_int64_t)(pa))&SUN4V_TLB_PA_MASK)|\
200((cache)?((aliased)?SUN4V_TLB_CP:SUN4V_TLB_CACHE_MASK):SUN4V_TLB_E)|\
201((priv)?SUN4V_TLB_P:0LL)|((write)?SUN4V_TLB_W:0LL)|((g)?SUN4V_TLB_G:0LL)|\
202((ie)?SUN4V_TLB_IE:0LL))
203
204#endif /* _MACHINE_PTE_H_ */