1/* $NetBSD: pte.h,v 1.17 2022/08/21 09:12:43 riastradh Exp $ */
2
3/*
4 * Copyright (c) 2001 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Frank van der Linden for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef _AMD64_PTE_H_
39#define _AMD64_PTE_H_
40
41#ifdef __x86_64__
42
43/*
44 * amd64 MMU hardware structure:
45 *
46 * the (first generation) amd64 MMU is a 4-level MMU which maps 2^48 bytes
47 * of virtual memory. The pagesize we use is 4K (4096 [0x1000] bytes),
48 * although 2M and 4M can be used as well. The indexes in the levels
49 * are 9 bits wide (512 64bit entries per level), dividing the bits
50 * 9-9-9-9-12.
51 *
52 * The top level table, called PML4, contains 512 64bit entries pointing
53 * to 3rd level table. The 3rd level table is called the 'page directory
54 * pointers directory' and has 512 entries pointing to page directories.
55 * The 2nd level is the page directory, containing 512 pointers to
56 * page table pages. Lastly, level 1 consists of pages containing 512
57 * PTEs.
58 *
59 * Simply put, levels 4-1 all consist of pages containing 512
60 * entries pointing to the next level. Level 0 is the actual PTEs
61 * themselves.
62 *
63 * For a description on the other bits, which are i386 compatible,
64 * see the i386 pte.h
65 */
66
67#if !defined(_LOCORE)
68/*
69 * Here we define the data types for PDEs and PTEs.
70 */
71#include <sys/stdint.h>
72typedef uint64_t pd_entry_t; /* PDE */
73typedef uint64_t pt_entry_t; /* PTE */
74#endif
75
76/*
77 * Mask to get rid of the sign-extended part of addresses.
78 */
79#define VA_SIGN_MASK 0xffff000000000000
80#define VA_SIGN_NEG(va) ((va) | VA_SIGN_MASK)
81/* XXXfvdl this one's not right. */
82#define VA_SIGN_POS(va) ((va) & ~VA_SIGN_MASK)
83
84/*
85 * Now we define various constants for playing with virtual addresses.
86 */
87#define L1_SHIFT 12
88#define L2_SHIFT 21
89#define L3_SHIFT 30
90#define L4_SHIFT 39
91#define NBPD_L1 (1UL << L1_SHIFT) /* # bytes mapped by L1 ent (4K) */
92#define NBPD_L2 (1UL << L2_SHIFT) /* # bytes mapped by L2 ent (2MB) */
93#define NBPD_L3 (1UL << L3_SHIFT) /* # bytes mapped by L3 ent (1G) */
94#define NBPD_L4 (1UL << L4_SHIFT) /* # bytes mapped by L4 ent (512G) */
95
96#define L4_MASK 0x0000ff8000000000
97#define L3_MASK 0x0000007fc0000000
98#define L2_MASK 0x000000003fe00000
99#define L1_MASK 0x00000000001ff000
100
101#define L4_FRAME L4_MASK
102#define L3_FRAME (L4_FRAME|L3_MASK)
103#define L2_FRAME (L3_FRAME|L2_MASK)
104#define L1_FRAME (L2_FRAME|L1_MASK)
105
106/*
107 * x86 PTE/PDE bits.
108 */
109#define PTE_P 0x0000000000000001 /* Present */
110#define PTE_W 0x0000000000000002 /* Write */
111#define PTE_U 0x0000000000000004 /* User */
112#define PTE_PWT 0x0000000000000008 /* Write-Through */
113#define PTE_PCD 0x0000000000000010 /* Cache-Disable */
114#define PTE_A 0x0000000000000020 /* Accessed */
115#define PTE_D 0x0000000000000040 /* Dirty */
116#define PTE_PAT 0x0000000000000080 /* PAT on 4KB Pages */
117#define PTE_PS 0x0000000000000080 /* Large Page Size */
118#define PTE_G 0x0000000000000100 /* Global Translation */
119#define PTE_AVL1 0x0000000000000200 /* Ignored by Hardware */
120#define PTE_AVL2 0x0000000000000400 /* Ignored by Hardware */
121#define PTE_AVL3 0x0000000000000800 /* Ignored by Hardware */
122#define PTE_LGPAT 0x0000000000001000 /* PAT on Large Pages */
123#define PTE_NX 0x8000000000000000 /* No Execute */
124
125#define PTE_4KFRAME 0x000ffffffffff000
126#define PTE_2MFRAME 0x000fffffffe00000
127#define PTE_1GFRAME 0x000fffffc0000000
128
129#define PTE_FRAME PTE_4KFRAME
130#define PTE_LGFRAME PTE_2MFRAME
131
132#define _MACHINE_PTE_H_X86
133#include <x86/pte.h>
134#undef _MACHINE_PTE_H_X86
135
136#else /* !__x86_64__ */
137
138#include <i386/pte.h>
139
140#endif /* !__x86_64__ */
141
142#endif /* _AMD64_PTE_H_ */