1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 a320,
9 addr_lsl_slow_14,
10 aes,
11 aggressive_fma,
12 aggressive_interleaving,
13 alternate_sextload_cvt_f32_pattern,
14 altnzcv,
15 alu_lsl_fast,
16 am,
17 amvs,
18 arith_bcc_fusion,
19 arith_cbz_fusion,
20 ascend_store_address,
21 avoid_ldapur,
22 balance_fp_ops,
23 bf16,
24 brbe,
25 bti,
26 btie,
27 call_saved_x10,
28 call_saved_x11,
29 call_saved_x12,
30 call_saved_x13,
31 call_saved_x14,
32 call_saved_x15,
33 call_saved_x18,
34 call_saved_x8,
35 call_saved_x9,
36 ccdp,
37 ccidx,
38 ccpp,
39 chk,
40 clrbhb,
41 cmh,
42 cmp_bcc_fusion,
43 cmpbr,
44 complxnum,
45 contextidr_el2,
46 cpa,
47 crc,
48 crypto,
49 cssc,
50 d128,
51 disable_fast_inc_vl,
52 disable_latency_sched_heuristic,
53 disable_ldp,
54 disable_maximize_scalable_bandwidth,
55 disable_stp,
56 disable_unpredicated_ld_st_lower,
57 dit,
58 dotprod,
59 ecv,
60 el2vmsa,
61 el3,
62 enable_select_opt,
63 ete,
64 execute_only,
65 exynos_cheap_as_move,
66 f16f32dot,
67 f16f32mm,
68 f16mm,
69 f32mm,
70 f64mm,
71 f8f16mm,
72 f8f32mm,
73 faminmax,
74 fgt,
75 fix_cortex_a53_835769,
76 flagm,
77 fmv,
78 force_32bit_jump_tables,
79 fp16fml,
80 fp8,
81 fp8dot2,
82 fp8dot4,
83 fp8fma,
84 fp_armv8,
85 fpac,
86 fprcvt,
87 fptoint,
88 fujitsu_monaka,
89 fullfp16,
90 fuse_address,
91 fuse_addsub_2reg_const1,
92 fuse_adrp_add,
93 fuse_aes,
94 fuse_arith_logic,
95 fuse_crypto_eor,
96 fuse_csel,
97 fuse_cset,
98 fuse_literals,
99 gcie,
100 gcs,
101 harden_sls_blr,
102 harden_sls_nocomdat,
103 harden_sls_retbr,
104 hbc,
105 hcx,
106 i8mm,
107 ite,
108 jsconv,
109 ldp_aligned_only,
110 lor,
111 ls64,
112 lscp,
113 lse,
114 lse128,
115 lse2,
116 lsfe,
117 lsui,
118 lut,
119 max_interleave_factor_4,
120 mec,
121 mops,
122 mops_go,
123 mpam,
124 mpamv2,
125 mte,
126 mtetc,
127 neon,
128 nmi,
129 no_bti_at_return_twice,
130 no_neg_immediates,
131 no_sve_fp_ld1r,
132 no_zcz_fpr64,
133 nv,
134 occmo,
135 olympus,
136 outline_atomics,
137 pan,
138 pan_rwv,
139 pauth,
140 pauth_lr,
141 pcdphint,
142 perfmon,
143 poe2,
144 pops,
145 predictable_select_expensive,
146 predres,
147 prfm_slc_target,
148 rand,
149 ras,
150 rasv2,
151 rcpc,
152 rcpc3,
153 rcpc_immo,
154 rdm,
155 reserve_lr_for_ra,
156 reserve_x1,
157 reserve_x10,
158 reserve_x11,
159 reserve_x12,
160 reserve_x13,
161 reserve_x14,
162 reserve_x15,
163 reserve_x18,
164 reserve_x2,
165 reserve_x20,
166 reserve_x21,
167 reserve_x22,
168 reserve_x23,
169 reserve_x24,
170 reserve_x25,
171 reserve_x26,
172 reserve_x27,
173 reserve_x28,
174 reserve_x3,
175 reserve_x4,
176 reserve_x5,
177 reserve_x6,
178 reserve_x7,
179 reserve_x9,
180 rme,
181 sb,
182 sel2,
183 sha2,
184 sha3,
185 slow_misaligned_128store,
186 slow_paired_128,
187 slow_strqro_store,
188 sm4,
189 sme,
190 sme2,
191 sme2p1,
192 sme2p2,
193 sme2p3,
194 sme_b16b16,
195 sme_f16f16,
196 sme_f64f64,
197 sme_f8f16,
198 sme_f8f32,
199 sme_fa64,
200 sme_i16i64,
201 sme_lutv2,
202 sme_mop4,
203 sme_tmop,
204 spe,
205 spe_eef,
206 specres2,
207 specrestrict,
208 ssbs,
209 ssve_aes,
210 ssve_bitperm,
211 ssve_fexpa,
212 ssve_fp8dot2,
213 ssve_fp8dot4,
214 ssve_fp8fma,
215 store_pair_suppress,
216 stp_aligned_only,
217 strict_align,
218 sve,
219 sve2,
220 sve2_aes,
221 sve2_bitperm,
222 sve2_sha3,
223 sve2_sm4,
224 sve2p1,
225 sve2p2,
226 sve2p3,
227 sve_aes,
228 sve_aes2,
229 sve_b16b16,
230 sve_b16mm,
231 sve_bfscale,
232 sve_bitperm,
233 sve_f16f32mm,
234 sve_sha3,
235 sve_sm4,
236 tagged_globals,
237 tev,
238 the,
239 tlb_rmi,
240 tlbid,
241 tlbiw,
242 tpidr_el1,
243 tpidr_el2,
244 tpidr_el3,
245 tpidrro_el0,
246 tracev8_4,
247 trbe,
248 uaops,
249 use_experimental_zeroing_pseudos,
250 use_fixed_over_scalable_if_equal_cost,
251 use_postra_scheduler,
252 use_reciprocal_square_root,
253 use_wzr_to_vec_move,
254 v8_1a,
255 v8_2a,
256 v8_3a,
257 v8_4a,
258 v8_5a,
259 v8_6a,
260 v8_7a,
261 v8_8a,
262 v8_9a,
263 v8a,
264 v8r,
265 v9_1a,
266 v9_2a,
267 v9_3a,
268 v9_4a,
269 v9_5a,
270 v9_6a,
271 v9_7a,
272 v9a,
273 vh,
274 wfxt,
275 xs,
276 zcm_fpr128,
277 zcm_fpr32,
278 zcm_fpr64,
279 zcm_gpr32,
280 zcm_gpr64,
281 zcz_fp_workaround,
282 zcz_fpr128,
283 zcz_gpr32,
284 zcz_gpr64,
285};
286
287pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
288pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
289pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
290pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
291
292pub const all_features = blk: {
293 @setEvalBranchQuota(2000);
294 const len = @typeInfo(Feature).@"enum".field_names.len;
295 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
296 var result: [len]CpuFeature = undefined;
297 result[@backingInt(Feature.a320)] = .{
298 .llvm_name = "a320",
299 .description = "Cortex-A320 ARM processors",
300 .dependencies = featureSet(&[_]Feature{
301 .aggressive_interleaving,
302 .fuse_adrp_add,
303 .fuse_aes,
304 .use_fixed_over_scalable_if_equal_cost,
305 .use_postra_scheduler,
306 .use_wzr_to_vec_move,
307 }),
308 };
309 result[@backingInt(Feature.addr_lsl_slow_14)] = .{
310 .llvm_name = "addr-lsl-slow-14",
311 .description = "Address operands with shift amount of 1 or 4 are slow",
312 .dependencies = featureSet(&[_]Feature{}),
313 };
314 result[@backingInt(Feature.aes)] = .{
315 .llvm_name = "aes",
316 .description = "Enable AES support",
317 .dependencies = featureSet(&[_]Feature{
318 .neon,
319 }),
320 };
321 result[@backingInt(Feature.aggressive_fma)] = .{
322 .llvm_name = "aggressive-fma",
323 .description = "Enable Aggressive FMA for floating-point.",
324 .dependencies = featureSet(&[_]Feature{}),
325 };
326 result[@backingInt(Feature.aggressive_interleaving)] = .{
327 .llvm_name = "aggressive-interleaving",
328 .description = "Make use of aggressive interleaving during vectorization",
329 .dependencies = featureSet(&[_]Feature{}),
330 };
331 result[@backingInt(Feature.alternate_sextload_cvt_f32_pattern)] = .{
332 .llvm_name = "alternate-sextload-cvt-f32-pattern",
333 .description = "Use alternative pattern for sextload convert to f32",
334 .dependencies = featureSet(&[_]Feature{}),
335 };
336 result[@backingInt(Feature.altnzcv)] = .{
337 .llvm_name = "altnzcv",
338 .description = "Enable alternative NZCV format for floating point comparisons",
339 .dependencies = featureSet(&[_]Feature{
340 .flagm,
341 }),
342 };
343 result[@backingInt(Feature.alu_lsl_fast)] = .{
344 .llvm_name = "alu-lsl-fast",
345 .description = "Add/Sub operations with lsl shift <= 4 are cheap",
346 .dependencies = featureSet(&[_]Feature{}),
347 };
348 result[@backingInt(Feature.am)] = .{
349 .llvm_name = "am",
350 .description = "Enable Armv8.4-A Activity Monitors extension",
351 .dependencies = featureSet(&[_]Feature{}),
352 };
353 result[@backingInt(Feature.amvs)] = .{
354 .llvm_name = "amvs",
355 .description = "Enable Armv8.6-A Activity Monitors Virtualization support",
356 .dependencies = featureSet(&[_]Feature{
357 .am,
358 }),
359 };
360 result[@backingInt(Feature.arith_bcc_fusion)] = .{
361 .llvm_name = "arith-bcc-fusion",
362 .description = "CPU fuses arithmetic+bcc operations",
363 .dependencies = featureSet(&[_]Feature{}),
364 };
365 result[@backingInt(Feature.arith_cbz_fusion)] = .{
366 .llvm_name = "arith-cbz-fusion",
367 .description = "CPU fuses arithmetic + cbz/cbnz operations",
368 .dependencies = featureSet(&[_]Feature{}),
369 };
370 result[@backingInt(Feature.ascend_store_address)] = .{
371 .llvm_name = "ascend-store-address",
372 .description = "Schedule vector stores by ascending address",
373 .dependencies = featureSet(&[_]Feature{}),
374 };
375 result[@backingInt(Feature.avoid_ldapur)] = .{
376 .llvm_name = "avoid-ldapur",
377 .description = "Prefer add+ldapr to offset ldapur",
378 .dependencies = featureSet(&[_]Feature{}),
379 };
380 result[@backingInt(Feature.balance_fp_ops)] = .{
381 .llvm_name = "balance-fp-ops",
382 .description = "balance mix of odd and even D-registers for fp multiply(-accumulate) ops",
383 .dependencies = featureSet(&[_]Feature{}),
384 };
385 result[@backingInt(Feature.bf16)] = .{
386 .llvm_name = "bf16",
387 .description = "Enable BFloat16 Extension",
388 .dependencies = featureSet(&[_]Feature{
389 .neon,
390 }),
391 };
392 result[@backingInt(Feature.brbe)] = .{
393 .llvm_name = "brbe",
394 .description = "Enable Branch Record Buffer Extension",
395 .dependencies = featureSet(&[_]Feature{}),
396 };
397 result[@backingInt(Feature.bti)] = .{
398 .llvm_name = "bti",
399 .description = "Enable Branch Target Identification",
400 .dependencies = featureSet(&[_]Feature{}),
401 };
402 result[@backingInt(Feature.btie)] = .{
403 .llvm_name = "btie",
404 .description = "Enable Enhanced Branch Target Identification extension",
405 .dependencies = featureSet(&[_]Feature{}),
406 };
407 result[@backingInt(Feature.call_saved_x10)] = .{
408 .llvm_name = "call-saved-x10",
409 .description = "Make X10 callee saved.",
410 .dependencies = featureSet(&[_]Feature{}),
411 };
412 result[@backingInt(Feature.call_saved_x11)] = .{
413 .llvm_name = "call-saved-x11",
414 .description = "Make X11 callee saved.",
415 .dependencies = featureSet(&[_]Feature{}),
416 };
417 result[@backingInt(Feature.call_saved_x12)] = .{
418 .llvm_name = "call-saved-x12",
419 .description = "Make X12 callee saved.",
420 .dependencies = featureSet(&[_]Feature{}),
421 };
422 result[@backingInt(Feature.call_saved_x13)] = .{
423 .llvm_name = "call-saved-x13",
424 .description = "Make X13 callee saved.",
425 .dependencies = featureSet(&[_]Feature{}),
426 };
427 result[@backingInt(Feature.call_saved_x14)] = .{
428 .llvm_name = "call-saved-x14",
429 .description = "Make X14 callee saved.",
430 .dependencies = featureSet(&[_]Feature{}),
431 };
432 result[@backingInt(Feature.call_saved_x15)] = .{
433 .llvm_name = "call-saved-x15",
434 .description = "Make X15 callee saved.",
435 .dependencies = featureSet(&[_]Feature{}),
436 };
437 result[@backingInt(Feature.call_saved_x18)] = .{
438 .llvm_name = "call-saved-x18",
439 .description = "Make X18 callee saved.",
440 .dependencies = featureSet(&[_]Feature{}),
441 };
442 result[@backingInt(Feature.call_saved_x8)] = .{
443 .llvm_name = "call-saved-x8",
444 .description = "Make X8 callee saved.",
445 .dependencies = featureSet(&[_]Feature{}),
446 };
447 result[@backingInt(Feature.call_saved_x9)] = .{
448 .llvm_name = "call-saved-x9",
449 .description = "Make X9 callee saved.",
450 .dependencies = featureSet(&[_]Feature{}),
451 };
452 result[@backingInt(Feature.ccdp)] = .{
453 .llvm_name = "ccdp",
454 .description = "Enable Armv8.5-A Cache Clean to Point of Deep Persistence",
455 .dependencies = featureSet(&[_]Feature{
456 .ccpp,
457 }),
458 };
459 result[@backingInt(Feature.ccidx)] = .{
460 .llvm_name = "ccidx",
461 .description = "Enable Armv8.3-A Extend of the CCSIDR number of sets",
462 .dependencies = featureSet(&[_]Feature{}),
463 };
464 result[@backingInt(Feature.ccpp)] = .{
465 .llvm_name = "ccpp",
466 .description = "Enable Armv8.2-A data Cache Clean to Point of Persistence",
467 .dependencies = featureSet(&[_]Feature{}),
468 };
469 result[@backingInt(Feature.chk)] = .{
470 .llvm_name = "chk",
471 .description = "Enable Armv8.0-A Check Feature Status Extension",
472 .dependencies = featureSet(&[_]Feature{}),
473 };
474 result[@backingInt(Feature.clrbhb)] = .{
475 .llvm_name = "clrbhb",
476 .description = "Enable Clear BHB instruction",
477 .dependencies = featureSet(&[_]Feature{}),
478 };
479 result[@backingInt(Feature.cmh)] = .{
480 .llvm_name = "cmh",
481 .description = "Enable Armv9.7-A Contention Management Hints",
482 .dependencies = featureSet(&[_]Feature{}),
483 };
484 result[@backingInt(Feature.cmp_bcc_fusion)] = .{
485 .llvm_name = "cmp-bcc-fusion",
486 .description = "CPU fuses cmp+bcc operations",
487 .dependencies = featureSet(&[_]Feature{}),
488 };
489 result[@backingInt(Feature.cmpbr)] = .{
490 .llvm_name = "cmpbr",
491 .description = "Enable Armv9.6-A base compare and branch instructions",
492 .dependencies = featureSet(&[_]Feature{}),
493 };
494 result[@backingInt(Feature.complxnum)] = .{
495 .llvm_name = "complxnum",
496 .description = "Enable Armv8.3-A Floating-point complex number support",
497 .dependencies = featureSet(&[_]Feature{
498 .neon,
499 }),
500 };
501 result[@backingInt(Feature.contextidr_el2)] = .{
502 .llvm_name = "CONTEXTIDREL2",
503 .description = "Enable RW operand Context ID Register (EL2)",
504 .dependencies = featureSet(&[_]Feature{}),
505 };
506 result[@backingInt(Feature.cpa)] = .{
507 .llvm_name = "cpa",
508 .description = "Enable Armv9.5-A Checked Pointer Arithmetic",
509 .dependencies = featureSet(&[_]Feature{}),
510 };
511 result[@backingInt(Feature.crc)] = .{
512 .llvm_name = "crc",
513 .description = "Enable Armv8.0-A CRC-32 checksum instructions",
514 .dependencies = featureSet(&[_]Feature{}),
515 };
516 result[@backingInt(Feature.crypto)] = .{
517 .llvm_name = "crypto",
518 .description = "Enable cryptographic instructions",
519 .dependencies = featureSet(&[_]Feature{
520 .aes,
521 .sha2,
522 }),
523 };
524 result[@backingInt(Feature.cssc)] = .{
525 .llvm_name = "cssc",
526 .description = "Enable Common Short Sequence Compression (CSSC) instructions",
527 .dependencies = featureSet(&[_]Feature{}),
528 };
529 result[@backingInt(Feature.d128)] = .{
530 .llvm_name = "d128",
531 .description = "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers and instructions",
532 .dependencies = featureSet(&[_]Feature{
533 .lse128,
534 }),
535 };
536 result[@backingInt(Feature.disable_fast_inc_vl)] = .{
537 .llvm_name = "disable-fast-inc-vl",
538 .description = "Do not prefer INC/DEC, ALL, { 1, 2, 4 } over ADDVL",
539 .dependencies = featureSet(&[_]Feature{}),
540 };
541 result[@backingInt(Feature.disable_latency_sched_heuristic)] = .{
542 .llvm_name = "disable-latency-sched-heuristic",
543 .description = "Disable latency scheduling heuristic",
544 .dependencies = featureSet(&[_]Feature{}),
545 };
546 result[@backingInt(Feature.disable_ldp)] = .{
547 .llvm_name = "disable-ldp",
548 .description = "Do not emit ldp",
549 .dependencies = featureSet(&[_]Feature{}),
550 };
551 result[@backingInt(Feature.disable_maximize_scalable_bandwidth)] = .{
552 .llvm_name = "disable-maximize-scalable-bandwidth",
553 .description = "Determine the maximum scalable vector length for a loop by the largest scalar type rather than the smallest",
554 .dependencies = featureSet(&[_]Feature{}),
555 };
556 result[@backingInt(Feature.disable_stp)] = .{
557 .llvm_name = "disable-stp",
558 .description = "Do not emit stp",
559 .dependencies = featureSet(&[_]Feature{}),
560 };
561 result[@backingInt(Feature.disable_unpredicated_ld_st_lower)] = .{
562 .llvm_name = "disable-unpredicated-ld-st-lower",
563 .description = "Disable lowering unpredicated loads/stores as LDR/STR",
564 .dependencies = featureSet(&[_]Feature{}),
565 };
566 result[@backingInt(Feature.dit)] = .{
567 .llvm_name = "dit",
568 .description = "Enable Armv8.4-A Data Independent Timing instructions",
569 .dependencies = featureSet(&[_]Feature{}),
570 };
571 result[@backingInt(Feature.dotprod)] = .{
572 .llvm_name = "dotprod",
573 .description = "Enable dot product support",
574 .dependencies = featureSet(&[_]Feature{
575 .neon,
576 }),
577 };
578 result[@backingInt(Feature.ecv)] = .{
579 .llvm_name = "ecv",
580 .description = "Enable enhanced counter virtualization extension",
581 .dependencies = featureSet(&[_]Feature{}),
582 };
583 result[@backingInt(Feature.el2vmsa)] = .{
584 .llvm_name = "el2vmsa",
585 .description = "Enable Exception Level 2 Virtual Memory System Architecture",
586 .dependencies = featureSet(&[_]Feature{}),
587 };
588 result[@backingInt(Feature.el3)] = .{
589 .llvm_name = "el3",
590 .description = "Enable Exception Level 3",
591 .dependencies = featureSet(&[_]Feature{}),
592 };
593 result[@backingInt(Feature.enable_select_opt)] = .{
594 .llvm_name = "enable-select-opt",
595 .description = "Enable the select optimize pass for select loop heuristics",
596 .dependencies = featureSet(&[_]Feature{}),
597 };
598 result[@backingInt(Feature.ete)] = .{
599 .llvm_name = "ete",
600 .description = "Enable Embedded Trace Extension",
601 .dependencies = featureSet(&[_]Feature{
602 .trbe,
603 }),
604 };
605 result[@backingInt(Feature.execute_only)] = .{
606 .llvm_name = "execute-only",
607 .description = "Enable the generation of execute only code.",
608 .dependencies = featureSet(&[_]Feature{}),
609 };
610 result[@backingInt(Feature.exynos_cheap_as_move)] = .{
611 .llvm_name = "exynos-cheap-as-move",
612 .description = "Use Exynos specific handling of cheap instructions",
613 .dependencies = featureSet(&[_]Feature{}),
614 };
615 result[@backingInt(Feature.f16f32dot)] = .{
616 .llvm_name = "f16f32dot",
617 .description = "Enable Armv9.7-A Advanced SIMD half-precision dot product accumulate to single-precision",
618 .dependencies = featureSet(&[_]Feature{
619 .fullfp16,
620 .neon,
621 }),
622 };
623 result[@backingInt(Feature.f16f32mm)] = .{
624 .llvm_name = "f16f32mm",
625 .description = "Enable Armv9.7-A Advanced SIMD half-precision matrix multiply-accumulate to single-precision",
626 .dependencies = featureSet(&[_]Feature{
627 .fullfp16,
628 .neon,
629 }),
630 };
631 result[@backingInt(Feature.f16mm)] = .{
632 .llvm_name = "f16mm",
633 .description = "Enable Armv9.7-A non-widening half-precision matrix multiply-accumulate",
634 .dependencies = featureSet(&[_]Feature{
635 .fullfp16,
636 .neon,
637 }),
638 };
639 result[@backingInt(Feature.f32mm)] = .{
640 .llvm_name = "f32mm",
641 .description = "Enable Matrix Multiply FP32 Extension",
642 .dependencies = featureSet(&[_]Feature{
643 .sve,
644 }),
645 };
646 result[@backingInt(Feature.f64mm)] = .{
647 .llvm_name = "f64mm",
648 .description = "Enable Matrix Multiply FP64 Extension",
649 .dependencies = featureSet(&[_]Feature{
650 .sve,
651 }),
652 };
653 result[@backingInt(Feature.f8f16mm)] = .{
654 .llvm_name = "f8f16mm",
655 .description = "Enable Armv9.6-A FP8 to Half-Precision Matrix Multiplication",
656 .dependencies = featureSet(&[_]Feature{
657 .fp8,
658 }),
659 };
660 result[@backingInt(Feature.f8f32mm)] = .{
661 .llvm_name = "f8f32mm",
662 .description = "Enable Armv9.6-A FP8 to Single-Precision Matrix Multiplication",
663 .dependencies = featureSet(&[_]Feature{
664 .fp8,
665 }),
666 };
667 result[@backingInt(Feature.faminmax)] = .{
668 .llvm_name = "faminmax",
669 .description = "Enable FAMIN and FAMAX instructions",
670 .dependencies = featureSet(&[_]Feature{
671 .neon,
672 }),
673 };
674 result[@backingInt(Feature.fgt)] = .{
675 .llvm_name = "fgt",
676 .description = "Enable fine grained virtualization traps extension",
677 .dependencies = featureSet(&[_]Feature{}),
678 };
679 result[@backingInt(Feature.fix_cortex_a53_835769)] = .{
680 .llvm_name = "fix-cortex-a53-835769",
681 .description = "Mitigate Cortex-A53 Erratum 835769",
682 .dependencies = featureSet(&[_]Feature{}),
683 };
684 result[@backingInt(Feature.flagm)] = .{
685 .llvm_name = "flagm",
686 .description = "Enable Armv8.4-A Flag Manipulation instructions",
687 .dependencies = featureSet(&[_]Feature{}),
688 };
689 result[@backingInt(Feature.fmv)] = .{
690 .llvm_name = "fmv",
691 .description = "Enable Function Multi Versioning support.",
692 .dependencies = featureSet(&[_]Feature{}),
693 };
694 result[@backingInt(Feature.force_32bit_jump_tables)] = .{
695 .llvm_name = "force-32bit-jump-tables",
696 .description = "Force jump table entries to be 32-bits wide except at MinSize",
697 .dependencies = featureSet(&[_]Feature{}),
698 };
699 result[@backingInt(Feature.fp16fml)] = .{
700 .llvm_name = "fp16fml",
701 .description = "Enable FP16 FML instructions",
702 .dependencies = featureSet(&[_]Feature{
703 .fullfp16,
704 .neon,
705 }),
706 };
707 result[@backingInt(Feature.fp8)] = .{
708 .llvm_name = "fp8",
709 .description = "Enable FP8 instructions",
710 .dependencies = featureSet(&[_]Feature{
711 .neon,
712 }),
713 };
714 result[@backingInt(Feature.fp8dot2)] = .{
715 .llvm_name = "fp8dot2",
716 .description = "Enable FP8 2-way dot instructions",
717 .dependencies = featureSet(&[_]Feature{
718 .fp8,
719 }),
720 };
721 result[@backingInt(Feature.fp8dot4)] = .{
722 .llvm_name = "fp8dot4",
723 .description = "Enable FP8 4-way dot instructions",
724 .dependencies = featureSet(&[_]Feature{
725 .fp8,
726 }),
727 };
728 result[@backingInt(Feature.fp8fma)] = .{
729 .llvm_name = "fp8fma",
730 .description = "Enable Armv9.5-A FP8 multiply-add instructions",
731 .dependencies = featureSet(&[_]Feature{
732 .fp8,
733 }),
734 };
735 result[@backingInt(Feature.fp_armv8)] = .{
736 .llvm_name = "fp-armv8",
737 .description = "Enable Armv8.0-A Floating Point Extensions",
738 .dependencies = featureSet(&[_]Feature{}),
739 };
740 result[@backingInt(Feature.fpac)] = .{
741 .llvm_name = "fpac",
742 .description = "Enable Armv8.3-A Pointer Authentication Faulting enhancement",
743 .dependencies = featureSet(&[_]Feature{}),
744 };
745 result[@backingInt(Feature.fprcvt)] = .{
746 .llvm_name = "fprcvt",
747 .description = "Enable Armv9.6-A base convert instructions for SIMD&FP scalar register operands of different input and output sizes",
748 .dependencies = featureSet(&[_]Feature{
749 .fp_armv8,
750 }),
751 };
752 result[@backingInt(Feature.fptoint)] = .{
753 .llvm_name = "fptoint",
754 .description = "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int",
755 .dependencies = featureSet(&[_]Feature{
756 .fp_armv8,
757 }),
758 };
759 result[@backingInt(Feature.fujitsu_monaka)] = .{
760 .llvm_name = "fujitsu-monaka",
761 .description = "Fujitsu FUJITSU-MONAKA processors",
762 .dependencies = featureSet(&[_]Feature{
763 .arith_bcc_fusion,
764 .enable_select_opt,
765 .predictable_select_expensive,
766 .use_postra_scheduler,
767 }),
768 };
769 result[@backingInt(Feature.fullfp16)] = .{
770 .llvm_name = "fullfp16",
771 .description = "Enable half-precision floating-point data processing",
772 .dependencies = featureSet(&[_]Feature{
773 .fp_armv8,
774 }),
775 };
776 result[@backingInt(Feature.fuse_address)] = .{
777 .llvm_name = "fuse-address",
778 .description = "CPU fuses address generation and memory operations",
779 .dependencies = featureSet(&[_]Feature{}),
780 };
781 result[@backingInt(Feature.fuse_addsub_2reg_const1)] = .{
782 .llvm_name = "fuse-addsub-2reg-const1",
783 .description = "CPU fuses (a + b + 1) and (a - b - 1)",
784 .dependencies = featureSet(&[_]Feature{}),
785 };
786 result[@backingInt(Feature.fuse_adrp_add)] = .{
787 .llvm_name = "fuse-adrp-add",
788 .description = "CPU fuses adrp+add operations",
789 .dependencies = featureSet(&[_]Feature{}),
790 };
791 result[@backingInt(Feature.fuse_aes)] = .{
792 .llvm_name = "fuse-aes",
793 .description = "CPU fuses AES crypto operations",
794 .dependencies = featureSet(&[_]Feature{}),
795 };
796 result[@backingInt(Feature.fuse_arith_logic)] = .{
797 .llvm_name = "fuse-arith-logic",
798 .description = "CPU fuses arithmetic and logic operations",
799 .dependencies = featureSet(&[_]Feature{}),
800 };
801 result[@backingInt(Feature.fuse_crypto_eor)] = .{
802 .llvm_name = "fuse-crypto-eor",
803 .description = "CPU fuses AES/PMULL and EOR operations",
804 .dependencies = featureSet(&[_]Feature{}),
805 };
806 result[@backingInt(Feature.fuse_csel)] = .{
807 .llvm_name = "fuse-csel",
808 .description = "CPU can fuse CMP and CSEL operations",
809 .dependencies = featureSet(&[_]Feature{}),
810 };
811 result[@backingInt(Feature.fuse_cset)] = .{
812 .llvm_name = "fuse-cset",
813 .description = "CPU can fuse CMP and CSET operations",
814 .dependencies = featureSet(&[_]Feature{}),
815 };
816 result[@backingInt(Feature.fuse_literals)] = .{
817 .llvm_name = "fuse-literals",
818 .description = "CPU fuses literal generation operations",
819 .dependencies = featureSet(&[_]Feature{}),
820 };
821 result[@backingInt(Feature.gcie)] = .{
822 .llvm_name = "gcie",
823 .description = "Enable GICv5 (Generic Interrupt Controller) CPU Interface Extension",
824 .dependencies = featureSet(&[_]Feature{}),
825 };
826 result[@backingInt(Feature.gcs)] = .{
827 .llvm_name = "gcs",
828 .description = "Enable Armv9.4-A Guarded Call Stack Extension",
829 .dependencies = featureSet(&[_]Feature{
830 .chk,
831 }),
832 };
833 result[@backingInt(Feature.harden_sls_blr)] = .{
834 .llvm_name = "harden-sls-blr",
835 .description = "Harden against straight line speculation across BLR instructions",
836 .dependencies = featureSet(&[_]Feature{}),
837 };
838 result[@backingInt(Feature.harden_sls_nocomdat)] = .{
839 .llvm_name = "harden-sls-nocomdat",
840 .description = "Generate thunk code for SLS mitigation in the normal text section",
841 .dependencies = featureSet(&[_]Feature{}),
842 };
843 result[@backingInt(Feature.harden_sls_retbr)] = .{
844 .llvm_name = "harden-sls-retbr",
845 .description = "Harden against straight line speculation across RET and BR instructions",
846 .dependencies = featureSet(&[_]Feature{}),
847 };
848 result[@backingInt(Feature.hbc)] = .{
849 .llvm_name = "hbc",
850 .description = "Enable Armv8.8-A Hinted Conditional Branches Extension",
851 .dependencies = featureSet(&[_]Feature{}),
852 };
853 result[@backingInt(Feature.hcx)] = .{
854 .llvm_name = "hcx",
855 .description = "Enable Armv8.7-A HCRX_EL2 system register",
856 .dependencies = featureSet(&[_]Feature{}),
857 };
858 result[@backingInt(Feature.i8mm)] = .{
859 .llvm_name = "i8mm",
860 .description = "Enable Matrix Multiply Int8 Extension",
861 .dependencies = featureSet(&[_]Feature{
862 .neon,
863 }),
864 };
865 result[@backingInt(Feature.ite)] = .{
866 .llvm_name = "ite",
867 .description = "Enable Armv9.4-A Instrumentation Extension",
868 .dependencies = featureSet(&[_]Feature{
869 .ete,
870 }),
871 };
872 result[@backingInt(Feature.jsconv)] = .{
873 .llvm_name = "jsconv",
874 .description = "Enable Armv8.3-A JavaScript FP conversion instructions",
875 .dependencies = featureSet(&[_]Feature{
876 .fp_armv8,
877 }),
878 };
879 result[@backingInt(Feature.ldp_aligned_only)] = .{
880 .llvm_name = "ldp-aligned-only",
881 .description = "In order to emit ldp, first check if the load will be aligned to 2 * element_size",
882 .dependencies = featureSet(&[_]Feature{}),
883 };
884 result[@backingInt(Feature.lor)] = .{
885 .llvm_name = "lor",
886 .description = "Enable Armv8.1-A Limited Ordering Regions extension",
887 .dependencies = featureSet(&[_]Feature{}),
888 };
889 result[@backingInt(Feature.ls64)] = .{
890 .llvm_name = "ls64",
891 .description = "Enable Armv8.7-A LD64B/ST64B Accelerator Extension",
892 .dependencies = featureSet(&[_]Feature{}),
893 };
894 result[@backingInt(Feature.lscp)] = .{
895 .llvm_name = "lscp",
896 .description = "Enable Armv9.7-A Load-acquire and store-release pair extension",
897 .dependencies = featureSet(&[_]Feature{}),
898 };
899 result[@backingInt(Feature.lse)] = .{
900 .llvm_name = "lse",
901 .description = "Enable Armv8.1-A Large System Extension (LSE) atomic instructions",
902 .dependencies = featureSet(&[_]Feature{}),
903 };
904 result[@backingInt(Feature.lse128)] = .{
905 .llvm_name = "lse128",
906 .description = "Enable Armv9.4-A 128-bit Atomic instructions",
907 .dependencies = featureSet(&[_]Feature{
908 .lse,
909 }),
910 };
911 result[@backingInt(Feature.lse2)] = .{
912 .llvm_name = "lse2",
913 .description = "Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules",
914 .dependencies = featureSet(&[_]Feature{}),
915 };
916 result[@backingInt(Feature.lsfe)] = .{
917 .llvm_name = "lsfe",
918 .description = "Enable Armv9.6-A base Atomic floating-point in-memory instructions",
919 .dependencies = featureSet(&[_]Feature{
920 .fp_armv8,
921 }),
922 };
923 result[@backingInt(Feature.lsui)] = .{
924 .llvm_name = "lsui",
925 .description = "Enable Armv9.6-A unprivileged load/store instructions",
926 .dependencies = featureSet(&[_]Feature{}),
927 };
928 result[@backingInt(Feature.lut)] = .{
929 .llvm_name = "lut",
930 .description = "Enable Lookup Table instructions",
931 .dependencies = featureSet(&[_]Feature{
932 .neon,
933 }),
934 };
935 result[@backingInt(Feature.max_interleave_factor_4)] = .{
936 .llvm_name = "max-interleave-factor-4",
937 .description = "Set the MaxInterleaveFactor to 4 (from the default 2)",
938 .dependencies = featureSet(&[_]Feature{}),
939 };
940 result[@backingInt(Feature.mec)] = .{
941 .llvm_name = "mec",
942 .description = "Enable Memory Encryption Contexts Extension",
943 .dependencies = featureSet(&[_]Feature{
944 .rme,
945 }),
946 };
947 result[@backingInt(Feature.mops)] = .{
948 .llvm_name = "mops",
949 .description = "Enable Armv8.8-A memcpy and memset acceleration instructions",
950 .dependencies = featureSet(&[_]Feature{}),
951 };
952 result[@backingInt(Feature.mops_go)] = .{
953 .llvm_name = "mops-go",
954 .description = "Enable memset acceleration granule only",
955 .dependencies = featureSet(&[_]Feature{
956 .mops,
957 .mte,
958 }),
959 };
960 result[@backingInt(Feature.mpam)] = .{
961 .llvm_name = "mpam",
962 .description = "Enable Armv8.4-A Memory system Partitioning and Monitoring extension",
963 .dependencies = featureSet(&[_]Feature{}),
964 };
965 result[@backingInt(Feature.mpamv2)] = .{
966 .llvm_name = "mpamv2",
967 .description = "Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions",
968 .dependencies = featureSet(&[_]Feature{}),
969 };
970 result[@backingInt(Feature.mte)] = .{
971 .llvm_name = "mte",
972 .description = "Enable Memory Tagging Extension",
973 .dependencies = featureSet(&[_]Feature{}),
974 };
975 result[@backingInt(Feature.mtetc)] = .{
976 .llvm_name = "mtetc",
977 .description = "Enable Virtual Memory Tagging Extension",
978 .dependencies = featureSet(&[_]Feature{
979 .mte,
980 }),
981 };
982 result[@backingInt(Feature.neon)] = .{
983 .llvm_name = "neon",
984 .description = "Enable Advanced SIMD instructions",
985 .dependencies = featureSet(&[_]Feature{
986 .fp_armv8,
987 }),
988 };
989 result[@backingInt(Feature.nmi)] = .{
990 .llvm_name = "nmi",
991 .description = "Enable Armv8.8-A Non-maskable Interrupts",
992 .dependencies = featureSet(&[_]Feature{}),
993 };
994 result[@backingInt(Feature.no_bti_at_return_twice)] = .{
995 .llvm_name = "no-bti-at-return-twice",
996 .description = "Don't place a BTI instruction after a return-twice",
997 .dependencies = featureSet(&[_]Feature{}),
998 };
999 result[@backingInt(Feature.no_neg_immediates)] = .{
1000 .llvm_name = "no-neg-immediates",
1001 .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
1002 .dependencies = featureSet(&[_]Feature{}),
1003 };
1004 result[@backingInt(Feature.no_sve_fp_ld1r)] = .{
1005 .llvm_name = "no-sve-fp-ld1r",
1006 .description = "Avoid using LD1RX instructions for FP",
1007 .dependencies = featureSet(&[_]Feature{}),
1008 };
1009 result[@backingInt(Feature.no_zcz_fpr64)] = .{
1010 .llvm_name = "no-zcz-fpr64",
1011 .description = "Has no zero-cycle zeroing instructions for FPR64 registers",
1012 .dependencies = featureSet(&[_]Feature{}),
1013 };
1014 result[@backingInt(Feature.nv)] = .{
1015 .llvm_name = "nv",
1016 .description = "Enable Armv8.4-A Nested Virtualization Enchancement",
1017 .dependencies = featureSet(&[_]Feature{}),
1018 };
1019 result[@backingInt(Feature.occmo)] = .{
1020 .llvm_name = "occmo",
1021 .description = "Enable Armv9.6-A Outer cacheable cache maintenance operations",
1022 .dependencies = featureSet(&[_]Feature{}),
1023 };
1024 result[@backingInt(Feature.olympus)] = .{
1025 .llvm_name = "olympus",
1026 .description = "NVIDIA Olympus processors",
1027 .dependencies = featureSet(&[_]Feature{
1028 .alu_lsl_fast,
1029 .cmp_bcc_fusion,
1030 .enable_select_opt,
1031 .fuse_adrp_add,
1032 .fuse_aes,
1033 .max_interleave_factor_4,
1034 .predictable_select_expensive,
1035 .use_fixed_over_scalable_if_equal_cost,
1036 .use_postra_scheduler,
1037 }),
1038 };
1039 result[@backingInt(Feature.outline_atomics)] = .{
1040 .llvm_name = "outline-atomics",
1041 .description = "Enable out of line atomics to support LSE instructions",
1042 .dependencies = featureSet(&[_]Feature{}),
1043 };
1044 result[@backingInt(Feature.pan)] = .{
1045 .llvm_name = "pan",
1046 .description = "Enable Armv8.1-A Privileged Access-Never extension",
1047 .dependencies = featureSet(&[_]Feature{}),
1048 };
1049 result[@backingInt(Feature.pan_rwv)] = .{
1050 .llvm_name = "pan-rwv",
1051 .description = "Enable Armv8.2-A PAN s1e1R and s1e1W Variants",
1052 .dependencies = featureSet(&[_]Feature{
1053 .pan,
1054 }),
1055 };
1056 result[@backingInt(Feature.pauth)] = .{
1057 .llvm_name = "pauth",
1058 .description = "Enable Armv8.3-A Pointer Authentication extension",
1059 .dependencies = featureSet(&[_]Feature{}),
1060 };
1061 result[@backingInt(Feature.pauth_lr)] = .{
1062 .llvm_name = "pauth-lr",
1063 .description = "Enable Armv9.5-A PAC enhancements",
1064 .dependencies = featureSet(&[_]Feature{}),
1065 };
1066 result[@backingInt(Feature.pcdphint)] = .{
1067 .llvm_name = "pcdphint",
1068 .description = "Enable Armv9.6-A Producer Consumer Data Placement hints",
1069 .dependencies = featureSet(&[_]Feature{}),
1070 };
1071 result[@backingInt(Feature.perfmon)] = .{
1072 .llvm_name = "perfmon",
1073 .description = "Enable Armv8.0-A PMUv3 Performance Monitors extension",
1074 .dependencies = featureSet(&[_]Feature{}),
1075 };
1076 result[@backingInt(Feature.poe2)] = .{
1077 .llvm_name = "poe2",
1078 .description = "Enable Stage 1 Permission Overlays Extension 2 instructions",
1079 .dependencies = featureSet(&[_]Feature{}),
1080 };
1081 result[@backingInt(Feature.pops)] = .{
1082 .llvm_name = "pops",
1083 .description = "Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions",
1084 .dependencies = featureSet(&[_]Feature{}),
1085 };
1086 result[@backingInt(Feature.predictable_select_expensive)] = .{
1087 .llvm_name = "predictable-select-expensive",
1088 .description = "Prefer likely predicted branches over selects",
1089 .dependencies = featureSet(&[_]Feature{}),
1090 };
1091 result[@backingInt(Feature.predres)] = .{
1092 .llvm_name = "predres",
1093 .description = "Enable Armv8.5-A execution and data prediction invalidation instructions",
1094 .dependencies = featureSet(&[_]Feature{}),
1095 };
1096 result[@backingInt(Feature.prfm_slc_target)] = .{
1097 .llvm_name = "prfm-slc-target",
1098 .description = "Enable SLC target for PRFM instruction",
1099 .dependencies = featureSet(&[_]Feature{}),
1100 };
1101 result[@backingInt(Feature.rand)] = .{
1102 .llvm_name = "rand",
1103 .description = "Enable Random Number generation instructions",
1104 .dependencies = featureSet(&[_]Feature{}),
1105 };
1106 result[@backingInt(Feature.ras)] = .{
1107 .llvm_name = "ras",
1108 .description = "Enable Armv8.0-A Reliability, Availability and Serviceability Extensions",
1109 .dependencies = featureSet(&[_]Feature{}),
1110 };
1111 result[@backingInt(Feature.rasv2)] = .{
1112 .llvm_name = "rasv2",
1113 .description = "Enable Armv8.9-A Reliability, Availability and Serviceability Extensions",
1114 .dependencies = featureSet(&[_]Feature{
1115 .ras,
1116 }),
1117 };
1118 result[@backingInt(Feature.rcpc)] = .{
1119 .llvm_name = "rcpc",
1120 .description = "Enable support for RCPC extension",
1121 .dependencies = featureSet(&[_]Feature{}),
1122 };
1123 result[@backingInt(Feature.rcpc3)] = .{
1124 .llvm_name = "rcpc3",
1125 .description = "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set",
1126 .dependencies = featureSet(&[_]Feature{
1127 .rcpc_immo,
1128 }),
1129 };
1130 result[@backingInt(Feature.rcpc_immo)] = .{
1131 .llvm_name = "rcpc-immo",
1132 .description = "Enable Armv8.4-A RCPC instructions with Immediate Offsets",
1133 .dependencies = featureSet(&[_]Feature{
1134 .rcpc,
1135 }),
1136 };
1137 result[@backingInt(Feature.rdm)] = .{
1138 .llvm_name = "rdm",
1139 .description = "Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions",
1140 .dependencies = featureSet(&[_]Feature{
1141 .neon,
1142 }),
1143 };
1144 result[@backingInt(Feature.reserve_lr_for_ra)] = .{
1145 .llvm_name = "reserve-lr-for-ra",
1146 .description = "Reserve LR for call use only",
1147 .dependencies = featureSet(&[_]Feature{}),
1148 };
1149 result[@backingInt(Feature.reserve_x1)] = .{
1150 .llvm_name = "reserve-x1",
1151 .description = "Reserve X1, making it unavailable as a GPR",
1152 .dependencies = featureSet(&[_]Feature{}),
1153 };
1154 result[@backingInt(Feature.reserve_x10)] = .{
1155 .llvm_name = "reserve-x10",
1156 .description = "Reserve X10, making it unavailable as a GPR",
1157 .dependencies = featureSet(&[_]Feature{}),
1158 };
1159 result[@backingInt(Feature.reserve_x11)] = .{
1160 .llvm_name = "reserve-x11",
1161 .description = "Reserve X11, making it unavailable as a GPR",
1162 .dependencies = featureSet(&[_]Feature{}),
1163 };
1164 result[@backingInt(Feature.reserve_x12)] = .{
1165 .llvm_name = "reserve-x12",
1166 .description = "Reserve X12, making it unavailable as a GPR",
1167 .dependencies = featureSet(&[_]Feature{}),
1168 };
1169 result[@backingInt(Feature.reserve_x13)] = .{
1170 .llvm_name = "reserve-x13",
1171 .description = "Reserve X13, making it unavailable as a GPR",
1172 .dependencies = featureSet(&[_]Feature{}),
1173 };
1174 result[@backingInt(Feature.reserve_x14)] = .{
1175 .llvm_name = "reserve-x14",
1176 .description = "Reserve X14, making it unavailable as a GPR",
1177 .dependencies = featureSet(&[_]Feature{}),
1178 };
1179 result[@backingInt(Feature.reserve_x15)] = .{
1180 .llvm_name = "reserve-x15",
1181 .description = "Reserve X15, making it unavailable as a GPR",
1182 .dependencies = featureSet(&[_]Feature{}),
1183 };
1184 result[@backingInt(Feature.reserve_x18)] = .{
1185 .llvm_name = "reserve-x18",
1186 .description = "Reserve X18, making it unavailable as a GPR",
1187 .dependencies = featureSet(&[_]Feature{}),
1188 };
1189 result[@backingInt(Feature.reserve_x2)] = .{
1190 .llvm_name = "reserve-x2",
1191 .description = "Reserve X2, making it unavailable as a GPR",
1192 .dependencies = featureSet(&[_]Feature{}),
1193 };
1194 result[@backingInt(Feature.reserve_x20)] = .{
1195 .llvm_name = "reserve-x20",
1196 .description = "Reserve X20, making it unavailable as a GPR",
1197 .dependencies = featureSet(&[_]Feature{}),
1198 };
1199 result[@backingInt(Feature.reserve_x21)] = .{
1200 .llvm_name = "reserve-x21",
1201 .description = "Reserve X21, making it unavailable as a GPR",
1202 .dependencies = featureSet(&[_]Feature{}),
1203 };
1204 result[@backingInt(Feature.reserve_x22)] = .{
1205 .llvm_name = "reserve-x22",
1206 .description = "Reserve X22, making it unavailable as a GPR",
1207 .dependencies = featureSet(&[_]Feature{}),
1208 };
1209 result[@backingInt(Feature.reserve_x23)] = .{
1210 .llvm_name = "reserve-x23",
1211 .description = "Reserve X23, making it unavailable as a GPR",
1212 .dependencies = featureSet(&[_]Feature{}),
1213 };
1214 result[@backingInt(Feature.reserve_x24)] = .{
1215 .llvm_name = "reserve-x24",
1216 .description = "Reserve X24, making it unavailable as a GPR",
1217 .dependencies = featureSet(&[_]Feature{}),
1218 };
1219 result[@backingInt(Feature.reserve_x25)] = .{
1220 .llvm_name = "reserve-x25",
1221 .description = "Reserve X25, making it unavailable as a GPR",
1222 .dependencies = featureSet(&[_]Feature{}),
1223 };
1224 result[@backingInt(Feature.reserve_x26)] = .{
1225 .llvm_name = "reserve-x26",
1226 .description = "Reserve X26, making it unavailable as a GPR",
1227 .dependencies = featureSet(&[_]Feature{}),
1228 };
1229 result[@backingInt(Feature.reserve_x27)] = .{
1230 .llvm_name = "reserve-x27",
1231 .description = "Reserve X27, making it unavailable as a GPR",
1232 .dependencies = featureSet(&[_]Feature{}),
1233 };
1234 result[@backingInt(Feature.reserve_x28)] = .{
1235 .llvm_name = "reserve-x28",
1236 .description = "Reserve X28, making it unavailable as a GPR",
1237 .dependencies = featureSet(&[_]Feature{}),
1238 };
1239 result[@backingInt(Feature.reserve_x3)] = .{
1240 .llvm_name = "reserve-x3",
1241 .description = "Reserve X3, making it unavailable as a GPR",
1242 .dependencies = featureSet(&[_]Feature{}),
1243 };
1244 result[@backingInt(Feature.reserve_x4)] = .{
1245 .llvm_name = "reserve-x4",
1246 .description = "Reserve X4, making it unavailable as a GPR",
1247 .dependencies = featureSet(&[_]Feature{}),
1248 };
1249 result[@backingInt(Feature.reserve_x5)] = .{
1250 .llvm_name = "reserve-x5",
1251 .description = "Reserve X5, making it unavailable as a GPR",
1252 .dependencies = featureSet(&[_]Feature{}),
1253 };
1254 result[@backingInt(Feature.reserve_x6)] = .{
1255 .llvm_name = "reserve-x6",
1256 .description = "Reserve X6, making it unavailable as a GPR",
1257 .dependencies = featureSet(&[_]Feature{}),
1258 };
1259 result[@backingInt(Feature.reserve_x7)] = .{
1260 .llvm_name = "reserve-x7",
1261 .description = "Reserve X7, making it unavailable as a GPR",
1262 .dependencies = featureSet(&[_]Feature{}),
1263 };
1264 result[@backingInt(Feature.reserve_x9)] = .{
1265 .llvm_name = "reserve-x9",
1266 .description = "Reserve X9, making it unavailable as a GPR",
1267 .dependencies = featureSet(&[_]Feature{}),
1268 };
1269 result[@backingInt(Feature.rme)] = .{
1270 .llvm_name = "rme",
1271 .description = "Enable Realm Management Extension",
1272 .dependencies = featureSet(&[_]Feature{}),
1273 };
1274 result[@backingInt(Feature.sb)] = .{
1275 .llvm_name = "sb",
1276 .description = "Enable Armv8.5-A Speculation Barrier",
1277 .dependencies = featureSet(&[_]Feature{}),
1278 };
1279 result[@backingInt(Feature.sel2)] = .{
1280 .llvm_name = "sel2",
1281 .description = "Enable Armv8.4-A Secure Exception Level 2 extension",
1282 .dependencies = featureSet(&[_]Feature{}),
1283 };
1284 result[@backingInt(Feature.sha2)] = .{
1285 .llvm_name = "sha2",
1286 .description = "Enable SHA1 and SHA256 support",
1287 .dependencies = featureSet(&[_]Feature{
1288 .neon,
1289 }),
1290 };
1291 result[@backingInt(Feature.sha3)] = .{
1292 .llvm_name = "sha3",
1293 .description = "Enable SHA512 and SHA3 support",
1294 .dependencies = featureSet(&[_]Feature{
1295 .sha2,
1296 }),
1297 };
1298 result[@backingInt(Feature.slow_misaligned_128store)] = .{
1299 .llvm_name = "slow-misaligned-128store",
1300 .description = "Misaligned 128 bit stores are slow",
1301 .dependencies = featureSet(&[_]Feature{}),
1302 };
1303 result[@backingInt(Feature.slow_paired_128)] = .{
1304 .llvm_name = "slow-paired-128",
1305 .description = "Paired 128 bit loads and stores are slow",
1306 .dependencies = featureSet(&[_]Feature{}),
1307 };
1308 result[@backingInt(Feature.slow_strqro_store)] = .{
1309 .llvm_name = "slow-strqro-store",
1310 .description = "STR of Q register with register offset is slow",
1311 .dependencies = featureSet(&[_]Feature{}),
1312 };
1313 result[@backingInt(Feature.sm4)] = .{
1314 .llvm_name = "sm4",
1315 .description = "Enable SM3 and SM4 support",
1316 .dependencies = featureSet(&[_]Feature{
1317 .neon,
1318 }),
1319 };
1320 result[@backingInt(Feature.sme)] = .{
1321 .llvm_name = "sme",
1322 .description = "Enable Scalable Matrix Extension (SME)",
1323 .dependencies = featureSet(&[_]Feature{
1324 .bf16,
1325 .fullfp16,
1326 }),
1327 };
1328 result[@backingInt(Feature.sme2)] = .{
1329 .llvm_name = "sme2",
1330 .description = "Enable Scalable Matrix Extension 2 (SME2) instructions",
1331 .dependencies = featureSet(&[_]Feature{
1332 .sme,
1333 }),
1334 };
1335 result[@backingInt(Feature.sme2p1)] = .{
1336 .llvm_name = "sme2p1",
1337 .description = "Enable Scalable Matrix Extension 2.1 instructions",
1338 .dependencies = featureSet(&[_]Feature{
1339 .sme2,
1340 }),
1341 };
1342 result[@backingInt(Feature.sme2p2)] = .{
1343 .llvm_name = "sme2p2",
1344 .description = "Enable Armv9.6-A Scalable Matrix Extension 2.2 instructions",
1345 .dependencies = featureSet(&[_]Feature{
1346 .sme2p1,
1347 }),
1348 };
1349 result[@backingInt(Feature.sme2p3)] = .{
1350 .llvm_name = "sme2p3",
1351 .description = "Enable Armv9.7-A Scalable Matrix Extension 2.3 instructions",
1352 .dependencies = featureSet(&[_]Feature{
1353 .sme2p2,
1354 }),
1355 };
1356 result[@backingInt(Feature.sme_b16b16)] = .{
1357 .llvm_name = "sme-b16b16",
1358 .description = "Enable SME2.1 ZA-targeting non-widening BFloat16 instructions",
1359 .dependencies = featureSet(&[_]Feature{
1360 .sme2,
1361 .sve_b16b16,
1362 }),
1363 };
1364 result[@backingInt(Feature.sme_f16f16)] = .{
1365 .llvm_name = "sme-f16f16",
1366 .description = "Enable SME non-widening Float16 instructions",
1367 .dependencies = featureSet(&[_]Feature{
1368 .sme2,
1369 }),
1370 };
1371 result[@backingInt(Feature.sme_f64f64)] = .{
1372 .llvm_name = "sme-f64f64",
1373 .description = "Enable Scalable Matrix Extension (SME) F64F64 instructions",
1374 .dependencies = featureSet(&[_]Feature{
1375 .sme,
1376 }),
1377 };
1378 result[@backingInt(Feature.sme_f8f16)] = .{
1379 .llvm_name = "sme-f8f16",
1380 .description = "Enable Scalable Matrix Extension (SME) F8F16 instructions",
1381 .dependencies = featureSet(&[_]Feature{
1382 .fp8,
1383 .sme2,
1384 }),
1385 };
1386 result[@backingInt(Feature.sme_f8f32)] = .{
1387 .llvm_name = "sme-f8f32",
1388 .description = "Enable Scalable Matrix Extension (SME) F8F32 instructions",
1389 .dependencies = featureSet(&[_]Feature{
1390 .fp8,
1391 .sme2,
1392 }),
1393 };
1394 result[@backingInt(Feature.sme_fa64)] = .{
1395 .llvm_name = "sme-fa64",
1396 .description = "Enable the full A64 instruction set in streaming SVE mode",
1397 .dependencies = featureSet(&[_]Feature{
1398 .sme,
1399 .sve2,
1400 }),
1401 };
1402 result[@backingInt(Feature.sme_i16i64)] = .{
1403 .llvm_name = "sme-i16i64",
1404 .description = "Enable Scalable Matrix Extension (SME) I16I64 instructions",
1405 .dependencies = featureSet(&[_]Feature{
1406 .sme,
1407 }),
1408 };
1409 result[@backingInt(Feature.sme_lutv2)] = .{
1410 .llvm_name = "sme-lutv2",
1411 .description = "Enable Scalable Matrix Extension (SME) LUTv2 instructions",
1412 .dependencies = featureSet(&[_]Feature{
1413 .sme2,
1414 }),
1415 };
1416 result[@backingInt(Feature.sme_mop4)] = .{
1417 .llvm_name = "sme-mop4",
1418 .description = "Enable SME Quarter-tile outer product instructions",
1419 .dependencies = featureSet(&[_]Feature{
1420 .sme2,
1421 }),
1422 };
1423 result[@backingInt(Feature.sme_tmop)] = .{
1424 .llvm_name = "sme-tmop",
1425 .description = "Enable SME Structured sparsity outer product instructions.",
1426 .dependencies = featureSet(&[_]Feature{
1427 .sme2,
1428 }),
1429 };
1430 result[@backingInt(Feature.spe)] = .{
1431 .llvm_name = "spe",
1432 .description = "Enable Statistical Profiling extension",
1433 .dependencies = featureSet(&[_]Feature{}),
1434 };
1435 result[@backingInt(Feature.spe_eef)] = .{
1436 .llvm_name = "spe-eef",
1437 .description = "Enable extra register in the Statistical Profiling Extension",
1438 .dependencies = featureSet(&[_]Feature{}),
1439 };
1440 result[@backingInt(Feature.specres2)] = .{
1441 .llvm_name = "specres2",
1442 .description = "Enable Speculation Restriction Instruction",
1443 .dependencies = featureSet(&[_]Feature{
1444 .predres,
1445 }),
1446 };
1447 result[@backingInt(Feature.specrestrict)] = .{
1448 .llvm_name = "specrestrict",
1449 .description = "Enable architectural speculation restriction",
1450 .dependencies = featureSet(&[_]Feature{}),
1451 };
1452 result[@backingInt(Feature.ssbs)] = .{
1453 .llvm_name = "ssbs",
1454 .description = "Enable Speculative Store Bypass Safe bit",
1455 .dependencies = featureSet(&[_]Feature{}),
1456 };
1457 result[@backingInt(Feature.ssve_aes)] = .{
1458 .llvm_name = "ssve-aes",
1459 .description = "Enable Armv9.6-A SVE AES support in streaming SVE mode",
1460 .dependencies = featureSet(&[_]Feature{
1461 .sme2,
1462 .sve_aes,
1463 }),
1464 };
1465 result[@backingInt(Feature.ssve_bitperm)] = .{
1466 .llvm_name = "ssve-bitperm",
1467 .description = "Enable Armv9.6-A SVE BitPerm support in streaming SVE mode",
1468 .dependencies = featureSet(&[_]Feature{
1469 .sme2,
1470 .sve_bitperm,
1471 }),
1472 };
1473 result[@backingInt(Feature.ssve_fexpa)] = .{
1474 .llvm_name = "ssve-fexpa",
1475 .description = "Enable SVE FEXPA instruction in Streaming SVE mode",
1476 .dependencies = featureSet(&[_]Feature{
1477 .sme2,
1478 }),
1479 };
1480 result[@backingInt(Feature.ssve_fp8dot2)] = .{
1481 .llvm_name = "ssve-fp8dot2",
1482 .description = "Enable SVE2 FP8 2-way dot product instructions",
1483 .dependencies = featureSet(&[_]Feature{
1484 .fp8,
1485 .sme2,
1486 }),
1487 };
1488 result[@backingInt(Feature.ssve_fp8dot4)] = .{
1489 .llvm_name = "ssve-fp8dot4",
1490 .description = "Enable SVE2 FP8 4-way dot product instructions",
1491 .dependencies = featureSet(&[_]Feature{
1492 .fp8,
1493 .sme2,
1494 }),
1495 };
1496 result[@backingInt(Feature.ssve_fp8fma)] = .{
1497 .llvm_name = "ssve-fp8fma",
1498 .description = "Enable SVE2 FP8 multiply-add instructions",
1499 .dependencies = featureSet(&[_]Feature{
1500 .fp8,
1501 .sme2,
1502 }),
1503 };
1504 result[@backingInt(Feature.store_pair_suppress)] = .{
1505 .llvm_name = "store-pair-suppress",
1506 .description = "Enable Store Pair Suppression heuristics",
1507 .dependencies = featureSet(&[_]Feature{}),
1508 };
1509 result[@backingInt(Feature.stp_aligned_only)] = .{
1510 .llvm_name = "stp-aligned-only",
1511 .description = "In order to emit stp, first check if the store will be aligned to 2 * element_size",
1512 .dependencies = featureSet(&[_]Feature{}),
1513 };
1514 result[@backingInt(Feature.strict_align)] = .{
1515 .llvm_name = "strict-align",
1516 .description = "Disallow all unaligned memory access",
1517 .dependencies = featureSet(&[_]Feature{}),
1518 };
1519 result[@backingInt(Feature.sve)] = .{
1520 .llvm_name = "sve",
1521 .description = "Enable Scalable Vector Extension (SVE) instructions",
1522 .dependencies = featureSet(&[_]Feature{
1523 .fullfp16,
1524 }),
1525 };
1526 result[@backingInt(Feature.sve2)] = .{
1527 .llvm_name = "sve2",
1528 .description = "Enable Scalable Vector Extension 2 (SVE2) instructions",
1529 .dependencies = featureSet(&[_]Feature{
1530 .sve,
1531 }),
1532 };
1533 result[@backingInt(Feature.sve2_aes)] = .{
1534 .llvm_name = "sve2-aes",
1535 .description = "Shorthand for +sve2+sve-aes",
1536 .dependencies = featureSet(&[_]Feature{
1537 .sve2,
1538 .sve_aes,
1539 }),
1540 };
1541 result[@backingInt(Feature.sve2_bitperm)] = .{
1542 .llvm_name = "sve2-bitperm",
1543 .description = "Shorthand for +sve2+sve-bitperm",
1544 .dependencies = featureSet(&[_]Feature{
1545 .sve2,
1546 .sve_bitperm,
1547 }),
1548 };
1549 result[@backingInt(Feature.sve2_sha3)] = .{
1550 .llvm_name = "sve2-sha3",
1551 .description = "Shorthand for +sve2+sve-sha3",
1552 .dependencies = featureSet(&[_]Feature{
1553 .sve2,
1554 .sve_sha3,
1555 }),
1556 };
1557 result[@backingInt(Feature.sve2_sm4)] = .{
1558 .llvm_name = "sve2-sm4",
1559 .description = "Shorthand for +sve2+sve-sm4",
1560 .dependencies = featureSet(&[_]Feature{
1561 .sve2,
1562 .sve_sm4,
1563 }),
1564 };
1565 result[@backingInt(Feature.sve2p1)] = .{
1566 .llvm_name = "sve2p1",
1567 .description = "Enable Scalable Vector Extension 2.1 instructions",
1568 .dependencies = featureSet(&[_]Feature{
1569 .sve2,
1570 }),
1571 };
1572 result[@backingInt(Feature.sve2p2)] = .{
1573 .llvm_name = "sve2p2",
1574 .description = "Enable Armv9.6-A Scalable Vector Extension 2.2 instructions",
1575 .dependencies = featureSet(&[_]Feature{
1576 .sve2p1,
1577 }),
1578 };
1579 result[@backingInt(Feature.sve2p3)] = .{
1580 .llvm_name = "sve2p3",
1581 .description = "Enable Armv9.7-A Scalable Vector Extension 2.3 instructions",
1582 .dependencies = featureSet(&[_]Feature{
1583 .sve2p2,
1584 }),
1585 };
1586 result[@backingInt(Feature.sve_aes)] = .{
1587 .llvm_name = "sve-aes",
1588 .description = "Enable SVE AES and quadword SVE polynomial multiply instructions",
1589 .dependencies = featureSet(&[_]Feature{
1590 .aes,
1591 }),
1592 };
1593 result[@backingInt(Feature.sve_aes2)] = .{
1594 .llvm_name = "sve-aes2",
1595 .description = "Enable Armv9.6-A SVE multi-vector AES and multi-vector quadword polynomial multiply instructions",
1596 .dependencies = featureSet(&[_]Feature{}),
1597 };
1598 result[@backingInt(Feature.sve_b16b16)] = .{
1599 .llvm_name = "sve-b16b16",
1600 .description = "Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions",
1601 .dependencies = featureSet(&[_]Feature{}),
1602 };
1603 result[@backingInt(Feature.sve_b16mm)] = .{
1604 .llvm_name = "sve-b16mm",
1605 .description = "Enable Armv9.7-A SVE non-widening BFloat16 matrix multiply-accumulate",
1606 .dependencies = featureSet(&[_]Feature{
1607 .sve,
1608 }),
1609 };
1610 result[@backingInt(Feature.sve_bfscale)] = .{
1611 .llvm_name = "sve-bfscale",
1612 .description = "Enable Armv9.6-A SVE BFloat16 scaling instructions",
1613 .dependencies = featureSet(&[_]Feature{}),
1614 };
1615 result[@backingInt(Feature.sve_bitperm)] = .{
1616 .llvm_name = "sve-bitperm",
1617 .description = "Enable bit permutation SVE2 instructions",
1618 .dependencies = featureSet(&[_]Feature{}),
1619 };
1620 result[@backingInt(Feature.sve_f16f32mm)] = .{
1621 .llvm_name = "sve-f16f32mm",
1622 .description = "Enable Armv9.6-A FP16 to FP32 Matrix Multiply instructions",
1623 .dependencies = featureSet(&[_]Feature{
1624 .sve,
1625 }),
1626 };
1627 result[@backingInt(Feature.sve_sha3)] = .{
1628 .llvm_name = "sve-sha3",
1629 .description = "Enable SVE SHA3 instructions",
1630 .dependencies = featureSet(&[_]Feature{
1631 .sha3,
1632 }),
1633 };
1634 result[@backingInt(Feature.sve_sm4)] = .{
1635 .llvm_name = "sve-sm4",
1636 .description = "Enable SVE SM4 instructions",
1637 .dependencies = featureSet(&[_]Feature{
1638 .sm4,
1639 }),
1640 };
1641 result[@backingInt(Feature.tagged_globals)] = .{
1642 .llvm_name = "tagged-globals",
1643 .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
1644 .dependencies = featureSet(&[_]Feature{}),
1645 };
1646 result[@backingInt(Feature.tev)] = .{
1647 .llvm_name = "tev",
1648 .description = "Enable TIndex Exception-like Vector instructions",
1649 .dependencies = featureSet(&[_]Feature{}),
1650 };
1651 result[@backingInt(Feature.the)] = .{
1652 .llvm_name = "the",
1653 .description = "Enable Armv8.9-A Translation Hardening Extension",
1654 .dependencies = featureSet(&[_]Feature{}),
1655 };
1656 result[@backingInt(Feature.tlb_rmi)] = .{
1657 .llvm_name = "tlb-rmi",
1658 .description = "Enable Armv8.4-A TLB Range and Maintenance instructions",
1659 .dependencies = featureSet(&[_]Feature{}),
1660 };
1661 result[@backingInt(Feature.tlbid)] = .{
1662 .llvm_name = "tlbid",
1663 .description = "Enable Armv9.7-A TLBI Domains extension",
1664 .dependencies = featureSet(&[_]Feature{}),
1665 };
1666 result[@backingInt(Feature.tlbiw)] = .{
1667 .llvm_name = "tlbiw",
1668 .description = "Enable Armv9.5-A TLBI VMALL for Dirty State",
1669 .dependencies = featureSet(&[_]Feature{}),
1670 };
1671 result[@backingInt(Feature.tpidr_el1)] = .{
1672 .llvm_name = "tpidr-el1",
1673 .description = "Permit use of TPIDR_EL1 for the TLS base",
1674 .dependencies = featureSet(&[_]Feature{}),
1675 };
1676 result[@backingInt(Feature.tpidr_el2)] = .{
1677 .llvm_name = "tpidr-el2",
1678 .description = "Permit use of TPIDR_EL2 for the TLS base",
1679 .dependencies = featureSet(&[_]Feature{}),
1680 };
1681 result[@backingInt(Feature.tpidr_el3)] = .{
1682 .llvm_name = "tpidr-el3",
1683 .description = "Permit use of TPIDR_EL3 for the TLS base",
1684 .dependencies = featureSet(&[_]Feature{}),
1685 };
1686 result[@backingInt(Feature.tpidrro_el0)] = .{
1687 .llvm_name = "tpidrro-el0",
1688 .description = "Permit use of TPIDRRO_EL0 for the TLS base",
1689 .dependencies = featureSet(&[_]Feature{}),
1690 };
1691 result[@backingInt(Feature.tracev8_4)] = .{
1692 .llvm_name = "tracev8.4",
1693 .description = "Enable Armv8.4-A Trace extension",
1694 .dependencies = featureSet(&[_]Feature{}),
1695 };
1696 result[@backingInt(Feature.trbe)] = .{
1697 .llvm_name = "trbe",
1698 .description = "Enable Trace Buffer Extension",
1699 .dependencies = featureSet(&[_]Feature{}),
1700 };
1701 result[@backingInt(Feature.uaops)] = .{
1702 .llvm_name = "uaops",
1703 .description = "Enable Armv8.2-A UAO PState",
1704 .dependencies = featureSet(&[_]Feature{}),
1705 };
1706 result[@backingInt(Feature.use_experimental_zeroing_pseudos)] = .{
1707 .llvm_name = "use-experimental-zeroing-pseudos",
1708 .description = "Hint to the compiler that the MOVPRFX instruction is merged with destructive operations",
1709 .dependencies = featureSet(&[_]Feature{}),
1710 };
1711 result[@backingInt(Feature.use_fixed_over_scalable_if_equal_cost)] = .{
1712 .llvm_name = "use-fixed-over-scalable-if-equal-cost",
1713 .description = "Prefer fixed width loop vectorization over scalable if the cost-model assigns equal costs",
1714 .dependencies = featureSet(&[_]Feature{}),
1715 };
1716 result[@backingInt(Feature.use_postra_scheduler)] = .{
1717 .llvm_name = "use-postra-scheduler",
1718 .description = "Schedule again after register allocation",
1719 .dependencies = featureSet(&[_]Feature{}),
1720 };
1721 result[@backingInt(Feature.use_reciprocal_square_root)] = .{
1722 .llvm_name = "use-reciprocal-square-root",
1723 .description = "Use the reciprocal square root approximation",
1724 .dependencies = featureSet(&[_]Feature{}),
1725 };
1726 result[@backingInt(Feature.use_wzr_to_vec_move)] = .{
1727 .llvm_name = "use-wzr-to-vec-move",
1728 .description = "Move from WZR to insert 0 into vector registers",
1729 .dependencies = featureSet(&[_]Feature{}),
1730 };
1731 result[@backingInt(Feature.v8_1a)] = .{
1732 .llvm_name = "v8.1a",
1733 .description = "Support ARM v8.1a architecture",
1734 .dependencies = featureSet(&[_]Feature{
1735 .crc,
1736 .lor,
1737 .lse,
1738 .pan,
1739 .rdm,
1740 .v8a,
1741 .vh,
1742 }),
1743 };
1744 result[@backingInt(Feature.v8_2a)] = .{
1745 .llvm_name = "v8.2a",
1746 .description = "Support ARM v8.2a architecture",
1747 .dependencies = featureSet(&[_]Feature{
1748 .ccpp,
1749 .pan_rwv,
1750 .ras,
1751 .uaops,
1752 .v8_1a,
1753 }),
1754 };
1755 result[@backingInt(Feature.v8_3a)] = .{
1756 .llvm_name = "v8.3a",
1757 .description = "Support ARM v8.3a architecture",
1758 .dependencies = featureSet(&[_]Feature{
1759 .ccidx,
1760 .complxnum,
1761 .jsconv,
1762 .pauth,
1763 .rcpc,
1764 .v8_2a,
1765 }),
1766 };
1767 result[@backingInt(Feature.v8_4a)] = .{
1768 .llvm_name = "v8.4a",
1769 .description = "Support ARM v8.4a architecture",
1770 .dependencies = featureSet(&[_]Feature{
1771 .am,
1772 .dit,
1773 .dotprod,
1774 .flagm,
1775 .lse2,
1776 .mpam,
1777 .nv,
1778 .rcpc_immo,
1779 .sel2,
1780 .tlb_rmi,
1781 .tracev8_4,
1782 .v8_3a,
1783 }),
1784 };
1785 result[@backingInt(Feature.v8_5a)] = .{
1786 .llvm_name = "v8.5a",
1787 .description = "Support ARM v8.5a architecture",
1788 .dependencies = featureSet(&[_]Feature{
1789 .altnzcv,
1790 .bti,
1791 .ccdp,
1792 .fptoint,
1793 .predres,
1794 .sb,
1795 .specrestrict,
1796 .ssbs,
1797 .v8_4a,
1798 }),
1799 };
1800 result[@backingInt(Feature.v8_6a)] = .{
1801 .llvm_name = "v8.6a",
1802 .description = "Support ARM v8.6a architecture",
1803 .dependencies = featureSet(&[_]Feature{
1804 .amvs,
1805 .bf16,
1806 .ecv,
1807 .fgt,
1808 .i8mm,
1809 .v8_5a,
1810 }),
1811 };
1812 result[@backingInt(Feature.v8_7a)] = .{
1813 .llvm_name = "v8.7a",
1814 .description = "Support ARM v8.7a architecture",
1815 .dependencies = featureSet(&[_]Feature{
1816 .hcx,
1817 .spe_eef,
1818 .v8_6a,
1819 .wfxt,
1820 .xs,
1821 }),
1822 };
1823 result[@backingInt(Feature.v8_8a)] = .{
1824 .llvm_name = "v8.8a",
1825 .description = "Support ARM v8.8a architecture",
1826 .dependencies = featureSet(&[_]Feature{
1827 .hbc,
1828 .mops,
1829 .nmi,
1830 .v8_7a,
1831 }),
1832 };
1833 result[@backingInt(Feature.v8_9a)] = .{
1834 .llvm_name = "v8.9a",
1835 .description = "Support ARM v8.9a architecture",
1836 .dependencies = featureSet(&[_]Feature{
1837 .chk,
1838 .clrbhb,
1839 .cssc,
1840 .prfm_slc_target,
1841 .rasv2,
1842 .specres2,
1843 .v8_8a,
1844 }),
1845 };
1846 result[@backingInt(Feature.v8a)] = .{
1847 .llvm_name = "v8a",
1848 .description = "Support ARM v8a architecture",
1849 .dependencies = featureSet(&[_]Feature{
1850 .el2vmsa,
1851 .el3,
1852 .neon,
1853 }),
1854 };
1855 result[@backingInt(Feature.v8r)] = .{
1856 .llvm_name = "v8r",
1857 .description = "Support ARM v8r architecture",
1858 .dependencies = featureSet(&[_]Feature{
1859 .ccidx,
1860 .ccpp,
1861 .complxnum,
1862 .contextidr_el2,
1863 .crc,
1864 .dit,
1865 .dotprod,
1866 .flagm,
1867 .fp16fml,
1868 .jsconv,
1869 .lse,
1870 .pan_rwv,
1871 .pauth,
1872 .ras,
1873 .rcpc_immo,
1874 .rdm,
1875 .sb,
1876 .sel2,
1877 .specrestrict,
1878 .ssbs,
1879 .tlb_rmi,
1880 .tracev8_4,
1881 .uaops,
1882 }),
1883 };
1884 result[@backingInt(Feature.v9_1a)] = .{
1885 .llvm_name = "v9.1a",
1886 .description = "Support ARM v9.1a architecture",
1887 .dependencies = featureSet(&[_]Feature{
1888 .rme,
1889 .v8_6a,
1890 .v9a,
1891 }),
1892 };
1893 result[@backingInt(Feature.v9_2a)] = .{
1894 .llvm_name = "v9.2a",
1895 .description = "Support ARM v9.2a architecture",
1896 .dependencies = featureSet(&[_]Feature{
1897 .mec,
1898 .v8_7a,
1899 .v9_1a,
1900 }),
1901 };
1902 result[@backingInt(Feature.v9_3a)] = .{
1903 .llvm_name = "v9.3a",
1904 .description = "Support ARM v9.3a architecture",
1905 .dependencies = featureSet(&[_]Feature{
1906 .v8_8a,
1907 .v9_2a,
1908 }),
1909 };
1910 result[@backingInt(Feature.v9_4a)] = .{
1911 .llvm_name = "v9.4a",
1912 .description = "Support ARM v9.4a architecture",
1913 .dependencies = featureSet(&[_]Feature{
1914 .sve2p1,
1915 .v8_9a,
1916 .v9_3a,
1917 }),
1918 };
1919 result[@backingInt(Feature.v9_5a)] = .{
1920 .llvm_name = "v9.5a",
1921 .description = "Support ARM v9.5a architecture",
1922 .dependencies = featureSet(&[_]Feature{
1923 .cpa,
1924 .faminmax,
1925 .lut,
1926 .v9_4a,
1927 }),
1928 };
1929 result[@backingInt(Feature.v9_6a)] = .{
1930 .llvm_name = "v9.6a",
1931 .description = "Support ARM v9.6a architecture",
1932 .dependencies = featureSet(&[_]Feature{
1933 .cmpbr,
1934 .lsui,
1935 .occmo,
1936 .v9_5a,
1937 }),
1938 };
1939 result[@backingInt(Feature.v9_7a)] = .{
1940 .llvm_name = "v9.7a",
1941 .description = "Support ARM v9.7a architecture",
1942 .dependencies = featureSet(&[_]Feature{
1943 .f16f32dot,
1944 .fprcvt,
1945 .sve2p3,
1946 .v9_6a,
1947 }),
1948 };
1949 result[@backingInt(Feature.v9a)] = .{
1950 .llvm_name = "v9a",
1951 .description = "Support ARM v9a architecture",
1952 .dependencies = featureSet(&[_]Feature{
1953 .sve2,
1954 .v8_5a,
1955 }),
1956 };
1957 result[@backingInt(Feature.vh)] = .{
1958 .llvm_name = "vh",
1959 .description = "Enable Armv8.1-A Virtual Host extension",
1960 .dependencies = featureSet(&[_]Feature{
1961 .contextidr_el2,
1962 }),
1963 };
1964 result[@backingInt(Feature.wfxt)] = .{
1965 .llvm_name = "wfxt",
1966 .description = "Enable Armv8.7-A WFET and WFIT instruction",
1967 .dependencies = featureSet(&[_]Feature{}),
1968 };
1969 result[@backingInt(Feature.xs)] = .{
1970 .llvm_name = "xs",
1971 .description = "Enable Armv8.7-A limited-TLB-maintenance instruction",
1972 .dependencies = featureSet(&[_]Feature{}),
1973 };
1974 result[@backingInt(Feature.zcm_fpr128)] = .{
1975 .llvm_name = "zcm-fpr128",
1976 .description = "Has zero-cycle register moves for FPR128 registers",
1977 .dependencies = featureSet(&[_]Feature{}),
1978 };
1979 result[@backingInt(Feature.zcm_fpr32)] = .{
1980 .llvm_name = "zcm-fpr32",
1981 .description = "Has zero-cycle register moves for FPR32 registers",
1982 .dependencies = featureSet(&[_]Feature{}),
1983 };
1984 result[@backingInt(Feature.zcm_fpr64)] = .{
1985 .llvm_name = "zcm-fpr64",
1986 .description = "Has zero-cycle register moves for FPR64 registers",
1987 .dependencies = featureSet(&[_]Feature{}),
1988 };
1989 result[@backingInt(Feature.zcm_gpr32)] = .{
1990 .llvm_name = "zcm-gpr32",
1991 .description = "Has zero-cycle register moves for GPR32 registers",
1992 .dependencies = featureSet(&[_]Feature{}),
1993 };
1994 result[@backingInt(Feature.zcm_gpr64)] = .{
1995 .llvm_name = "zcm-gpr64",
1996 .description = "Has zero-cycle register moves for GPR64 registers",
1997 .dependencies = featureSet(&[_]Feature{}),
1998 };
1999 result[@backingInt(Feature.zcz_fp_workaround)] = .{
2000 .llvm_name = "zcz-fp-workaround",
2001 .description = "The zero-cycle floating-point zeroing instruction has a bug",
2002 .dependencies = featureSet(&[_]Feature{}),
2003 };
2004 result[@backingInt(Feature.zcz_fpr128)] = .{
2005 .llvm_name = "zcz-fpr128",
2006 .description = "Has zero-cycle zeroing instructions for FPR128 registers",
2007 .dependencies = featureSet(&[_]Feature{}),
2008 };
2009 result[@backingInt(Feature.zcz_gpr32)] = .{
2010 .llvm_name = "zcz-gpr32",
2011 .description = "Has zero-cycle zeroing instructions for GPR32 registers",
2012 .dependencies = featureSet(&[_]Feature{}),
2013 };
2014 result[@backingInt(Feature.zcz_gpr64)] = .{
2015 .llvm_name = "zcz-gpr64",
2016 .description = "Has zero-cycle zeroing instructions for GPR64 registers",
2017 .dependencies = featureSet(&[_]Feature{}),
2018 };
2019 const ti = @typeInfo(Feature);
2020 for (&result, 0..) |*elem, i| {
2021 elem.index = i;
2022 elem.name = ti.@"enum".field_names[i];
2023 }
2024 break :blk result;
2025};
2026
2027pub const cpu = struct {
2028 pub const a64fx: CpuModel = .{
2029 .name = "a64fx",
2030 .llvm_name = "a64fx",
2031 .features = featureSet(&[_]Feature{
2032 .aes,
2033 .aggressive_fma,
2034 .arith_bcc_fusion,
2035 .complxnum,
2036 .disable_unpredicated_ld_st_lower,
2037 .max_interleave_factor_4,
2038 .perfmon,
2039 .predictable_select_expensive,
2040 .sha2,
2041 .store_pair_suppress,
2042 .sve,
2043 .use_postra_scheduler,
2044 .v8_2a,
2045 }),
2046 };
2047 pub const ampere1: CpuModel = .{
2048 .name = "ampere1",
2049 .llvm_name = "ampere1",
2050 .features = featureSet(&[_]Feature{
2051 .aes,
2052 .aggressive_fma,
2053 .alu_lsl_fast,
2054 .arith_bcc_fusion,
2055 .cmp_bcc_fusion,
2056 .fullfp16,
2057 .fuse_address,
2058 .fuse_adrp_add,
2059 .fuse_aes,
2060 .fuse_literals,
2061 .ldp_aligned_only,
2062 .max_interleave_factor_4,
2063 .perfmon,
2064 .rand,
2065 .sha3,
2066 .store_pair_suppress,
2067 .stp_aligned_only,
2068 .use_postra_scheduler,
2069 .v8_6a,
2070 }),
2071 };
2072 pub const ampere1a: CpuModel = .{
2073 .name = "ampere1a",
2074 .llvm_name = "ampere1a",
2075 .features = featureSet(&[_]Feature{
2076 .aes,
2077 .aggressive_fma,
2078 .alu_lsl_fast,
2079 .arith_bcc_fusion,
2080 .cmp_bcc_fusion,
2081 .fullfp16,
2082 .fuse_address,
2083 .fuse_addsub_2reg_const1,
2084 .fuse_adrp_add,
2085 .fuse_aes,
2086 .fuse_literals,
2087 .ldp_aligned_only,
2088 .max_interleave_factor_4,
2089 .mte,
2090 .perfmon,
2091 .rand,
2092 .sha3,
2093 .sm4,
2094 .store_pair_suppress,
2095 .stp_aligned_only,
2096 .use_postra_scheduler,
2097 .v8_6a,
2098 }),
2099 };
2100 pub const ampere1b: CpuModel = .{
2101 .name = "ampere1b",
2102 .llvm_name = "ampere1b",
2103 .features = featureSet(&[_]Feature{
2104 .aes,
2105 .aggressive_fma,
2106 .alu_lsl_fast,
2107 .arith_bcc_fusion,
2108 .cmp_bcc_fusion,
2109 .cssc,
2110 .enable_select_opt,
2111 .fullfp16,
2112 .fuse_address,
2113 .fuse_adrp_add,
2114 .fuse_aes,
2115 .fuse_literals,
2116 .ldp_aligned_only,
2117 .max_interleave_factor_4,
2118 .mte,
2119 .perfmon,
2120 .predictable_select_expensive,
2121 .rand,
2122 .sha3,
2123 .sm4,
2124 .store_pair_suppress,
2125 .stp_aligned_only,
2126 .use_postra_scheduler,
2127 .v8_7a,
2128 }),
2129 };
2130 pub const ampere1c: CpuModel = .{
2131 .name = "ampere1c",
2132 .llvm_name = "ampere1c",
2133 .features = featureSet(&[_]Feature{
2134 .aggressive_fma,
2135 .alu_lsl_fast,
2136 .arith_bcc_fusion,
2137 .cmp_bcc_fusion,
2138 .cssc,
2139 .enable_select_opt,
2140 .faminmax,
2141 .fp16fml,
2142 .fp8fma,
2143 .fuse_address,
2144 .fuse_adrp_add,
2145 .fuse_aes,
2146 .fuse_literals,
2147 .lut,
2148 .max_interleave_factor_4,
2149 .mte,
2150 .perfmon,
2151 .predictable_select_expensive,
2152 .rand,
2153 .store_pair_suppress,
2154 .sve_aes,
2155 .sve_b16b16,
2156 .sve_sha3,
2157 .sve_sm4,
2158 .use_postra_scheduler,
2159 .v9_2a,
2160 }),
2161 };
2162 pub const apple_a10: CpuModel = .{
2163 .name = "apple_a10",
2164 .llvm_name = "apple-a10",
2165 .features = featureSet(&[_]Feature{
2166 .aes,
2167 .alternate_sextload_cvt_f32_pattern,
2168 .arith_bcc_fusion,
2169 .arith_cbz_fusion,
2170 .crc,
2171 .disable_latency_sched_heuristic,
2172 .fuse_aes,
2173 .fuse_crypto_eor,
2174 .lor,
2175 .no_zcz_fpr64,
2176 .pan,
2177 .perfmon,
2178 .rdm,
2179 .sha2,
2180 .store_pair_suppress,
2181 .v8a,
2182 .vh,
2183 .zcm_fpr128,
2184 .zcm_gpr64,
2185 .zcz_fpr128,
2186 .zcz_gpr32,
2187 .zcz_gpr64,
2188 }),
2189 };
2190 pub const apple_a11: CpuModel = .{
2191 .name = "apple_a11",
2192 .llvm_name = "apple-a11",
2193 .features = featureSet(&[_]Feature{
2194 .aes,
2195 .alternate_sextload_cvt_f32_pattern,
2196 .arith_bcc_fusion,
2197 .arith_cbz_fusion,
2198 .disable_latency_sched_heuristic,
2199 .fullfp16,
2200 .fuse_aes,
2201 .fuse_crypto_eor,
2202 .no_zcz_fpr64,
2203 .perfmon,
2204 .sha2,
2205 .store_pair_suppress,
2206 .v8_2a,
2207 .zcm_fpr128,
2208 .zcm_gpr64,
2209 .zcz_fpr128,
2210 .zcz_gpr32,
2211 .zcz_gpr64,
2212 }),
2213 };
2214 pub const apple_a12: CpuModel = .{
2215 .name = "apple_a12",
2216 .llvm_name = "apple-a12",
2217 .features = featureSet(&[_]Feature{
2218 .aes,
2219 .alternate_sextload_cvt_f32_pattern,
2220 .arith_bcc_fusion,
2221 .arith_cbz_fusion,
2222 .disable_latency_sched_heuristic,
2223 .fullfp16,
2224 .fuse_aes,
2225 .fuse_crypto_eor,
2226 .no_zcz_fpr64,
2227 .perfmon,
2228 .sha2,
2229 .store_pair_suppress,
2230 .v8_3a,
2231 .zcm_fpr128,
2232 .zcm_gpr64,
2233 .zcz_fpr128,
2234 .zcz_gpr32,
2235 .zcz_gpr64,
2236 }),
2237 };
2238 pub const apple_a13: CpuModel = .{
2239 .name = "apple_a13",
2240 .llvm_name = "apple-a13",
2241 .features = featureSet(&[_]Feature{
2242 .aes,
2243 .alternate_sextload_cvt_f32_pattern,
2244 .arith_bcc_fusion,
2245 .arith_cbz_fusion,
2246 .disable_latency_sched_heuristic,
2247 .fp16fml,
2248 .fuse_aes,
2249 .fuse_crypto_eor,
2250 .no_zcz_fpr64,
2251 .perfmon,
2252 .sha3,
2253 .store_pair_suppress,
2254 .v8_4a,
2255 .zcm_fpr128,
2256 .zcm_gpr64,
2257 .zcz_fpr128,
2258 .zcz_gpr32,
2259 .zcz_gpr64,
2260 }),
2261 };
2262 pub const apple_a14: CpuModel = .{
2263 .name = "apple_a14",
2264 .llvm_name = "apple-a14",
2265 .features = featureSet(&[_]Feature{
2266 .aes,
2267 .aggressive_fma,
2268 .alternate_sextload_cvt_f32_pattern,
2269 .altnzcv,
2270 .arith_bcc_fusion,
2271 .arith_cbz_fusion,
2272 .ccdp,
2273 .disable_latency_sched_heuristic,
2274 .fp16fml,
2275 .fptoint,
2276 .fuse_address,
2277 .fuse_aes,
2278 .fuse_arith_logic,
2279 .fuse_crypto_eor,
2280 .fuse_csel,
2281 .fuse_literals,
2282 .max_interleave_factor_4,
2283 .no_zcz_fpr64,
2284 .perfmon,
2285 .predres,
2286 .sb,
2287 .sha3,
2288 .specrestrict,
2289 .ssbs,
2290 .store_pair_suppress,
2291 .v8_4a,
2292 .zcm_fpr128,
2293 .zcm_gpr64,
2294 .zcz_fpr128,
2295 .zcz_gpr32,
2296 .zcz_gpr64,
2297 }),
2298 };
2299 pub const apple_a15: CpuModel = .{
2300 .name = "apple_a15",
2301 .llvm_name = "apple-a15",
2302 .features = featureSet(&[_]Feature{
2303 .aes,
2304 .alternate_sextload_cvt_f32_pattern,
2305 .arith_bcc_fusion,
2306 .arith_cbz_fusion,
2307 .disable_latency_sched_heuristic,
2308 .fp16fml,
2309 .fpac,
2310 .fuse_address,
2311 .fuse_adrp_add,
2312 .fuse_aes,
2313 .fuse_arith_logic,
2314 .fuse_crypto_eor,
2315 .fuse_csel,
2316 .fuse_literals,
2317 .max_interleave_factor_4,
2318 .no_zcz_fpr64,
2319 .perfmon,
2320 .sha3,
2321 .store_pair_suppress,
2322 .v8_6a,
2323 .zcm_fpr128,
2324 .zcm_gpr64,
2325 .zcz_fpr128,
2326 .zcz_gpr32,
2327 .zcz_gpr64,
2328 }),
2329 };
2330 pub const apple_a16: CpuModel = .{
2331 .name = "apple_a16",
2332 .llvm_name = "apple-a16",
2333 .features = featureSet(&[_]Feature{
2334 .aes,
2335 .alternate_sextload_cvt_f32_pattern,
2336 .arith_bcc_fusion,
2337 .arith_cbz_fusion,
2338 .disable_latency_sched_heuristic,
2339 .fp16fml,
2340 .fpac,
2341 .fuse_address,
2342 .fuse_adrp_add,
2343 .fuse_aes,
2344 .fuse_arith_logic,
2345 .fuse_crypto_eor,
2346 .fuse_csel,
2347 .fuse_literals,
2348 .hcx,
2349 .max_interleave_factor_4,
2350 .no_zcz_fpr64,
2351 .perfmon,
2352 .sha3,
2353 .store_pair_suppress,
2354 .v8_6a,
2355 .zcm_fpr128,
2356 .zcm_gpr64,
2357 .zcz_fpr128,
2358 .zcz_gpr32,
2359 .zcz_gpr64,
2360 }),
2361 };
2362 pub const apple_a17: CpuModel = .{
2363 .name = "apple_a17",
2364 .llvm_name = "apple-a17",
2365 .features = featureSet(&[_]Feature{
2366 .aes,
2367 .alternate_sextload_cvt_f32_pattern,
2368 .arith_bcc_fusion,
2369 .arith_cbz_fusion,
2370 .disable_latency_sched_heuristic,
2371 .fp16fml,
2372 .fpac,
2373 .fuse_address,
2374 .fuse_adrp_add,
2375 .fuse_aes,
2376 .fuse_arith_logic,
2377 .fuse_crypto_eor,
2378 .fuse_csel,
2379 .fuse_literals,
2380 .hcx,
2381 .max_interleave_factor_4,
2382 .no_zcz_fpr64,
2383 .perfmon,
2384 .sha3,
2385 .store_pair_suppress,
2386 .v8_6a,
2387 .zcm_fpr128,
2388 .zcm_gpr64,
2389 .zcz_fpr128,
2390 .zcz_gpr32,
2391 .zcz_gpr64,
2392 }),
2393 };
2394 pub const apple_a18: CpuModel = .{
2395 .name = "apple_a18",
2396 .llvm_name = "apple-a18",
2397 .features = featureSet(&[_]Feature{
2398 .aes,
2399 .alternate_sextload_cvt_f32_pattern,
2400 .arith_bcc_fusion,
2401 .arith_cbz_fusion,
2402 .disable_latency_sched_heuristic,
2403 .fp16fml,
2404 .fpac,
2405 .fuse_address,
2406 .fuse_adrp_add,
2407 .fuse_aes,
2408 .fuse_arith_logic,
2409 .fuse_crypto_eor,
2410 .fuse_csel,
2411 .fuse_literals,
2412 .max_interleave_factor_4,
2413 .no_zcz_fpr64,
2414 .perfmon,
2415 .sha3,
2416 .sme2,
2417 .sme_f64f64,
2418 .sme_i16i64,
2419 .v8_7a,
2420 .zcm_fpr128,
2421 .zcm_gpr64,
2422 .zcz_fpr128,
2423 .zcz_gpr32,
2424 .zcz_gpr64,
2425 }),
2426 };
2427 pub const apple_a19: CpuModel = .{
2428 .name = "apple_a19",
2429 .llvm_name = "apple-a19",
2430 .features = featureSet(&[_]Feature{
2431 .aes,
2432 .alternate_sextload_cvt_f32_pattern,
2433 .arith_bcc_fusion,
2434 .arith_cbz_fusion,
2435 .cssc,
2436 .disable_latency_sched_heuristic,
2437 .fp16fml,
2438 .fpac,
2439 .fuse_address,
2440 .fuse_adrp_add,
2441 .fuse_aes,
2442 .fuse_arith_logic,
2443 .fuse_crypto_eor,
2444 .fuse_csel,
2445 .fuse_literals,
2446 .hbc,
2447 .max_interleave_factor_4,
2448 .mte,
2449 .no_zcz_fpr64,
2450 .perfmon,
2451 .sha3,
2452 .sme2p1,
2453 .sme_b16b16,
2454 .sme_f16f16,
2455 .sme_f64f64,
2456 .sme_i16i64,
2457 .specres2,
2458 .v8_7a,
2459 .zcm_fpr128,
2460 .zcm_gpr64,
2461 .zcz_fpr128,
2462 .zcz_gpr32,
2463 .zcz_gpr64,
2464 }),
2465 };
2466 pub const apple_a7: CpuModel = .{
2467 .name = "apple_a7",
2468 .llvm_name = "apple-a7",
2469 .features = featureSet(&[_]Feature{
2470 .aes,
2471 .alternate_sextload_cvt_f32_pattern,
2472 .arith_bcc_fusion,
2473 .arith_cbz_fusion,
2474 .disable_latency_sched_heuristic,
2475 .fuse_aes,
2476 .fuse_crypto_eor,
2477 .no_zcz_fpr64,
2478 .perfmon,
2479 .sha2,
2480 .store_pair_suppress,
2481 .v8a,
2482 .zcm_fpr128,
2483 .zcm_gpr64,
2484 .zcz_fp_workaround,
2485 .zcz_fpr128,
2486 .zcz_gpr32,
2487 .zcz_gpr64,
2488 }),
2489 };
2490 pub const apple_a8: CpuModel = .{
2491 .name = "apple_a8",
2492 .llvm_name = "apple-a8",
2493 .features = featureSet(&[_]Feature{
2494 .aes,
2495 .alternate_sextload_cvt_f32_pattern,
2496 .arith_bcc_fusion,
2497 .arith_cbz_fusion,
2498 .disable_latency_sched_heuristic,
2499 .fuse_aes,
2500 .fuse_crypto_eor,
2501 .no_zcz_fpr64,
2502 .perfmon,
2503 .sha2,
2504 .store_pair_suppress,
2505 .v8a,
2506 .zcm_fpr128,
2507 .zcm_gpr64,
2508 .zcz_fp_workaround,
2509 .zcz_fpr128,
2510 .zcz_gpr32,
2511 .zcz_gpr64,
2512 }),
2513 };
2514 pub const apple_a9: CpuModel = .{
2515 .name = "apple_a9",
2516 .llvm_name = "apple-a9",
2517 .features = featureSet(&[_]Feature{
2518 .aes,
2519 .alternate_sextload_cvt_f32_pattern,
2520 .arith_bcc_fusion,
2521 .arith_cbz_fusion,
2522 .disable_latency_sched_heuristic,
2523 .fuse_aes,
2524 .fuse_crypto_eor,
2525 .no_zcz_fpr64,
2526 .perfmon,
2527 .sha2,
2528 .store_pair_suppress,
2529 .v8a,
2530 .zcm_fpr128,
2531 .zcm_gpr64,
2532 .zcz_fp_workaround,
2533 .zcz_fpr128,
2534 .zcz_gpr32,
2535 .zcz_gpr64,
2536 }),
2537 };
2538 pub const apple_m1: CpuModel = .{
2539 .name = "apple_m1",
2540 .llvm_name = "apple-m1",
2541 .features = featureSet(&[_]Feature{
2542 .aes,
2543 .aggressive_fma,
2544 .alternate_sextload_cvt_f32_pattern,
2545 .altnzcv,
2546 .arith_bcc_fusion,
2547 .arith_cbz_fusion,
2548 .ccdp,
2549 .disable_latency_sched_heuristic,
2550 .fp16fml,
2551 .fptoint,
2552 .fuse_address,
2553 .fuse_aes,
2554 .fuse_arith_logic,
2555 .fuse_crypto_eor,
2556 .fuse_csel,
2557 .fuse_literals,
2558 .max_interleave_factor_4,
2559 .no_zcz_fpr64,
2560 .perfmon,
2561 .predres,
2562 .sb,
2563 .sha3,
2564 .specrestrict,
2565 .ssbs,
2566 .store_pair_suppress,
2567 .v8_4a,
2568 .zcm_fpr128,
2569 .zcm_gpr64,
2570 .zcz_fpr128,
2571 .zcz_gpr32,
2572 .zcz_gpr64,
2573 }),
2574 };
2575 pub const apple_m2: CpuModel = .{
2576 .name = "apple_m2",
2577 .llvm_name = "apple-m2",
2578 .features = featureSet(&[_]Feature{
2579 .aes,
2580 .alternate_sextload_cvt_f32_pattern,
2581 .arith_bcc_fusion,
2582 .arith_cbz_fusion,
2583 .disable_latency_sched_heuristic,
2584 .fp16fml,
2585 .fpac,
2586 .fuse_address,
2587 .fuse_adrp_add,
2588 .fuse_aes,
2589 .fuse_arith_logic,
2590 .fuse_crypto_eor,
2591 .fuse_csel,
2592 .fuse_literals,
2593 .max_interleave_factor_4,
2594 .no_zcz_fpr64,
2595 .perfmon,
2596 .sha3,
2597 .store_pair_suppress,
2598 .v8_6a,
2599 .zcm_fpr128,
2600 .zcm_gpr64,
2601 .zcz_fpr128,
2602 .zcz_gpr32,
2603 .zcz_gpr64,
2604 }),
2605 };
2606 pub const apple_m3: CpuModel = .{
2607 .name = "apple_m3",
2608 .llvm_name = "apple-m3",
2609 .features = featureSet(&[_]Feature{
2610 .aes,
2611 .alternate_sextload_cvt_f32_pattern,
2612 .arith_bcc_fusion,
2613 .arith_cbz_fusion,
2614 .disable_latency_sched_heuristic,
2615 .fp16fml,
2616 .fpac,
2617 .fuse_address,
2618 .fuse_adrp_add,
2619 .fuse_aes,
2620 .fuse_arith_logic,
2621 .fuse_crypto_eor,
2622 .fuse_csel,
2623 .fuse_literals,
2624 .hcx,
2625 .max_interleave_factor_4,
2626 .no_zcz_fpr64,
2627 .perfmon,
2628 .sha3,
2629 .store_pair_suppress,
2630 .v8_6a,
2631 .zcm_fpr128,
2632 .zcm_gpr64,
2633 .zcz_fpr128,
2634 .zcz_gpr32,
2635 .zcz_gpr64,
2636 }),
2637 };
2638 pub const apple_m4: CpuModel = .{
2639 .name = "apple_m4",
2640 .llvm_name = "apple-m4",
2641 .features = featureSet(&[_]Feature{
2642 .aes,
2643 .alternate_sextload_cvt_f32_pattern,
2644 .arith_bcc_fusion,
2645 .arith_cbz_fusion,
2646 .disable_latency_sched_heuristic,
2647 .fp16fml,
2648 .fpac,
2649 .fuse_address,
2650 .fuse_adrp_add,
2651 .fuse_aes,
2652 .fuse_arith_logic,
2653 .fuse_crypto_eor,
2654 .fuse_csel,
2655 .fuse_literals,
2656 .max_interleave_factor_4,
2657 .no_zcz_fpr64,
2658 .perfmon,
2659 .sha3,
2660 .sme2,
2661 .sme_f64f64,
2662 .sme_i16i64,
2663 .v8_7a,
2664 .zcm_fpr128,
2665 .zcm_gpr64,
2666 .zcz_fpr128,
2667 .zcz_gpr32,
2668 .zcz_gpr64,
2669 }),
2670 };
2671 pub const apple_m5: CpuModel = .{
2672 .name = "apple_m5",
2673 .llvm_name = "apple-m5",
2674 .features = featureSet(&[_]Feature{
2675 .aes,
2676 .alternate_sextload_cvt_f32_pattern,
2677 .arith_bcc_fusion,
2678 .arith_cbz_fusion,
2679 .cssc,
2680 .disable_latency_sched_heuristic,
2681 .fp16fml,
2682 .fpac,
2683 .fuse_address,
2684 .fuse_adrp_add,
2685 .fuse_aes,
2686 .fuse_arith_logic,
2687 .fuse_crypto_eor,
2688 .fuse_csel,
2689 .fuse_literals,
2690 .hbc,
2691 .max_interleave_factor_4,
2692 .mte,
2693 .no_zcz_fpr64,
2694 .perfmon,
2695 .sha3,
2696 .sme2p1,
2697 .sme_b16b16,
2698 .sme_f16f16,
2699 .sme_f64f64,
2700 .sme_i16i64,
2701 .specres2,
2702 .v8_7a,
2703 .zcm_fpr128,
2704 .zcm_gpr64,
2705 .zcz_fpr128,
2706 .zcz_gpr32,
2707 .zcz_gpr64,
2708 }),
2709 };
2710 pub const apple_s10: CpuModel = .{
2711 .name = "apple_s10",
2712 .llvm_name = "apple-s10",
2713 .features = featureSet(&[_]Feature{
2714 .aes,
2715 .alternate_sextload_cvt_f32_pattern,
2716 .arith_bcc_fusion,
2717 .arith_cbz_fusion,
2718 .disable_latency_sched_heuristic,
2719 .fp16fml,
2720 .fpac,
2721 .fuse_address,
2722 .fuse_adrp_add,
2723 .fuse_aes,
2724 .fuse_arith_logic,
2725 .fuse_crypto_eor,
2726 .fuse_csel,
2727 .fuse_literals,
2728 .hcx,
2729 .max_interleave_factor_4,
2730 .no_zcz_fpr64,
2731 .perfmon,
2732 .sha3,
2733 .store_pair_suppress,
2734 .v8_6a,
2735 .zcm_fpr128,
2736 .zcm_gpr64,
2737 .zcz_fpr128,
2738 .zcz_gpr32,
2739 .zcz_gpr64,
2740 }),
2741 };
2742 pub const apple_s4: CpuModel = .{
2743 .name = "apple_s4",
2744 .llvm_name = "apple-s4",
2745 .features = featureSet(&[_]Feature{
2746 .aes,
2747 .alternate_sextload_cvt_f32_pattern,
2748 .arith_bcc_fusion,
2749 .arith_cbz_fusion,
2750 .disable_latency_sched_heuristic,
2751 .fullfp16,
2752 .fuse_aes,
2753 .fuse_crypto_eor,
2754 .no_zcz_fpr64,
2755 .perfmon,
2756 .sha2,
2757 .store_pair_suppress,
2758 .v8_3a,
2759 .zcm_fpr128,
2760 .zcm_gpr64,
2761 .zcz_fpr128,
2762 .zcz_gpr32,
2763 .zcz_gpr64,
2764 }),
2765 };
2766 pub const apple_s5: CpuModel = .{
2767 .name = "apple_s5",
2768 .llvm_name = "apple-s5",
2769 .features = featureSet(&[_]Feature{
2770 .aes,
2771 .alternate_sextload_cvt_f32_pattern,
2772 .arith_bcc_fusion,
2773 .arith_cbz_fusion,
2774 .disable_latency_sched_heuristic,
2775 .fullfp16,
2776 .fuse_aes,
2777 .fuse_crypto_eor,
2778 .no_zcz_fpr64,
2779 .perfmon,
2780 .sha2,
2781 .store_pair_suppress,
2782 .v8_3a,
2783 .zcm_fpr128,
2784 .zcm_gpr64,
2785 .zcz_fpr128,
2786 .zcz_gpr32,
2787 .zcz_gpr64,
2788 }),
2789 };
2790 pub const apple_s6: CpuModel = .{
2791 .name = "apple_s6",
2792 .llvm_name = "apple-s6",
2793 .features = featureSet(&[_]Feature{
2794 .aes,
2795 .alternate_sextload_cvt_f32_pattern,
2796 .arith_bcc_fusion,
2797 .arith_cbz_fusion,
2798 .disable_latency_sched_heuristic,
2799 .fp16fml,
2800 .fuse_aes,
2801 .fuse_crypto_eor,
2802 .no_zcz_fpr64,
2803 .perfmon,
2804 .sha3,
2805 .store_pair_suppress,
2806 .v8_4a,
2807 .zcm_fpr128,
2808 .zcm_gpr64,
2809 .zcz_fpr128,
2810 .zcz_gpr32,
2811 .zcz_gpr64,
2812 }),
2813 };
2814 pub const apple_s7: CpuModel = .{
2815 .name = "apple_s7",
2816 .llvm_name = "apple-s7",
2817 .features = featureSet(&[_]Feature{
2818 .aes,
2819 .alternate_sextload_cvt_f32_pattern,
2820 .arith_bcc_fusion,
2821 .arith_cbz_fusion,
2822 .disable_latency_sched_heuristic,
2823 .fp16fml,
2824 .fuse_aes,
2825 .fuse_crypto_eor,
2826 .no_zcz_fpr64,
2827 .perfmon,
2828 .sha3,
2829 .store_pair_suppress,
2830 .v8_4a,
2831 .zcm_fpr128,
2832 .zcm_gpr64,
2833 .zcz_fpr128,
2834 .zcz_gpr32,
2835 .zcz_gpr64,
2836 }),
2837 };
2838 pub const apple_s8: CpuModel = .{
2839 .name = "apple_s8",
2840 .llvm_name = "apple-s8",
2841 .features = featureSet(&[_]Feature{
2842 .aes,
2843 .alternate_sextload_cvt_f32_pattern,
2844 .arith_bcc_fusion,
2845 .arith_cbz_fusion,
2846 .disable_latency_sched_heuristic,
2847 .fp16fml,
2848 .fuse_aes,
2849 .fuse_crypto_eor,
2850 .no_zcz_fpr64,
2851 .perfmon,
2852 .sha3,
2853 .store_pair_suppress,
2854 .v8_4a,
2855 .zcm_fpr128,
2856 .zcm_gpr64,
2857 .zcz_fpr128,
2858 .zcz_gpr32,
2859 .zcz_gpr64,
2860 }),
2861 };
2862 pub const apple_s9: CpuModel = .{
2863 .name = "apple_s9",
2864 .llvm_name = "apple-s9",
2865 .features = featureSet(&[_]Feature{
2866 .aes,
2867 .alternate_sextload_cvt_f32_pattern,
2868 .arith_bcc_fusion,
2869 .arith_cbz_fusion,
2870 .disable_latency_sched_heuristic,
2871 .fp16fml,
2872 .fpac,
2873 .fuse_address,
2874 .fuse_adrp_add,
2875 .fuse_aes,
2876 .fuse_arith_logic,
2877 .fuse_crypto_eor,
2878 .fuse_csel,
2879 .fuse_literals,
2880 .hcx,
2881 .max_interleave_factor_4,
2882 .no_zcz_fpr64,
2883 .perfmon,
2884 .sha3,
2885 .store_pair_suppress,
2886 .v8_6a,
2887 .zcm_fpr128,
2888 .zcm_gpr64,
2889 .zcz_fpr128,
2890 .zcz_gpr32,
2891 .zcz_gpr64,
2892 }),
2893 };
2894 pub const c1_nano: CpuModel = .{
2895 .name = "c1_nano",
2896 .llvm_name = "c1-nano",
2897 .features = featureSet(&[_]Feature{
2898 .chk,
2899 .clrbhb,
2900 .ete,
2901 .fp16fml,
2902 .fpac,
2903 .fuse_adrp_add,
2904 .fuse_aes,
2905 .mte,
2906 .perfmon,
2907 .rcpc3,
2908 .sme2,
2909 .specres2,
2910 .sve_bitperm,
2911 .use_fixed_over_scalable_if_equal_cost,
2912 .use_postra_scheduler,
2913 .use_wzr_to_vec_move,
2914 .v9_3a,
2915 }),
2916 };
2917 pub const c1_premium: CpuModel = .{
2918 .name = "c1_premium",
2919 .llvm_name = "c1-premium",
2920 .features = featureSet(&[_]Feature{
2921 .alu_lsl_fast,
2922 .avoid_ldapur,
2923 .chk,
2924 .clrbhb,
2925 .enable_select_opt,
2926 .ete,
2927 .fp16fml,
2928 .fpac,
2929 .fuse_adrp_add,
2930 .fuse_aes,
2931 .fuse_csel,
2932 .fuse_cset,
2933 .mte,
2934 .perfmon,
2935 .predictable_select_expensive,
2936 .rcpc3,
2937 .sme2,
2938 .spe,
2939 .specres2,
2940 .sve_bitperm,
2941 .use_fixed_over_scalable_if_equal_cost,
2942 .use_postra_scheduler,
2943 .v9_3a,
2944 }),
2945 };
2946 pub const c1_pro: CpuModel = .{
2947 .name = "c1_pro",
2948 .llvm_name = "c1-pro",
2949 .features = featureSet(&[_]Feature{
2950 .alu_lsl_fast,
2951 .chk,
2952 .clrbhb,
2953 .cmp_bcc_fusion,
2954 .enable_select_opt,
2955 .ete,
2956 .fp16fml,
2957 .fpac,
2958 .fuse_adrp_add,
2959 .fuse_aes,
2960 .fuse_csel,
2961 .fuse_cset,
2962 .mte,
2963 .perfmon,
2964 .predictable_select_expensive,
2965 .rcpc3,
2966 .sme2,
2967 .spe,
2968 .specres2,
2969 .sve_bitperm,
2970 .use_postra_scheduler,
2971 .v9_3a,
2972 }),
2973 };
2974 pub const c1_ultra: CpuModel = .{
2975 .name = "c1_ultra",
2976 .llvm_name = "c1-ultra",
2977 .features = featureSet(&[_]Feature{
2978 .alu_lsl_fast,
2979 .avoid_ldapur,
2980 .chk,
2981 .clrbhb,
2982 .enable_select_opt,
2983 .ete,
2984 .fp16fml,
2985 .fpac,
2986 .fuse_adrp_add,
2987 .fuse_aes,
2988 .fuse_csel,
2989 .fuse_cset,
2990 .mte,
2991 .perfmon,
2992 .predictable_select_expensive,
2993 .rcpc3,
2994 .sme2,
2995 .spe,
2996 .specres2,
2997 .sve_bitperm,
2998 .use_fixed_over_scalable_if_equal_cost,
2999 .use_postra_scheduler,
3000 .v9_3a,
3001 }),
3002 };
3003 pub const carmel: CpuModel = .{
3004 .name = "carmel",
3005 .llvm_name = "carmel",
3006 .features = featureSet(&[_]Feature{
3007 .aes,
3008 .fullfp16,
3009 .sha2,
3010 .v8_2a,
3011 }),
3012 };
3013 pub const cobalt_100: CpuModel = .{
3014 .name = "cobalt_100",
3015 .llvm_name = "cobalt-100",
3016 .features = featureSet(&[_]Feature{
3017 .alu_lsl_fast,
3018 .bf16,
3019 .disable_maximize_scalable_bandwidth,
3020 .enable_select_opt,
3021 .ete,
3022 .fp16fml,
3023 .fpac,
3024 .fuse_adrp_add,
3025 .fuse_aes,
3026 .fuse_csel,
3027 .fuse_cset,
3028 .i8mm,
3029 .mte,
3030 .perfmon,
3031 .predictable_select_expensive,
3032 .sve_bitperm,
3033 .use_postra_scheduler,
3034 .v9a,
3035 }),
3036 };
3037 pub const cortex_a320: CpuModel = .{
3038 .name = "cortex_a320",
3039 .llvm_name = "cortex-a320",
3040 .features = featureSet(&[_]Feature{
3041 .a320,
3042 .ete,
3043 .fp16fml,
3044 .mte,
3045 .perfmon,
3046 .sve_bitperm,
3047 .v9_2a,
3048 }),
3049 };
3050 pub const cortex_a34: CpuModel = .{
3051 .name = "cortex_a34",
3052 .llvm_name = "cortex-a34",
3053 .features = featureSet(&[_]Feature{
3054 .aes,
3055 .crc,
3056 .perfmon,
3057 .sha2,
3058 .v8a,
3059 }),
3060 };
3061 pub const cortex_a35: CpuModel = .{
3062 .name = "cortex_a35",
3063 .llvm_name = "cortex-a35",
3064 .features = featureSet(&[_]Feature{
3065 .aes,
3066 .crc,
3067 .perfmon,
3068 .sha2,
3069 .v8a,
3070 }),
3071 };
3072 pub const cortex_a510: CpuModel = .{
3073 .name = "cortex_a510",
3074 .llvm_name = "cortex-a510",
3075 .features = featureSet(&[_]Feature{
3076 .bf16,
3077 .ete,
3078 .fp16fml,
3079 .fpac,
3080 .fuse_adrp_add,
3081 .fuse_aes,
3082 .i8mm,
3083 .mte,
3084 .perfmon,
3085 .sve_bitperm,
3086 .use_fixed_over_scalable_if_equal_cost,
3087 .use_postra_scheduler,
3088 .use_wzr_to_vec_move,
3089 .v9a,
3090 }),
3091 };
3092 pub const cortex_a520: CpuModel = .{
3093 .name = "cortex_a520",
3094 .llvm_name = "cortex-a520",
3095 .features = featureSet(&[_]Feature{
3096 .ete,
3097 .fp16fml,
3098 .fpac,
3099 .fuse_adrp_add,
3100 .fuse_aes,
3101 .mte,
3102 .perfmon,
3103 .sve_bitperm,
3104 .use_fixed_over_scalable_if_equal_cost,
3105 .use_postra_scheduler,
3106 .use_wzr_to_vec_move,
3107 .v9_2a,
3108 }),
3109 };
3110 pub const cortex_a520ae: CpuModel = .{
3111 .name = "cortex_a520ae",
3112 .llvm_name = "cortex-a520ae",
3113 .features = featureSet(&[_]Feature{
3114 .ete,
3115 .fp16fml,
3116 .fpac,
3117 .fuse_adrp_add,
3118 .fuse_aes,
3119 .mte,
3120 .perfmon,
3121 .sve_bitperm,
3122 .use_postra_scheduler,
3123 .use_wzr_to_vec_move,
3124 .v9_2a,
3125 }),
3126 };
3127 pub const cortex_a53: CpuModel = .{
3128 .name = "cortex_a53",
3129 .llvm_name = "cortex-a53",
3130 .features = featureSet(&[_]Feature{
3131 .aes,
3132 .balance_fp_ops,
3133 .crc,
3134 .fuse_adrp_add,
3135 .fuse_aes,
3136 .perfmon,
3137 .sha2,
3138 .use_postra_scheduler,
3139 .use_wzr_to_vec_move,
3140 .v8a,
3141 }),
3142 };
3143 pub const cortex_a55: CpuModel = .{
3144 .name = "cortex_a55",
3145 .llvm_name = "cortex-a55",
3146 .features = featureSet(&[_]Feature{
3147 .aes,
3148 .dotprod,
3149 .fullfp16,
3150 .fuse_address,
3151 .fuse_adrp_add,
3152 .fuse_aes,
3153 .perfmon,
3154 .rcpc,
3155 .sha2,
3156 .use_postra_scheduler,
3157 .use_wzr_to_vec_move,
3158 .v8_2a,
3159 }),
3160 };
3161 pub const cortex_a57: CpuModel = .{
3162 .name = "cortex_a57",
3163 .llvm_name = "cortex-a57",
3164 .features = featureSet(&[_]Feature{
3165 .addr_lsl_slow_14,
3166 .aes,
3167 .balance_fp_ops,
3168 .crc,
3169 .enable_select_opt,
3170 .fuse_adrp_add,
3171 .fuse_aes,
3172 .fuse_literals,
3173 .max_interleave_factor_4,
3174 .perfmon,
3175 .predictable_select_expensive,
3176 .sha2,
3177 .use_postra_scheduler,
3178 .v8a,
3179 }),
3180 };
3181 pub const cortex_a65: CpuModel = .{
3182 .name = "cortex_a65",
3183 .llvm_name = "cortex-a65",
3184 .features = featureSet(&[_]Feature{
3185 .aes,
3186 .dotprod,
3187 .enable_select_opt,
3188 .fullfp16,
3189 .fuse_address,
3190 .fuse_adrp_add,
3191 .fuse_aes,
3192 .fuse_literals,
3193 .perfmon,
3194 .predictable_select_expensive,
3195 .rcpc,
3196 .sha2,
3197 .ssbs,
3198 .v8_2a,
3199 }),
3200 };
3201 pub const cortex_a65ae: CpuModel = .{
3202 .name = "cortex_a65ae",
3203 .llvm_name = "cortex-a65ae",
3204 .features = featureSet(&[_]Feature{
3205 .aes,
3206 .dotprod,
3207 .enable_select_opt,
3208 .fullfp16,
3209 .fuse_address,
3210 .fuse_adrp_add,
3211 .fuse_aes,
3212 .fuse_literals,
3213 .perfmon,
3214 .predictable_select_expensive,
3215 .rcpc,
3216 .sha2,
3217 .ssbs,
3218 .v8_2a,
3219 }),
3220 };
3221 pub const cortex_a710: CpuModel = .{
3222 .name = "cortex_a710",
3223 .llvm_name = "cortex-a710",
3224 .features = featureSet(&[_]Feature{
3225 .alu_lsl_fast,
3226 .bf16,
3227 .cmp_bcc_fusion,
3228 .enable_select_opt,
3229 .ete,
3230 .fp16fml,
3231 .fpac,
3232 .fuse_adrp_add,
3233 .fuse_aes,
3234 .fuse_csel,
3235 .fuse_cset,
3236 .i8mm,
3237 .mte,
3238 .perfmon,
3239 .predictable_select_expensive,
3240 .sve_bitperm,
3241 .use_postra_scheduler,
3242 .v9a,
3243 }),
3244 };
3245 pub const cortex_a715: CpuModel = .{
3246 .name = "cortex_a715",
3247 .llvm_name = "cortex-a715",
3248 .features = featureSet(&[_]Feature{
3249 .alu_lsl_fast,
3250 .bf16,
3251 .cmp_bcc_fusion,
3252 .enable_select_opt,
3253 .ete,
3254 .fp16fml,
3255 .fpac,
3256 .fuse_adrp_add,
3257 .fuse_aes,
3258 .fuse_csel,
3259 .fuse_cset,
3260 .i8mm,
3261 .mte,
3262 .perfmon,
3263 .predictable_select_expensive,
3264 .spe,
3265 .sve_bitperm,
3266 .use_postra_scheduler,
3267 .v9a,
3268 }),
3269 };
3270 pub const cortex_a72: CpuModel = .{
3271 .name = "cortex_a72",
3272 .llvm_name = "cortex-a72",
3273 .features = featureSet(&[_]Feature{
3274 .addr_lsl_slow_14,
3275 .aes,
3276 .crc,
3277 .enable_select_opt,
3278 .fuse_adrp_add,
3279 .fuse_aes,
3280 .fuse_literals,
3281 .perfmon,
3282 .predictable_select_expensive,
3283 .sha2,
3284 .v8a,
3285 }),
3286 };
3287 pub const cortex_a720: CpuModel = .{
3288 .name = "cortex_a720",
3289 .llvm_name = "cortex-a720",
3290 .features = featureSet(&[_]Feature{
3291 .alu_lsl_fast,
3292 .cmp_bcc_fusion,
3293 .enable_select_opt,
3294 .ete,
3295 .fp16fml,
3296 .fpac,
3297 .fuse_adrp_add,
3298 .fuse_aes,
3299 .fuse_csel,
3300 .fuse_cset,
3301 .mte,
3302 .perfmon,
3303 .predictable_select_expensive,
3304 .spe,
3305 .sve_bitperm,
3306 .use_postra_scheduler,
3307 .v9_2a,
3308 }),
3309 };
3310 pub const cortex_a720ae: CpuModel = .{
3311 .name = "cortex_a720ae",
3312 .llvm_name = "cortex-a720ae",
3313 .features = featureSet(&[_]Feature{
3314 .alu_lsl_fast,
3315 .cmp_bcc_fusion,
3316 .enable_select_opt,
3317 .ete,
3318 .fp16fml,
3319 .fpac,
3320 .fuse_adrp_add,
3321 .fuse_aes,
3322 .fuse_csel,
3323 .fuse_cset,
3324 .mte,
3325 .perfmon,
3326 .predictable_select_expensive,
3327 .spe,
3328 .sve_bitperm,
3329 .use_postra_scheduler,
3330 .v9_2a,
3331 }),
3332 };
3333 pub const cortex_a725: CpuModel = .{
3334 .name = "cortex_a725",
3335 .llvm_name = "cortex-a725",
3336 .features = featureSet(&[_]Feature{
3337 .alu_lsl_fast,
3338 .cmp_bcc_fusion,
3339 .enable_select_opt,
3340 .ete,
3341 .fp16fml,
3342 .fpac,
3343 .fuse_adrp_add,
3344 .fuse_aes,
3345 .fuse_csel,
3346 .fuse_cset,
3347 .mte,
3348 .perfmon,
3349 .predictable_select_expensive,
3350 .spe,
3351 .sve_bitperm,
3352 .use_postra_scheduler,
3353 .v9_2a,
3354 }),
3355 };
3356 pub const cortex_a73: CpuModel = .{
3357 .name = "cortex_a73",
3358 .llvm_name = "cortex-a73",
3359 .features = featureSet(&[_]Feature{
3360 .addr_lsl_slow_14,
3361 .aes,
3362 .crc,
3363 .enable_select_opt,
3364 .fuse_adrp_add,
3365 .fuse_aes,
3366 .perfmon,
3367 .predictable_select_expensive,
3368 .sha2,
3369 .v8a,
3370 }),
3371 };
3372 pub const cortex_a75: CpuModel = .{
3373 .name = "cortex_a75",
3374 .llvm_name = "cortex-a75",
3375 .features = featureSet(&[_]Feature{
3376 .addr_lsl_slow_14,
3377 .aes,
3378 .dotprod,
3379 .enable_select_opt,
3380 .fullfp16,
3381 .fuse_adrp_add,
3382 .fuse_aes,
3383 .perfmon,
3384 .predictable_select_expensive,
3385 .rcpc,
3386 .sha2,
3387 .v8_2a,
3388 }),
3389 };
3390 pub const cortex_a76: CpuModel = .{
3391 .name = "cortex_a76",
3392 .llvm_name = "cortex-a76",
3393 .features = featureSet(&[_]Feature{
3394 .addr_lsl_slow_14,
3395 .aes,
3396 .alu_lsl_fast,
3397 .dotprod,
3398 .enable_select_opt,
3399 .fullfp16,
3400 .fuse_adrp_add,
3401 .fuse_aes,
3402 .perfmon,
3403 .predictable_select_expensive,
3404 .rcpc,
3405 .sha2,
3406 .ssbs,
3407 .v8_2a,
3408 }),
3409 };
3410 pub const cortex_a76ae: CpuModel = .{
3411 .name = "cortex_a76ae",
3412 .llvm_name = "cortex-a76ae",
3413 .features = featureSet(&[_]Feature{
3414 .addr_lsl_slow_14,
3415 .aes,
3416 .alu_lsl_fast,
3417 .dotprod,
3418 .enable_select_opt,
3419 .fullfp16,
3420 .fuse_adrp_add,
3421 .fuse_aes,
3422 .perfmon,
3423 .predictable_select_expensive,
3424 .rcpc,
3425 .sha2,
3426 .ssbs,
3427 .v8_2a,
3428 }),
3429 };
3430 pub const cortex_a77: CpuModel = .{
3431 .name = "cortex_a77",
3432 .llvm_name = "cortex-a77",
3433 .features = featureSet(&[_]Feature{
3434 .addr_lsl_slow_14,
3435 .aes,
3436 .alu_lsl_fast,
3437 .cmp_bcc_fusion,
3438 .dotprod,
3439 .enable_select_opt,
3440 .fullfp16,
3441 .fuse_adrp_add,
3442 .fuse_aes,
3443 .perfmon,
3444 .predictable_select_expensive,
3445 .rcpc,
3446 .sha2,
3447 .ssbs,
3448 .v8_2a,
3449 }),
3450 };
3451 pub const cortex_a78: CpuModel = .{
3452 .name = "cortex_a78",
3453 .llvm_name = "cortex-a78",
3454 .features = featureSet(&[_]Feature{
3455 .addr_lsl_slow_14,
3456 .aes,
3457 .alu_lsl_fast,
3458 .cmp_bcc_fusion,
3459 .dotprod,
3460 .enable_select_opt,
3461 .fullfp16,
3462 .fuse_adrp_add,
3463 .fuse_aes,
3464 .fuse_csel,
3465 .fuse_cset,
3466 .perfmon,
3467 .predictable_select_expensive,
3468 .rcpc,
3469 .sha2,
3470 .spe,
3471 .ssbs,
3472 .use_postra_scheduler,
3473 .v8_2a,
3474 }),
3475 };
3476 pub const cortex_a78ae: CpuModel = .{
3477 .name = "cortex_a78ae",
3478 .llvm_name = "cortex-a78ae",
3479 .features = featureSet(&[_]Feature{
3480 .addr_lsl_slow_14,
3481 .aes,
3482 .alu_lsl_fast,
3483 .cmp_bcc_fusion,
3484 .dotprod,
3485 .enable_select_opt,
3486 .fullfp16,
3487 .fuse_adrp_add,
3488 .fuse_aes,
3489 .fuse_csel,
3490 .fuse_cset,
3491 .perfmon,
3492 .predictable_select_expensive,
3493 .rcpc,
3494 .sha2,
3495 .spe,
3496 .ssbs,
3497 .use_postra_scheduler,
3498 .v8_2a,
3499 }),
3500 };
3501 pub const cortex_a78c: CpuModel = .{
3502 .name = "cortex_a78c",
3503 .llvm_name = "cortex-a78c",
3504 .features = featureSet(&[_]Feature{
3505 .addr_lsl_slow_14,
3506 .aes,
3507 .alu_lsl_fast,
3508 .cmp_bcc_fusion,
3509 .dotprod,
3510 .enable_select_opt,
3511 .flagm,
3512 .fullfp16,
3513 .fuse_adrp_add,
3514 .fuse_aes,
3515 .fuse_csel,
3516 .fuse_cset,
3517 .pauth,
3518 .perfmon,
3519 .predictable_select_expensive,
3520 .rcpc,
3521 .sha2,
3522 .spe,
3523 .ssbs,
3524 .use_postra_scheduler,
3525 .v8_2a,
3526 }),
3527 };
3528 pub const cortex_r82: CpuModel = .{
3529 .name = "cortex_r82",
3530 .llvm_name = "cortex-r82",
3531 .features = featureSet(&[_]Feature{
3532 .ccdp,
3533 .fpac,
3534 .perfmon,
3535 .predres,
3536 .use_postra_scheduler,
3537 .v8r,
3538 }),
3539 };
3540 pub const cortex_r82ae: CpuModel = .{
3541 .name = "cortex_r82ae",
3542 .llvm_name = "cortex-r82ae",
3543 .features = featureSet(&[_]Feature{
3544 .ccdp,
3545 .fpac,
3546 .perfmon,
3547 .predres,
3548 .use_postra_scheduler,
3549 .v8r,
3550 }),
3551 };
3552 pub const cortex_x1: CpuModel = .{
3553 .name = "cortex_x1",
3554 .llvm_name = "cortex-x1",
3555 .features = featureSet(&[_]Feature{
3556 .addr_lsl_slow_14,
3557 .aes,
3558 .alu_lsl_fast,
3559 .cmp_bcc_fusion,
3560 .dotprod,
3561 .enable_select_opt,
3562 .fullfp16,
3563 .fuse_adrp_add,
3564 .fuse_aes,
3565 .perfmon,
3566 .predictable_select_expensive,
3567 .rcpc,
3568 .sha2,
3569 .spe,
3570 .ssbs,
3571 .use_postra_scheduler,
3572 .v8_2a,
3573 }),
3574 };
3575 pub const cortex_x1c: CpuModel = .{
3576 .name = "cortex_x1c",
3577 .llvm_name = "cortex-x1c",
3578 .features = featureSet(&[_]Feature{
3579 .addr_lsl_slow_14,
3580 .aes,
3581 .alu_lsl_fast,
3582 .cmp_bcc_fusion,
3583 .dotprod,
3584 .enable_select_opt,
3585 .flagm,
3586 .fullfp16,
3587 .fuse_adrp_add,
3588 .fuse_aes,
3589 .lse2,
3590 .pauth,
3591 .perfmon,
3592 .predictable_select_expensive,
3593 .rcpc_immo,
3594 .sha2,
3595 .spe,
3596 .ssbs,
3597 .use_postra_scheduler,
3598 .v8_2a,
3599 }),
3600 };
3601 pub const cortex_x2: CpuModel = .{
3602 .name = "cortex_x2",
3603 .llvm_name = "cortex-x2",
3604 .features = featureSet(&[_]Feature{
3605 .alu_lsl_fast,
3606 .bf16,
3607 .cmp_bcc_fusion,
3608 .enable_select_opt,
3609 .ete,
3610 .fp16fml,
3611 .fpac,
3612 .fuse_adrp_add,
3613 .fuse_aes,
3614 .i8mm,
3615 .mte,
3616 .perfmon,
3617 .predictable_select_expensive,
3618 .sve_bitperm,
3619 .use_fixed_over_scalable_if_equal_cost,
3620 .use_postra_scheduler,
3621 .v9a,
3622 }),
3623 };
3624 pub const cortex_x3: CpuModel = .{
3625 .name = "cortex_x3",
3626 .llvm_name = "cortex-x3",
3627 .features = featureSet(&[_]Feature{
3628 .alu_lsl_fast,
3629 .avoid_ldapur,
3630 .bf16,
3631 .enable_select_opt,
3632 .ete,
3633 .fp16fml,
3634 .fpac,
3635 .fuse_adrp_add,
3636 .fuse_aes,
3637 .i8mm,
3638 .mte,
3639 .perfmon,
3640 .predictable_select_expensive,
3641 .spe,
3642 .sve_bitperm,
3643 .use_fixed_over_scalable_if_equal_cost,
3644 .use_postra_scheduler,
3645 .v9a,
3646 }),
3647 };
3648 pub const cortex_x4: CpuModel = .{
3649 .name = "cortex_x4",
3650 .llvm_name = "cortex-x4",
3651 .features = featureSet(&[_]Feature{
3652 .alu_lsl_fast,
3653 .avoid_ldapur,
3654 .enable_select_opt,
3655 .ete,
3656 .fp16fml,
3657 .fpac,
3658 .fuse_adrp_add,
3659 .fuse_aes,
3660 .fuse_csel,
3661 .fuse_cset,
3662 .mte,
3663 .perfmon,
3664 .predictable_select_expensive,
3665 .spe,
3666 .sve_bitperm,
3667 .use_fixed_over_scalable_if_equal_cost,
3668 .use_postra_scheduler,
3669 .v9_2a,
3670 }),
3671 };
3672 pub const cortex_x925: CpuModel = .{
3673 .name = "cortex_x925",
3674 .llvm_name = "cortex-x925",
3675 .features = featureSet(&[_]Feature{
3676 .alu_lsl_fast,
3677 .avoid_ldapur,
3678 .enable_select_opt,
3679 .ete,
3680 .fp16fml,
3681 .fpac,
3682 .fuse_adrp_add,
3683 .fuse_aes,
3684 .fuse_csel,
3685 .fuse_cset,
3686 .mte,
3687 .perfmon,
3688 .predictable_select_expensive,
3689 .spe,
3690 .sve_bitperm,
3691 .use_fixed_over_scalable_if_equal_cost,
3692 .use_postra_scheduler,
3693 .v9_2a,
3694 }),
3695 };
3696 pub const cyclone: CpuModel = .{
3697 .name = "cyclone",
3698 .llvm_name = "cyclone",
3699 .features = featureSet(&[_]Feature{
3700 .aes,
3701 .alternate_sextload_cvt_f32_pattern,
3702 .arith_bcc_fusion,
3703 .arith_cbz_fusion,
3704 .disable_latency_sched_heuristic,
3705 .fuse_aes,
3706 .fuse_crypto_eor,
3707 .no_zcz_fpr64,
3708 .perfmon,
3709 .sha2,
3710 .store_pair_suppress,
3711 .v8a,
3712 .zcm_fpr128,
3713 .zcm_gpr64,
3714 .zcz_fp_workaround,
3715 .zcz_fpr128,
3716 .zcz_gpr32,
3717 .zcz_gpr64,
3718 }),
3719 };
3720 pub const emag: CpuModel = .{
3721 .name = "emag",
3722 .llvm_name = null,
3723 .features = featureSet(&[_]Feature{
3724 .crc,
3725 .crypto,
3726 .perfmon,
3727 .v8a,
3728 }),
3729 };
3730 pub const exynos_m1: CpuModel = .{
3731 .name = "exynos_m1",
3732 .llvm_name = null,
3733 .features = featureSet(&[_]Feature{
3734 .crc,
3735 .crypto,
3736 .exynos_cheap_as_move,
3737 .force_32bit_jump_tables,
3738 .fuse_aes,
3739 .perfmon,
3740 .slow_misaligned_128store,
3741 .slow_paired_128,
3742 .use_postra_scheduler,
3743 .use_reciprocal_square_root,
3744 .v8a,
3745 }),
3746 };
3747 pub const exynos_m2: CpuModel = .{
3748 .name = "exynos_m2",
3749 .llvm_name = null,
3750 .features = featureSet(&[_]Feature{
3751 .crc,
3752 .crypto,
3753 .exynos_cheap_as_move,
3754 .force_32bit_jump_tables,
3755 .fuse_aes,
3756 .perfmon,
3757 .slow_misaligned_128store,
3758 .slow_paired_128,
3759 .use_postra_scheduler,
3760 .v8a,
3761 }),
3762 };
3763 pub const exynos_m3: CpuModel = .{
3764 .name = "exynos_m3",
3765 .llvm_name = "exynos-m3",
3766 .features = featureSet(&[_]Feature{
3767 .aes,
3768 .alu_lsl_fast,
3769 .crc,
3770 .exynos_cheap_as_move,
3771 .force_32bit_jump_tables,
3772 .fuse_address,
3773 .fuse_adrp_add,
3774 .fuse_aes,
3775 .fuse_csel,
3776 .fuse_literals,
3777 .max_interleave_factor_4,
3778 .perfmon,
3779 .predictable_select_expensive,
3780 .sha2,
3781 .store_pair_suppress,
3782 .use_postra_scheduler,
3783 .v8a,
3784 }),
3785 };
3786 pub const exynos_m4: CpuModel = .{
3787 .name = "exynos_m4",
3788 .llvm_name = "exynos-m4",
3789 .features = featureSet(&[_]Feature{
3790 .aes,
3791 .alu_lsl_fast,
3792 .arith_bcc_fusion,
3793 .arith_cbz_fusion,
3794 .dotprod,
3795 .exynos_cheap_as_move,
3796 .force_32bit_jump_tables,
3797 .fullfp16,
3798 .fuse_address,
3799 .fuse_adrp_add,
3800 .fuse_aes,
3801 .fuse_arith_logic,
3802 .fuse_csel,
3803 .fuse_literals,
3804 .max_interleave_factor_4,
3805 .perfmon,
3806 .sha2,
3807 .store_pair_suppress,
3808 .use_postra_scheduler,
3809 .v8_2a,
3810 .zcz_gpr32,
3811 .zcz_gpr64,
3812 }),
3813 };
3814 pub const exynos_m5: CpuModel = .{
3815 .name = "exynos_m5",
3816 .llvm_name = "exynos-m5",
3817 .features = featureSet(&[_]Feature{
3818 .aes,
3819 .alu_lsl_fast,
3820 .arith_bcc_fusion,
3821 .arith_cbz_fusion,
3822 .dotprod,
3823 .exynos_cheap_as_move,
3824 .force_32bit_jump_tables,
3825 .fullfp16,
3826 .fuse_address,
3827 .fuse_adrp_add,
3828 .fuse_aes,
3829 .fuse_arith_logic,
3830 .fuse_csel,
3831 .fuse_literals,
3832 .max_interleave_factor_4,
3833 .perfmon,
3834 .sha2,
3835 .store_pair_suppress,
3836 .use_postra_scheduler,
3837 .v8_2a,
3838 .zcz_gpr32,
3839 .zcz_gpr64,
3840 }),
3841 };
3842 pub const falkor: CpuModel = .{
3843 .name = "falkor",
3844 .llvm_name = "falkor",
3845 .features = featureSet(&[_]Feature{
3846 .aes,
3847 .alu_lsl_fast,
3848 .crc,
3849 .max_interleave_factor_4,
3850 .perfmon,
3851 .predictable_select_expensive,
3852 .rdm,
3853 .sha2,
3854 .slow_strqro_store,
3855 .store_pair_suppress,
3856 .use_postra_scheduler,
3857 .v8a,
3858 .zcz_gpr32,
3859 .zcz_gpr64,
3860 }),
3861 };
3862 pub const fujitsu_monaka: CpuModel = .{
3863 .name = "fujitsu_monaka",
3864 .llvm_name = "fujitsu-monaka",
3865 .features = featureSet(&[_]Feature{
3866 .clrbhb,
3867 .ete,
3868 .faminmax,
3869 .fp16fml,
3870 .fp8dot2,
3871 .fp8dot4,
3872 .fp8fma,
3873 .fpac,
3874 .fujitsu_monaka,
3875 .ls64,
3876 .lut,
3877 .perfmon,
3878 .rand,
3879 .specres2,
3880 .sve_aes,
3881 .sve_bitperm,
3882 .sve_sha3,
3883 .sve_sm4,
3884 .v9_3a,
3885 }),
3886 };
3887 pub const gb10: CpuModel = .{
3888 .name = "gb10",
3889 .llvm_name = "gb10",
3890 .features = featureSet(&[_]Feature{
3891 .alu_lsl_fast,
3892 .avoid_ldapur,
3893 .enable_select_opt,
3894 .ete,
3895 .fp16fml,
3896 .fpac,
3897 .fuse_adrp_add,
3898 .fuse_aes,
3899 .fuse_csel,
3900 .fuse_cset,
3901 .mte,
3902 .perfmon,
3903 .predictable_select_expensive,
3904 .spe,
3905 .sve_aes,
3906 .sve_bitperm,
3907 .sve_sha3,
3908 .sve_sm4,
3909 .use_fixed_over_scalable_if_equal_cost,
3910 .use_postra_scheduler,
3911 .v9_2a,
3912 }),
3913 };
3914 pub const generic: CpuModel = .{
3915 .name = "generic",
3916 .llvm_name = "generic",
3917 .features = featureSet(&[_]Feature{
3918 .enable_select_opt,
3919 .ete,
3920 .fuse_adrp_add,
3921 .fuse_aes,
3922 .neon,
3923 .use_postra_scheduler,
3924 }),
3925 };
3926 pub const grace: CpuModel = .{
3927 .name = "grace",
3928 .llvm_name = "grace",
3929 .features = featureSet(&[_]Feature{
3930 .alu_lsl_fast,
3931 .avoid_ldapur,
3932 .bf16,
3933 .cmp_bcc_fusion,
3934 .disable_latency_sched_heuristic,
3935 .enable_select_opt,
3936 .ete,
3937 .fp16fml,
3938 .fpac,
3939 .fuse_adrp_add,
3940 .fuse_aes,
3941 .fuse_csel,
3942 .fuse_cset,
3943 .i8mm,
3944 .max_interleave_factor_4,
3945 .mte,
3946 .perfmon,
3947 .predictable_select_expensive,
3948 .spe,
3949 .sve_aes,
3950 .sve_bitperm,
3951 .sve_sha3,
3952 .sve_sm4,
3953 .use_fixed_over_scalable_if_equal_cost,
3954 .use_postra_scheduler,
3955 .v9a,
3956 }),
3957 };
3958 pub const kryo: CpuModel = .{
3959 .name = "kryo",
3960 .llvm_name = "kryo",
3961 .features = featureSet(&[_]Feature{
3962 .aes,
3963 .alu_lsl_fast,
3964 .crc,
3965 .max_interleave_factor_4,
3966 .perfmon,
3967 .predictable_select_expensive,
3968 .sha2,
3969 .store_pair_suppress,
3970 .use_postra_scheduler,
3971 .v8a,
3972 .zcz_gpr32,
3973 .zcz_gpr64,
3974 }),
3975 };
3976 pub const neoverse_512tvb: CpuModel = .{
3977 .name = "neoverse_512tvb",
3978 .llvm_name = "neoverse-512tvb",
3979 .features = featureSet(&[_]Feature{
3980 .aes,
3981 .alu_lsl_fast,
3982 .bf16,
3983 .ccdp,
3984 .enable_select_opt,
3985 .fp16fml,
3986 .fpac,
3987 .fuse_adrp_add,
3988 .fuse_aes,
3989 .i8mm,
3990 .max_interleave_factor_4,
3991 .perfmon,
3992 .predictable_select_expensive,
3993 .rand,
3994 .sha3,
3995 .sm4,
3996 .spe,
3997 .ssbs,
3998 .sve,
3999 .use_postra_scheduler,
4000 .v8_4a,
4001 }),
4002 };
4003 pub const neoverse_e1: CpuModel = .{
4004 .name = "neoverse_e1",
4005 .llvm_name = "neoverse-e1",
4006 .features = featureSet(&[_]Feature{
4007 .aes,
4008 .dotprod,
4009 .fullfp16,
4010 .fuse_adrp_add,
4011 .fuse_aes,
4012 .perfmon,
4013 .rcpc,
4014 .sha2,
4015 .ssbs,
4016 .use_postra_scheduler,
4017 .v8_2a,
4018 }),
4019 };
4020 pub const neoverse_n1: CpuModel = .{
4021 .name = "neoverse_n1",
4022 .llvm_name = "neoverse-n1",
4023 .features = featureSet(&[_]Feature{
4024 .addr_lsl_slow_14,
4025 .aes,
4026 .alu_lsl_fast,
4027 .dotprod,
4028 .enable_select_opt,
4029 .fullfp16,
4030 .fuse_adrp_add,
4031 .fuse_aes,
4032 .perfmon,
4033 .predictable_select_expensive,
4034 .rcpc,
4035 .sha2,
4036 .spe,
4037 .ssbs,
4038 .use_postra_scheduler,
4039 .v8_2a,
4040 }),
4041 };
4042 pub const neoverse_n2: CpuModel = .{
4043 .name = "neoverse_n2",
4044 .llvm_name = "neoverse-n2",
4045 .features = featureSet(&[_]Feature{
4046 .alu_lsl_fast,
4047 .bf16,
4048 .disable_maximize_scalable_bandwidth,
4049 .enable_select_opt,
4050 .ete,
4051 .fp16fml,
4052 .fpac,
4053 .fuse_adrp_add,
4054 .fuse_aes,
4055 .fuse_csel,
4056 .fuse_cset,
4057 .i8mm,
4058 .mte,
4059 .perfmon,
4060 .predictable_select_expensive,
4061 .sve_bitperm,
4062 .use_postra_scheduler,
4063 .v9a,
4064 }),
4065 };
4066 pub const neoverse_n3: CpuModel = .{
4067 .name = "neoverse_n3",
4068 .llvm_name = "neoverse-n3",
4069 .features = featureSet(&[_]Feature{
4070 .alu_lsl_fast,
4071 .enable_select_opt,
4072 .ete,
4073 .fp16fml,
4074 .fpac,
4075 .fuse_adrp_add,
4076 .fuse_aes,
4077 .fuse_csel,
4078 .fuse_cset,
4079 .mte,
4080 .perfmon,
4081 .predictable_select_expensive,
4082 .rand,
4083 .spe,
4084 .sve_bitperm,
4085 .use_postra_scheduler,
4086 .v9_2a,
4087 }),
4088 };
4089 pub const neoverse_v1: CpuModel = .{
4090 .name = "neoverse_v1",
4091 .llvm_name = "neoverse-v1",
4092 .features = featureSet(&[_]Feature{
4093 .addr_lsl_slow_14,
4094 .aes,
4095 .alu_lsl_fast,
4096 .bf16,
4097 .ccdp,
4098 .disable_maximize_scalable_bandwidth,
4099 .enable_select_opt,
4100 .fp16fml,
4101 .fuse_adrp_add,
4102 .fuse_aes,
4103 .fuse_csel,
4104 .fuse_cset,
4105 .i8mm,
4106 .no_sve_fp_ld1r,
4107 .perfmon,
4108 .predictable_select_expensive,
4109 .rand,
4110 .sha3,
4111 .sm4,
4112 .spe,
4113 .ssbs,
4114 .sve,
4115 .use_postra_scheduler,
4116 .v8_4a,
4117 }),
4118 };
4119 pub const neoverse_v2: CpuModel = .{
4120 .name = "neoverse_v2",
4121 .llvm_name = "neoverse-v2",
4122 .features = featureSet(&[_]Feature{
4123 .alu_lsl_fast,
4124 .avoid_ldapur,
4125 .bf16,
4126 .cmp_bcc_fusion,
4127 .disable_latency_sched_heuristic,
4128 .enable_select_opt,
4129 .ete,
4130 .fp16fml,
4131 .fpac,
4132 .fuse_adrp_add,
4133 .fuse_aes,
4134 .fuse_csel,
4135 .fuse_cset,
4136 .i8mm,
4137 .max_interleave_factor_4,
4138 .mte,
4139 .perfmon,
4140 .predictable_select_expensive,
4141 .rand,
4142 .spe,
4143 .sve_bitperm,
4144 .use_fixed_over_scalable_if_equal_cost,
4145 .use_postra_scheduler,
4146 .v9a,
4147 }),
4148 };
4149 pub const neoverse_v3: CpuModel = .{
4150 .name = "neoverse_v3",
4151 .llvm_name = "neoverse-v3",
4152 .features = featureSet(&[_]Feature{
4153 .alu_lsl_fast,
4154 .avoid_ldapur,
4155 .brbe,
4156 .enable_select_opt,
4157 .ete,
4158 .fp16fml,
4159 .fpac,
4160 .fuse_adrp_add,
4161 .fuse_aes,
4162 .fuse_csel,
4163 .fuse_cset,
4164 .ls64,
4165 .max_interleave_factor_4,
4166 .mte,
4167 .perfmon,
4168 .predictable_select_expensive,
4169 .rand,
4170 .spe,
4171 .sve_bitperm,
4172 .use_postra_scheduler,
4173 .v9_2a,
4174 }),
4175 };
4176 pub const neoverse_v3ae: CpuModel = .{
4177 .name = "neoverse_v3ae",
4178 .llvm_name = "neoverse-v3ae",
4179 .features = featureSet(&[_]Feature{
4180 .alu_lsl_fast,
4181 .avoid_ldapur,
4182 .brbe,
4183 .enable_select_opt,
4184 .ete,
4185 .fp16fml,
4186 .fpac,
4187 .fuse_adrp_add,
4188 .fuse_aes,
4189 .fuse_csel,
4190 .fuse_cset,
4191 .ls64,
4192 .max_interleave_factor_4,
4193 .mte,
4194 .perfmon,
4195 .predictable_select_expensive,
4196 .rand,
4197 .spe,
4198 .sve_bitperm,
4199 .use_postra_scheduler,
4200 .v9_2a,
4201 }),
4202 };
4203 pub const olympus: CpuModel = .{
4204 .name = "olympus",
4205 .llvm_name = "olympus",
4206 .features = featureSet(&[_]Feature{
4207 .brbe,
4208 .chk,
4209 .ete,
4210 .faminmax,
4211 .fp16fml,
4212 .fp8dot2,
4213 .fp8dot4,
4214 .fp8fma,
4215 .fpac,
4216 .ls64,
4217 .lut,
4218 .mte,
4219 .olympus,
4220 .perfmon,
4221 .rand,
4222 .spe,
4223 .sve_aes,
4224 .sve_bitperm,
4225 .sve_sha3,
4226 .sve_sm4,
4227 .v9_2a,
4228 }),
4229 };
4230 pub const oryon_1: CpuModel = .{
4231 .name = "oryon_1",
4232 .llvm_name = "oryon-1",
4233 .features = featureSet(&[_]Feature{
4234 .aes,
4235 .enable_select_opt,
4236 .fp16fml,
4237 .fuse_address,
4238 .fuse_adrp_add,
4239 .fuse_aes,
4240 .fuse_crypto_eor,
4241 .max_interleave_factor_4,
4242 .perfmon,
4243 .rand,
4244 .sha3,
4245 .sm4,
4246 .spe,
4247 .use_postra_scheduler,
4248 .v8_6a,
4249 }),
4250 };
4251 pub const saphira: CpuModel = .{
4252 .name = "saphira",
4253 .llvm_name = "saphira",
4254 .features = featureSet(&[_]Feature{
4255 .aes,
4256 .alu_lsl_fast,
4257 .max_interleave_factor_4,
4258 .perfmon,
4259 .predictable_select_expensive,
4260 .sha2,
4261 .spe,
4262 .store_pair_suppress,
4263 .use_postra_scheduler,
4264 .v8_4a,
4265 .zcz_gpr32,
4266 .zcz_gpr64,
4267 }),
4268 };
4269 pub const thunderx: CpuModel = .{
4270 .name = "thunderx",
4271 .llvm_name = "thunderx",
4272 .features = featureSet(&[_]Feature{
4273 .aes,
4274 .crc,
4275 .perfmon,
4276 .predictable_select_expensive,
4277 .sha2,
4278 .store_pair_suppress,
4279 .use_postra_scheduler,
4280 .v8a,
4281 }),
4282 };
4283 pub const thunderx2t99: CpuModel = .{
4284 .name = "thunderx2t99",
4285 .llvm_name = "thunderx2t99",
4286 .features = featureSet(&[_]Feature{
4287 .aes,
4288 .aggressive_fma,
4289 .arith_bcc_fusion,
4290 .max_interleave_factor_4,
4291 .predictable_select_expensive,
4292 .sha2,
4293 .store_pair_suppress,
4294 .use_postra_scheduler,
4295 .v8_1a,
4296 }),
4297 };
4298 pub const thunderx3t110: CpuModel = .{
4299 .name = "thunderx3t110",
4300 .llvm_name = "thunderx3t110",
4301 .features = featureSet(&[_]Feature{
4302 .aes,
4303 .aggressive_fma,
4304 .arith_bcc_fusion,
4305 .balance_fp_ops,
4306 .max_interleave_factor_4,
4307 .perfmon,
4308 .predictable_select_expensive,
4309 .sha2,
4310 .store_pair_suppress,
4311 .strict_align,
4312 .use_postra_scheduler,
4313 .v8_3a,
4314 }),
4315 };
4316 pub const thunderxt81: CpuModel = .{
4317 .name = "thunderxt81",
4318 .llvm_name = "thunderxt81",
4319 .features = featureSet(&[_]Feature{
4320 .aes,
4321 .crc,
4322 .perfmon,
4323 .predictable_select_expensive,
4324 .sha2,
4325 .store_pair_suppress,
4326 .use_postra_scheduler,
4327 .v8a,
4328 }),
4329 };
4330 pub const thunderxt83: CpuModel = .{
4331 .name = "thunderxt83",
4332 .llvm_name = "thunderxt83",
4333 .features = featureSet(&[_]Feature{
4334 .aes,
4335 .crc,
4336 .perfmon,
4337 .predictable_select_expensive,
4338 .sha2,
4339 .store_pair_suppress,
4340 .use_postra_scheduler,
4341 .v8a,
4342 }),
4343 };
4344 pub const thunderxt88: CpuModel = .{
4345 .name = "thunderxt88",
4346 .llvm_name = "thunderxt88",
4347 .features = featureSet(&[_]Feature{
4348 .aes,
4349 .crc,
4350 .perfmon,
4351 .predictable_select_expensive,
4352 .sha2,
4353 .store_pair_suppress,
4354 .use_postra_scheduler,
4355 .v8a,
4356 }),
4357 };
4358 pub const tsv110: CpuModel = .{
4359 .name = "tsv110",
4360 .llvm_name = "tsv110",
4361 .features = featureSet(&[_]Feature{
4362 .aes,
4363 .complxnum,
4364 .dotprod,
4365 .fp16fml,
4366 .fuse_aes,
4367 .jsconv,
4368 .perfmon,
4369 .sha2,
4370 .spe,
4371 .store_pair_suppress,
4372 .use_postra_scheduler,
4373 .v8_2a,
4374 }),
4375 };
4376 pub const xgene1: CpuModel = .{
4377 .name = "xgene1",
4378 .llvm_name = null,
4379 .features = featureSet(&[_]Feature{
4380 .perfmon,
4381 .v8a,
4382 }),
4383 };
4384};