| 1 | //! This file is auto-generated by tools/update_cpu_features.zig. |
| 2 | |
| 3 | const std = @import("../std.zig"); |
| 4 | const CpuFeature = std.Target.Cpu.Feature; |
| 5 | const CpuModel = std.Target.Cpu.Model; |
| 6 | |
| 7 | pub const Feature = enum { |
| 8 | isa_68000, |
| 9 | isa_68010, |
| 10 | isa_68020, |
| 11 | isa_68030, |
| 12 | isa_68040, |
| 13 | isa_68060, |
| 14 | isa_68881, |
| 15 | isa_68882, |
| 16 | reserve_a0, |
| 17 | reserve_a1, |
| 18 | reserve_a2, |
| 19 | reserve_a3, |
| 20 | reserve_a4, |
| 21 | reserve_a5, |
| 22 | reserve_a6, |
| 23 | reserve_d0, |
| 24 | reserve_d1, |
| 25 | reserve_d2, |
| 26 | reserve_d3, |
| 27 | reserve_d4, |
| 28 | reserve_d5, |
| 29 | reserve_d6, |
| 30 | reserve_d7, |
| 31 | }; |
| 32 | |
| 33 | pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; |
| 34 | pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas; |
| 35 | pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny; |
| 36 | pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll; |
| 37 | |
| 38 | pub const all_features = blk: { |
| 39 | const len = @typeInfo(Feature).@"enum".field_names.len; |
| 40 | std.debug.assert(len <= CpuFeature.Set.needed_bit_count); |
| 41 | var result: [len]CpuFeature = undefined; |
| 42 | result[@backingInt(Feature.isa_68000)] = .{ |
| 43 | .llvm_name = "isa-68000", |
| 44 | .description = "Is M68000 ISA supported", |
| 45 | .dependencies = featureSet(&[_]Feature{}), |
| 46 | }; |
| 47 | result[@backingInt(Feature.isa_68010)] = .{ |
| 48 | .llvm_name = "isa-68010", |
| 49 | .description = "Is M68010 ISA supported", |
| 50 | .dependencies = featureSet(&[_]Feature{ |
| 51 | .isa_68000, |
| 52 | }), |
| 53 | }; |
| 54 | result[@backingInt(Feature.isa_68020)] = .{ |
| 55 | .llvm_name = "isa-68020", |
| 56 | .description = "Is M68020 ISA supported", |
| 57 | .dependencies = featureSet(&[_]Feature{ |
| 58 | .isa_68010, |
| 59 | }), |
| 60 | }; |
| 61 | result[@backingInt(Feature.isa_68030)] = .{ |
| 62 | .llvm_name = "isa-68030", |
| 63 | .description = "Is M68030 ISA supported", |
| 64 | .dependencies = featureSet(&[_]Feature{ |
| 65 | .isa_68020, |
| 66 | }), |
| 67 | }; |
| 68 | result[@backingInt(Feature.isa_68040)] = .{ |
| 69 | .llvm_name = "isa-68040", |
| 70 | .description = "Is M68040 ISA supported", |
| 71 | .dependencies = featureSet(&[_]Feature{ |
| 72 | .isa_68030, |
| 73 | .isa_68882, |
| 74 | }), |
| 75 | }; |
| 76 | result[@backingInt(Feature.isa_68060)] = .{ |
| 77 | .llvm_name = "isa-68060", |
| 78 | .description = "Is M68060 ISA supported", |
| 79 | .dependencies = featureSet(&[_]Feature{ |
| 80 | .isa_68040, |
| 81 | }), |
| 82 | }; |
| 83 | result[@backingInt(Feature.isa_68881)] = .{ |
| 84 | .llvm_name = "isa-68881", |
| 85 | .description = "Is M68881 (FPU) ISA supported", |
| 86 | .dependencies = featureSet(&[_]Feature{}), |
| 87 | }; |
| 88 | result[@backingInt(Feature.isa_68882)] = .{ |
| 89 | .llvm_name = "isa-68882", |
| 90 | .description = "Is M68882 (FPU) ISA supported", |
| 91 | .dependencies = featureSet(&[_]Feature{ |
| 92 | .isa_68881, |
| 93 | }), |
| 94 | }; |
| 95 | result[@backingInt(Feature.reserve_a0)] = .{ |
| 96 | .llvm_name = "reserve-a0", |
| 97 | .description = "Reserve A0 register", |
| 98 | .dependencies = featureSet(&[_]Feature{}), |
| 99 | }; |
| 100 | result[@backingInt(Feature.reserve_a1)] = .{ |
| 101 | .llvm_name = "reserve-a1", |
| 102 | .description = "Reserve A1 register", |
| 103 | .dependencies = featureSet(&[_]Feature{}), |
| 104 | }; |
| 105 | result[@backingInt(Feature.reserve_a2)] = .{ |
| 106 | .llvm_name = "reserve-a2", |
| 107 | .description = "Reserve A2 register", |
| 108 | .dependencies = featureSet(&[_]Feature{}), |
| 109 | }; |
| 110 | result[@backingInt(Feature.reserve_a3)] = .{ |
| 111 | .llvm_name = "reserve-a3", |
| 112 | .description = "Reserve A3 register", |
| 113 | .dependencies = featureSet(&[_]Feature{}), |
| 114 | }; |
| 115 | result[@backingInt(Feature.reserve_a4)] = .{ |
| 116 | .llvm_name = "reserve-a4", |
| 117 | .description = "Reserve A4 register", |
| 118 | .dependencies = featureSet(&[_]Feature{}), |
| 119 | }; |
| 120 | result[@backingInt(Feature.reserve_a5)] = .{ |
| 121 | .llvm_name = "reserve-a5", |
| 122 | .description = "Reserve A5 register", |
| 123 | .dependencies = featureSet(&[_]Feature{}), |
| 124 | }; |
| 125 | result[@backingInt(Feature.reserve_a6)] = .{ |
| 126 | .llvm_name = "reserve-a6", |
| 127 | .description = "Reserve A6 register", |
| 128 | .dependencies = featureSet(&[_]Feature{}), |
| 129 | }; |
| 130 | result[@backingInt(Feature.reserve_d0)] = .{ |
| 131 | .llvm_name = "reserve-d0", |
| 132 | .description = "Reserve D0 register", |
| 133 | .dependencies = featureSet(&[_]Feature{}), |
| 134 | }; |
| 135 | result[@backingInt(Feature.reserve_d1)] = .{ |
| 136 | .llvm_name = "reserve-d1", |
| 137 | .description = "Reserve D1 register", |
| 138 | .dependencies = featureSet(&[_]Feature{}), |
| 139 | }; |
| 140 | result[@backingInt(Feature.reserve_d2)] = .{ |
| 141 | .llvm_name = "reserve-d2", |
| 142 | .description = "Reserve D2 register", |
| 143 | .dependencies = featureSet(&[_]Feature{}), |
| 144 | }; |
| 145 | result[@backingInt(Feature.reserve_d3)] = .{ |
| 146 | .llvm_name = "reserve-d3", |
| 147 | .description = "Reserve D3 register", |
| 148 | .dependencies = featureSet(&[_]Feature{}), |
| 149 | }; |
| 150 | result[@backingInt(Feature.reserve_d4)] = .{ |
| 151 | .llvm_name = "reserve-d4", |
| 152 | .description = "Reserve D4 register", |
| 153 | .dependencies = featureSet(&[_]Feature{}), |
| 154 | }; |
| 155 | result[@backingInt(Feature.reserve_d5)] = .{ |
| 156 | .llvm_name = "reserve-d5", |
| 157 | .description = "Reserve D5 register", |
| 158 | .dependencies = featureSet(&[_]Feature{}), |
| 159 | }; |
| 160 | result[@backingInt(Feature.reserve_d6)] = .{ |
| 161 | .llvm_name = "reserve-d6", |
| 162 | .description = "Reserve D6 register", |
| 163 | .dependencies = featureSet(&[_]Feature{}), |
| 164 | }; |
| 165 | result[@backingInt(Feature.reserve_d7)] = .{ |
| 166 | .llvm_name = "reserve-d7", |
| 167 | .description = "Reserve D7 register", |
| 168 | .dependencies = featureSet(&[_]Feature{}), |
| 169 | }; |
| 170 | const ti = @typeInfo(Feature); |
| 171 | for (&result, 0..) |*elem, i| { |
| 172 | elem.index = i; |
| 173 | elem.name = ti.@"enum".field_names[i]; |
| 174 | } |
| 175 | break :blk result; |
| 176 | }; |
| 177 | |
| 178 | pub const cpu = struct { |
| 179 | pub const generic: CpuModel = .{ |
| 180 | .name = "generic", |
| 181 | .llvm_name = "generic", |
| 182 | .features = featureSet(&[_]Feature{ |
| 183 | .isa_68000, |
| 184 | }), |
| 185 | }; |
| 186 | pub const M68000: CpuModel = .{ |
| 187 | .name = "M68000", |
| 188 | .llvm_name = "M68000", |
| 189 | .features = featureSet(&[_]Feature{ |
| 190 | .isa_68000, |
| 191 | }), |
| 192 | }; |
| 193 | pub const M68010: CpuModel = .{ |
| 194 | .name = "M68010", |
| 195 | .llvm_name = "M68010", |
| 196 | .features = featureSet(&[_]Feature{ |
| 197 | .isa_68010, |
| 198 | }), |
| 199 | }; |
| 200 | pub const M68020: CpuModel = .{ |
| 201 | .name = "M68020", |
| 202 | .llvm_name = "M68020", |
| 203 | .features = featureSet(&[_]Feature{ |
| 204 | .isa_68020, |
| 205 | }), |
| 206 | }; |
| 207 | pub const M68030: CpuModel = .{ |
| 208 | .name = "M68030", |
| 209 | .llvm_name = "M68030", |
| 210 | .features = featureSet(&[_]Feature{ |
| 211 | .isa_68030, |
| 212 | }), |
| 213 | }; |
| 214 | pub const M68040: CpuModel = .{ |
| 215 | .name = "M68040", |
| 216 | .llvm_name = "M68040", |
| 217 | .features = featureSet(&[_]Feature{ |
| 218 | .isa_68040, |
| 219 | }), |
| 220 | }; |
| 221 | pub const M68060: CpuModel = .{ |
| 222 | .name = "M68060", |
| 223 | .llvm_name = "M68060", |
| 224 | .features = featureSet(&[_]Feature{ |
| 225 | .isa_68060, |
| 226 | }), |
| 227 | }; |
| 228 | }; |