1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 @"32bit",
9 @"64bit",
10 a,
11 add_load_fusion,
12 addi_load_fusion,
13 andes45,
14 auipc_addi_fusion,
15 auipc_load_fusion,
16 b,
17 bfext_fusion,
18 c,
19 conditional_cmv_fusion,
20 d,
21 disable_latency_sched_heuristic,
22 disable_misched_load_clustering,
23 disable_misched_store_clustering,
24 disable_postmisched_load_clustering,
25 disable_postmisched_store_clustering,
26 dlen_factor_2,
27 e,
28 enable_vsetvli_sched_heuristic,
29 exact_asm,
30 experimental,
31 experimental_p,
32 experimental_rvm23u32,
33 experimental_smpmpmt,
34 experimental_svukte,
35 experimental_xrivosvisni,
36 experimental_xrivosvizip,
37 experimental_xsfmclic,
38 experimental_xsfsclic,
39 experimental_zibi,
40 experimental_zicfilp,
41 experimental_zicfiss,
42 experimental_zvbc32e,
43 experimental_zvfbfa,
44 experimental_zvfofp8min,
45 experimental_zvkgs,
46 experimental_zvqdotq,
47 f,
48 forced_atomics,
49 h,
50 i,
51 ld_add_fusion,
52 log_vrgather,
53 lui_addi_fusion,
54 lui_load_fusion,
55 m,
56 mips_p8700,
57 no_default_unroll,
58 no_sink_splat_operands,
59 no_trailing_seq_cst_fence,
60 optimized_nf2_segment_load_store,
61 optimized_nf3_segment_load_store,
62 optimized_nf4_segment_load_store,
63 optimized_nf5_segment_load_store,
64 optimized_nf6_segment_load_store,
65 optimized_nf7_segment_load_store,
66 optimized_nf8_segment_load_store,
67 optimized_zero_stride_load,
68 permissive_zalrsc,
69 predictable_select_expensive,
70 prefer_vsetvli_over_read_vlenb,
71 prefer_w_inst,
72 q,
73 relax,
74 reserve_x1,
75 reserve_x10,
76 reserve_x11,
77 reserve_x12,
78 reserve_x13,
79 reserve_x14,
80 reserve_x15,
81 reserve_x16,
82 reserve_x17,
83 reserve_x18,
84 reserve_x19,
85 reserve_x2,
86 reserve_x20,
87 reserve_x21,
88 reserve_x22,
89 reserve_x23,
90 reserve_x24,
91 reserve_x25,
92 reserve_x26,
93 reserve_x27,
94 reserve_x28,
95 reserve_x29,
96 reserve_x3,
97 reserve_x30,
98 reserve_x31,
99 reserve_x4,
100 reserve_x5,
101 reserve_x6,
102 reserve_x7,
103 reserve_x8,
104 reserve_x9,
105 rva20s64,
106 rva20u64,
107 rva22s64,
108 rva22u64,
109 rva23s64,
110 rva23u64,
111 rvb23s64,
112 rvb23u64,
113 rvi20u32,
114 rvi20u64,
115 save_restore,
116 sdext,
117 sdtrig,
118 sha,
119 shcounterenw,
120 shgatpa,
121 shifted_zextw_fusion,
122 shlcofideleg,
123 short_forward_branch_ialu,
124 short_forward_branch_iload,
125 short_forward_branch_iminmax,
126 short_forward_branch_imul,
127 shtvala,
128 shvsatpa,
129 shvstvala,
130 shvstvecd,
131 shxadd_load_fusion,
132 single_element_vec_fp64,
133 smaia,
134 smcdeleg,
135 smcntrpmf,
136 smcsrind,
137 smctr,
138 smdbltrp,
139 smepmp,
140 smmpm,
141 smnpm,
142 smrnmi,
143 smstateen,
144 ssaia,
145 ssccfg,
146 ssccptr,
147 sscofpmf,
148 sscounterenw,
149 sscsrind,
150 ssctr,
151 ssdbltrp,
152 ssnpm,
153 sspm,
154 ssqosid,
155 ssstateen,
156 ssstrict,
157 sstc,
158 sstvala,
159 sstvecd,
160 ssu64xl,
161 supm,
162 svade,
163 svadu,
164 svbare,
165 svinval,
166 svnapot,
167 svpbmt,
168 svvptc,
169 tagged_globals,
170 unaligned_scalar_mem,
171 unaligned_vector_mem,
172 use_postra_scheduler,
173 v,
174 ventana_veyron,
175 vl_dependent_latency,
176 vxrm_pipeline_flush,
177 xandesbfhcvt,
178 xandesperf,
179 xandesvbfhcvt,
180 xandesvdot,
181 xandesvpackfph,
182 xandesvsinth,
183 xandesvsintload,
184 xcvalu,
185 xcvbi,
186 xcvbitmanip,
187 xcvelw,
188 xcvmac,
189 xcvmem,
190 xcvsimd,
191 xmipscbop,
192 xmipscmov,
193 xmipsexectl,
194 xmipslsp,
195 xqccmp,
196 xqci,
197 xqcia,
198 xqciac,
199 xqcibi,
200 xqcibm,
201 xqcicli,
202 xqcicm,
203 xqcics,
204 xqcicsr,
205 xqciint,
206 xqciio,
207 xqcilb,
208 xqcili,
209 xqcilia,
210 xqcilo,
211 xqcilsm,
212 xqcisim,
213 xqcisls,
214 xqcisync,
215 xsfcease,
216 xsfmm128t,
217 xsfmm16t,
218 xsfmm32a16f,
219 xsfmm32a32f,
220 xsfmm32a8f,
221 xsfmm32a8i,
222 xsfmm32t,
223 xsfmm64a64f,
224 xsfmm64t,
225 xsfmmbase,
226 xsfvcp,
227 xsfvfbfexp16e,
228 xsfvfexp16e,
229 xsfvfexp32e,
230 xsfvfexpa,
231 xsfvfexpa64e,
232 xsfvfnrclipxfqf,
233 xsfvfwmaccqqq,
234 xsfvqmaccdod,
235 xsfvqmaccqoq,
236 xsifivecdiscarddlone,
237 xsifivecflushdlone,
238 xsmtvdot,
239 xtheadba,
240 xtheadbb,
241 xtheadbs,
242 xtheadcmo,
243 xtheadcondmov,
244 xtheadfmemidx,
245 xtheadmac,
246 xtheadmemidx,
247 xtheadmempair,
248 xtheadsync,
249 xtheadvdot,
250 xventanacondops,
251 xwchc,
252 za128rs,
253 za64rs,
254 zaamo,
255 zabha,
256 zacas,
257 zalasr,
258 zalrsc,
259 zama16b,
260 zawrs,
261 zba,
262 zbb,
263 zbc,
264 zbkb,
265 zbkc,
266 zbkx,
267 zbs,
268 zca,
269 zcb,
270 zcd,
271 zce,
272 zcf,
273 zclsd,
274 zcmop,
275 zcmp,
276 zcmt,
277 zdinx,
278 zexth_fusion,
279 zextw_fusion,
280 zfa,
281 zfbfmin,
282 zfh,
283 zfhmin,
284 zfinx,
285 zhinx,
286 zhinxmin,
287 zic64b,
288 zicbom,
289 zicbop,
290 zicboz,
291 ziccamoa,
292 ziccamoc,
293 ziccif,
294 zicclsm,
295 ziccrse,
296 zicntr,
297 zicond,
298 zicsr,
299 zifencei,
300 zihintntl,
301 zihintpause,
302 zihpm,
303 zilsd,
304 zilsd_4byte_align,
305 zimop,
306 zk,
307 zkn,
308 zknd,
309 zkne,
310 zknh,
311 zkr,
312 zks,
313 zksed,
314 zksh,
315 zkt,
316 zmmul,
317 ztso,
318 zvbb,
319 zvbc,
320 zve32f,
321 zve32x,
322 zve64d,
323 zve64f,
324 zve64x,
325 zvfbfmin,
326 zvfbfwma,
327 zvfh,
328 zvfhmin,
329 zvkb,
330 zvkg,
331 zvkn,
332 zvknc,
333 zvkned,
334 zvkng,
335 zvknha,
336 zvknhb,
337 zvks,
338 zvksc,
339 zvksed,
340 zvksg,
341 zvksh,
342 zvkt,
343 zvl1024b,
344 zvl128b,
345 zvl16384b,
346 zvl2048b,
347 zvl256b,
348 zvl32768b,
349 zvl32b,
350 zvl4096b,
351 zvl512b,
352 zvl64b,
353 zvl65536b,
354 zvl8192b,
355};
356
357pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
358pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
359pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
360pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
361
362pub const all_features = blk: {
363 @setEvalBranchQuota(2000);
364 const len = @typeInfo(Feature).@"enum".field_names.len;
365 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
366 var result: [len]CpuFeature = undefined;
367 result[@backingInt(Feature.@"32bit")] = .{
368 .llvm_name = "32bit",
369 .description = "Implements RV32",
370 .dependencies = featureSet(&[_]Feature{}),
371 };
372 result[@backingInt(Feature.@"64bit")] = .{
373 .llvm_name = "64bit",
374 .description = "Implements RV64",
375 .dependencies = featureSet(&[_]Feature{}),
376 };
377 result[@backingInt(Feature.a)] = .{
378 .llvm_name = "a",
379 .description = "'A' (Atomic Instructions)",
380 .dependencies = featureSet(&[_]Feature{
381 .zaamo,
382 .zalrsc,
383 }),
384 };
385 result[@backingInt(Feature.add_load_fusion)] = .{
386 .llvm_name = "add-load-fusion",
387 .description = "Enable ADD(.UW) + load macrofusion",
388 .dependencies = featureSet(&[_]Feature{}),
389 };
390 result[@backingInt(Feature.addi_load_fusion)] = .{
391 .llvm_name = "addi-load-fusion",
392 .description = "Enable ADDI + load macrofusion",
393 .dependencies = featureSet(&[_]Feature{}),
394 };
395 result[@backingInt(Feature.andes45)] = .{
396 .llvm_name = "andes45",
397 .description = "Andes 45-Series processors",
398 .dependencies = featureSet(&[_]Feature{}),
399 };
400 result[@backingInt(Feature.auipc_addi_fusion)] = .{
401 .llvm_name = "auipc-addi-fusion",
402 .description = "Enable AUIPC+ADDI macrofusion",
403 .dependencies = featureSet(&[_]Feature{}),
404 };
405 result[@backingInt(Feature.auipc_load_fusion)] = .{
406 .llvm_name = "auipc-load-fusion",
407 .description = "Enable AUIPC + load macrofusion",
408 .dependencies = featureSet(&[_]Feature{}),
409 };
410 result[@backingInt(Feature.b)] = .{
411 .llvm_name = "b",
412 .description = "'B' (the collection of the Zba, Zbb, Zbs extensions)",
413 .dependencies = featureSet(&[_]Feature{
414 .zba,
415 .zbb,
416 .zbs,
417 }),
418 };
419 result[@backingInt(Feature.bfext_fusion)] = .{
420 .llvm_name = "bfext-fusion",
421 .description = "Enable SLLI+SRLI (bitfield extract) macrofusion",
422 .dependencies = featureSet(&[_]Feature{}),
423 };
424 result[@backingInt(Feature.c)] = .{
425 .llvm_name = "c",
426 .description = "'C' (Compressed Instructions)",
427 .dependencies = featureSet(&[_]Feature{
428 .zca,
429 }),
430 };
431 result[@backingInt(Feature.conditional_cmv_fusion)] = .{
432 .llvm_name = "conditional-cmv-fusion",
433 .description = "Enable branch+c.mv fusion",
434 .dependencies = featureSet(&[_]Feature{}),
435 };
436 result[@backingInt(Feature.d)] = .{
437 .llvm_name = "d",
438 .description = "'D' (Double-Precision Floating-Point)",
439 .dependencies = featureSet(&[_]Feature{
440 .f,
441 }),
442 };
443 result[@backingInt(Feature.disable_latency_sched_heuristic)] = .{
444 .llvm_name = "disable-latency-sched-heuristic",
445 .description = "Disable latency scheduling heuristic",
446 .dependencies = featureSet(&[_]Feature{}),
447 };
448 result[@backingInt(Feature.disable_misched_load_clustering)] = .{
449 .llvm_name = "disable-misched-load-clustering",
450 .description = "Disable load clustering in the machine scheduler",
451 .dependencies = featureSet(&[_]Feature{}),
452 };
453 result[@backingInt(Feature.disable_misched_store_clustering)] = .{
454 .llvm_name = "disable-misched-store-clustering",
455 .description = "Disable store clustering in the machine scheduler",
456 .dependencies = featureSet(&[_]Feature{}),
457 };
458 result[@backingInt(Feature.disable_postmisched_load_clustering)] = .{
459 .llvm_name = "disable-postmisched-load-clustering",
460 .description = "Disable PostRA load clustering in the machine scheduler",
461 .dependencies = featureSet(&[_]Feature{}),
462 };
463 result[@backingInt(Feature.disable_postmisched_store_clustering)] = .{
464 .llvm_name = "disable-postmisched-store-clustering",
465 .description = "Disable PostRA store clustering in the machine scheduler",
466 .dependencies = featureSet(&[_]Feature{}),
467 };
468 result[@backingInt(Feature.dlen_factor_2)] = .{
469 .llvm_name = "dlen-factor-2",
470 .description = "Vector unit DLEN(data path width) is half of VLEN",
471 .dependencies = featureSet(&[_]Feature{}),
472 };
473 result[@backingInt(Feature.e)] = .{
474 .llvm_name = "e",
475 .description = "'E' (Embedded Instruction Set with 16 GPRs)",
476 .dependencies = featureSet(&[_]Feature{}),
477 };
478 result[@backingInt(Feature.enable_vsetvli_sched_heuristic)] = .{
479 .llvm_name = "enable-vsetvli-sched-heuristic",
480 .description = "Enable vsetvli-based scheduling heuristic",
481 .dependencies = featureSet(&[_]Feature{}),
482 };
483 result[@backingInt(Feature.exact_asm)] = .{
484 .llvm_name = "exact-asm",
485 .description = "Enable Exact Assembly (Disables Compression and Relaxation)",
486 .dependencies = featureSet(&[_]Feature{}),
487 };
488 result[@backingInt(Feature.experimental)] = .{
489 .llvm_name = "experimental",
490 .description = "Experimental intrinsics",
491 .dependencies = featureSet(&[_]Feature{}),
492 };
493 result[@backingInt(Feature.experimental_p)] = .{
494 .llvm_name = "experimental-p",
495 .description = "'P' ('Base P' (Packed SIMD))",
496 .dependencies = featureSet(&[_]Feature{}),
497 };
498 result[@backingInt(Feature.experimental_rvm23u32)] = .{
499 .llvm_name = "experimental-rvm23u32",
500 .description = "RISC-V experimental-rvm23u32 profile",
501 .dependencies = featureSet(&[_]Feature{
502 .@"32bit",
503 .b,
504 .i,
505 .m,
506 .zce,
507 .zcmop,
508 .zicbop,
509 .zicond,
510 .zihintntl,
511 .zihintpause,
512 .zimop,
513 }),
514 };
515 result[@backingInt(Feature.experimental_smpmpmt)] = .{
516 .llvm_name = "experimental-smpmpmt",
517 .description = "'Smpmpmt' (PMP-based Memory Types Extension)",
518 .dependencies = featureSet(&[_]Feature{}),
519 };
520 result[@backingInt(Feature.experimental_svukte)] = .{
521 .llvm_name = "experimental-svukte",
522 .description = "'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)",
523 .dependencies = featureSet(&[_]Feature{}),
524 };
525 result[@backingInt(Feature.experimental_xrivosvisni)] = .{
526 .llvm_name = "experimental-xrivosvisni",
527 .description = "'XRivosVisni' (Rivos Vector Integer Small New)",
528 .dependencies = featureSet(&[_]Feature{}),
529 };
530 result[@backingInt(Feature.experimental_xrivosvizip)] = .{
531 .llvm_name = "experimental-xrivosvizip",
532 .description = "'XRivosVizip' (Rivos Vector Register Zips)",
533 .dependencies = featureSet(&[_]Feature{}),
534 };
535 result[@backingInt(Feature.experimental_xsfmclic)] = .{
536 .llvm_name = "experimental-xsfmclic",
537 .description = "'XSfmclic' (SiFive CLIC Machine-mode CSRs)",
538 .dependencies = featureSet(&[_]Feature{}),
539 };
540 result[@backingInt(Feature.experimental_xsfsclic)] = .{
541 .llvm_name = "experimental-xsfsclic",
542 .description = "'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)",
543 .dependencies = featureSet(&[_]Feature{}),
544 };
545 result[@backingInt(Feature.experimental_zibi)] = .{
546 .llvm_name = "experimental-zibi",
547 .description = "'Zibi' (Branch with Immediate)",
548 .dependencies = featureSet(&[_]Feature{}),
549 };
550 result[@backingInt(Feature.experimental_zicfilp)] = .{
551 .llvm_name = "experimental-zicfilp",
552 .description = "'Zicfilp' (Landing pad)",
553 .dependencies = featureSet(&[_]Feature{
554 .zicsr,
555 }),
556 };
557 result[@backingInt(Feature.experimental_zicfiss)] = .{
558 .llvm_name = "experimental-zicfiss",
559 .description = "'Zicfiss' (Shadow stack)",
560 .dependencies = featureSet(&[_]Feature{
561 .zicsr,
562 .zimop,
563 }),
564 };
565 result[@backingInt(Feature.experimental_zvbc32e)] = .{
566 .llvm_name = "experimental-zvbc32e",
567 .description = "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)",
568 .dependencies = featureSet(&[_]Feature{
569 .zve32x,
570 }),
571 };
572 result[@backingInt(Feature.experimental_zvfbfa)] = .{
573 .llvm_name = "experimental-zvfbfa",
574 .description = "'Zvfbfa' (Additional BF16 vector compute support)",
575 .dependencies = featureSet(&[_]Feature{
576 .zfbfmin,
577 .zve32f,
578 }),
579 };
580 result[@backingInt(Feature.experimental_zvfofp8min)] = .{
581 .llvm_name = "experimental-zvfofp8min",
582 .description = "'Zvfofp8min' (Vector OFP8 Converts)",
583 .dependencies = featureSet(&[_]Feature{
584 .zve32f,
585 }),
586 };
587 result[@backingInt(Feature.experimental_zvkgs)] = .{
588 .llvm_name = "experimental-zvkgs",
589 .description = "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)",
590 .dependencies = featureSet(&[_]Feature{
591 .zvkg,
592 }),
593 };
594 result[@backingInt(Feature.experimental_zvqdotq)] = .{
595 .llvm_name = "experimental-zvqdotq",
596 .description = "'Zvqdotq' (Vector quad widening 4D Dot Product)",
597 .dependencies = featureSet(&[_]Feature{
598 .zve32x,
599 }),
600 };
601 result[@backingInt(Feature.f)] = .{
602 .llvm_name = "f",
603 .description = "'F' (Single-Precision Floating-Point)",
604 .dependencies = featureSet(&[_]Feature{
605 .zicsr,
606 }),
607 };
608 result[@backingInt(Feature.forced_atomics)] = .{
609 .llvm_name = "forced-atomics",
610 .description = "Assume that lock-free native-width atomics are available",
611 .dependencies = featureSet(&[_]Feature{}),
612 };
613 result[@backingInt(Feature.h)] = .{
614 .llvm_name = "h",
615 .description = "'H' (Hypervisor)",
616 .dependencies = featureSet(&[_]Feature{}),
617 };
618 result[@backingInt(Feature.i)] = .{
619 .llvm_name = "i",
620 .description = "'I' (Base Integer Instruction Set)",
621 .dependencies = featureSet(&[_]Feature{}),
622 };
623 result[@backingInt(Feature.ld_add_fusion)] = .{
624 .llvm_name = "ld-add-fusion",
625 .description = "Enable LD+ADD macrofusion",
626 .dependencies = featureSet(&[_]Feature{}),
627 };
628 result[@backingInt(Feature.log_vrgather)] = .{
629 .llvm_name = "log-vrgather",
630 .description = "Has vrgather.vv with LMUL*log2(LMUL) latency",
631 .dependencies = featureSet(&[_]Feature{}),
632 };
633 result[@backingInt(Feature.lui_addi_fusion)] = .{
634 .llvm_name = "lui-addi-fusion",
635 .description = "Enable LUI+ADDI macro fusion",
636 .dependencies = featureSet(&[_]Feature{}),
637 };
638 result[@backingInt(Feature.lui_load_fusion)] = .{
639 .llvm_name = "lui-load-fusion",
640 .description = "Enable LUI + load macrofusion",
641 .dependencies = featureSet(&[_]Feature{}),
642 };
643 result[@backingInt(Feature.m)] = .{
644 .llvm_name = "m",
645 .description = "'M' (Integer Multiplication and Division)",
646 .dependencies = featureSet(&[_]Feature{
647 .zmmul,
648 }),
649 };
650 result[@backingInt(Feature.mips_p8700)] = .{
651 .llvm_name = "mips-p8700",
652 .description = "MIPS p8700 processor",
653 .dependencies = featureSet(&[_]Feature{}),
654 };
655 result[@backingInt(Feature.no_default_unroll)] = .{
656 .llvm_name = "no-default-unroll",
657 .description = "Disable default unroll preference.",
658 .dependencies = featureSet(&[_]Feature{}),
659 };
660 result[@backingInt(Feature.no_sink_splat_operands)] = .{
661 .llvm_name = "no-sink-splat-operands",
662 .description = "Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions",
663 .dependencies = featureSet(&[_]Feature{}),
664 };
665 result[@backingInt(Feature.no_trailing_seq_cst_fence)] = .{
666 .llvm_name = "no-trailing-seq-cst-fence",
667 .description = "Disable trailing fence for seq-cst store.",
668 .dependencies = featureSet(&[_]Feature{}),
669 };
670 result[@backingInt(Feature.optimized_nf2_segment_load_store)] = .{
671 .llvm_name = "optimized-nf2-segment-load-store",
672 .description = "vlseg2eN.v and vsseg2eN.v are implemented as a wide memory op and shuffle",
673 .dependencies = featureSet(&[_]Feature{}),
674 };
675 result[@backingInt(Feature.optimized_nf3_segment_load_store)] = .{
676 .llvm_name = "optimized-nf3-segment-load-store",
677 .description = "vlseg3eN.v and vsseg3eN.v are implemented as a wide memory op and shuffle",
678 .dependencies = featureSet(&[_]Feature{}),
679 };
680 result[@backingInt(Feature.optimized_nf4_segment_load_store)] = .{
681 .llvm_name = "optimized-nf4-segment-load-store",
682 .description = "vlseg4eN.v and vsseg4eN.v are implemented as a wide memory op and shuffle",
683 .dependencies = featureSet(&[_]Feature{}),
684 };
685 result[@backingInt(Feature.optimized_nf5_segment_load_store)] = .{
686 .llvm_name = "optimized-nf5-segment-load-store",
687 .description = "vlseg5eN.v and vsseg5eN.v are implemented as a wide memory op and shuffle",
688 .dependencies = featureSet(&[_]Feature{}),
689 };
690 result[@backingInt(Feature.optimized_nf6_segment_load_store)] = .{
691 .llvm_name = "optimized-nf6-segment-load-store",
692 .description = "vlseg6eN.v and vsseg6eN.v are implemented as a wide memory op and shuffle",
693 .dependencies = featureSet(&[_]Feature{}),
694 };
695 result[@backingInt(Feature.optimized_nf7_segment_load_store)] = .{
696 .llvm_name = "optimized-nf7-segment-load-store",
697 .description = "vlseg7eN.v and vsseg7eN.v are implemented as a wide memory op and shuffle",
698 .dependencies = featureSet(&[_]Feature{}),
699 };
700 result[@backingInt(Feature.optimized_nf8_segment_load_store)] = .{
701 .llvm_name = "optimized-nf8-segment-load-store",
702 .description = "vlseg8eN.v and vsseg8eN.v are implemented as a wide memory op and shuffle",
703 .dependencies = featureSet(&[_]Feature{}),
704 };
705 result[@backingInt(Feature.optimized_zero_stride_load)] = .{
706 .llvm_name = "optimized-zero-stride-load",
707 .description = "Optimized (perform fewer memory operations)zero-stride vector load",
708 .dependencies = featureSet(&[_]Feature{}),
709 };
710 result[@backingInt(Feature.permissive_zalrsc)] = .{
711 .llvm_name = "permissive-zalrsc",
712 .description = "Implementation permits non-base instructions between LR/SC pairs",
713 .dependencies = featureSet(&[_]Feature{}),
714 };
715 result[@backingInt(Feature.predictable_select_expensive)] = .{
716 .llvm_name = "predictable-select-expensive",
717 .description = "Prefer likely predicted branches over selects",
718 .dependencies = featureSet(&[_]Feature{}),
719 };
720 result[@backingInt(Feature.prefer_vsetvli_over_read_vlenb)] = .{
721 .llvm_name = "prefer-vsetvli-over-read-vlenb",
722 .description = "Prefer vsetvli over read vlenb CSR to calculate VLEN",
723 .dependencies = featureSet(&[_]Feature{}),
724 };
725 result[@backingInt(Feature.prefer_w_inst)] = .{
726 .llvm_name = "prefer-w-inst",
727 .description = "Prefer instructions with W suffix",
728 .dependencies = featureSet(&[_]Feature{}),
729 };
730 result[@backingInt(Feature.q)] = .{
731 .llvm_name = "q",
732 .description = "'Q' (Quad-Precision Floating-Point)",
733 .dependencies = featureSet(&[_]Feature{
734 .d,
735 }),
736 };
737 result[@backingInt(Feature.relax)] = .{
738 .llvm_name = "relax",
739 .description = "Enable Linker relaxation.",
740 .dependencies = featureSet(&[_]Feature{}),
741 };
742 result[@backingInt(Feature.reserve_x1)] = .{
743 .llvm_name = "reserve-x1",
744 .description = "Reserve X1",
745 .dependencies = featureSet(&[_]Feature{}),
746 };
747 result[@backingInt(Feature.reserve_x10)] = .{
748 .llvm_name = "reserve-x10",
749 .description = "Reserve X10",
750 .dependencies = featureSet(&[_]Feature{}),
751 };
752 result[@backingInt(Feature.reserve_x11)] = .{
753 .llvm_name = "reserve-x11",
754 .description = "Reserve X11",
755 .dependencies = featureSet(&[_]Feature{}),
756 };
757 result[@backingInt(Feature.reserve_x12)] = .{
758 .llvm_name = "reserve-x12",
759 .description = "Reserve X12",
760 .dependencies = featureSet(&[_]Feature{}),
761 };
762 result[@backingInt(Feature.reserve_x13)] = .{
763 .llvm_name = "reserve-x13",
764 .description = "Reserve X13",
765 .dependencies = featureSet(&[_]Feature{}),
766 };
767 result[@backingInt(Feature.reserve_x14)] = .{
768 .llvm_name = "reserve-x14",
769 .description = "Reserve X14",
770 .dependencies = featureSet(&[_]Feature{}),
771 };
772 result[@backingInt(Feature.reserve_x15)] = .{
773 .llvm_name = "reserve-x15",
774 .description = "Reserve X15",
775 .dependencies = featureSet(&[_]Feature{}),
776 };
777 result[@backingInt(Feature.reserve_x16)] = .{
778 .llvm_name = "reserve-x16",
779 .description = "Reserve X16",
780 .dependencies = featureSet(&[_]Feature{}),
781 };
782 result[@backingInt(Feature.reserve_x17)] = .{
783 .llvm_name = "reserve-x17",
784 .description = "Reserve X17",
785 .dependencies = featureSet(&[_]Feature{}),
786 };
787 result[@backingInt(Feature.reserve_x18)] = .{
788 .llvm_name = "reserve-x18",
789 .description = "Reserve X18",
790 .dependencies = featureSet(&[_]Feature{}),
791 };
792 result[@backingInt(Feature.reserve_x19)] = .{
793 .llvm_name = "reserve-x19",
794 .description = "Reserve X19",
795 .dependencies = featureSet(&[_]Feature{}),
796 };
797 result[@backingInt(Feature.reserve_x2)] = .{
798 .llvm_name = "reserve-x2",
799 .description = "Reserve X2",
800 .dependencies = featureSet(&[_]Feature{}),
801 };
802 result[@backingInt(Feature.reserve_x20)] = .{
803 .llvm_name = "reserve-x20",
804 .description = "Reserve X20",
805 .dependencies = featureSet(&[_]Feature{}),
806 };
807 result[@backingInt(Feature.reserve_x21)] = .{
808 .llvm_name = "reserve-x21",
809 .description = "Reserve X21",
810 .dependencies = featureSet(&[_]Feature{}),
811 };
812 result[@backingInt(Feature.reserve_x22)] = .{
813 .llvm_name = "reserve-x22",
814 .description = "Reserve X22",
815 .dependencies = featureSet(&[_]Feature{}),
816 };
817 result[@backingInt(Feature.reserve_x23)] = .{
818 .llvm_name = "reserve-x23",
819 .description = "Reserve X23",
820 .dependencies = featureSet(&[_]Feature{}),
821 };
822 result[@backingInt(Feature.reserve_x24)] = .{
823 .llvm_name = "reserve-x24",
824 .description = "Reserve X24",
825 .dependencies = featureSet(&[_]Feature{}),
826 };
827 result[@backingInt(Feature.reserve_x25)] = .{
828 .llvm_name = "reserve-x25",
829 .description = "Reserve X25",
830 .dependencies = featureSet(&[_]Feature{}),
831 };
832 result[@backingInt(Feature.reserve_x26)] = .{
833 .llvm_name = "reserve-x26",
834 .description = "Reserve X26",
835 .dependencies = featureSet(&[_]Feature{}),
836 };
837 result[@backingInt(Feature.reserve_x27)] = .{
838 .llvm_name = "reserve-x27",
839 .description = "Reserve X27",
840 .dependencies = featureSet(&[_]Feature{}),
841 };
842 result[@backingInt(Feature.reserve_x28)] = .{
843 .llvm_name = "reserve-x28",
844 .description = "Reserve X28",
845 .dependencies = featureSet(&[_]Feature{}),
846 };
847 result[@backingInt(Feature.reserve_x29)] = .{
848 .llvm_name = "reserve-x29",
849 .description = "Reserve X29",
850 .dependencies = featureSet(&[_]Feature{}),
851 };
852 result[@backingInt(Feature.reserve_x3)] = .{
853 .llvm_name = "reserve-x3",
854 .description = "Reserve X3",
855 .dependencies = featureSet(&[_]Feature{}),
856 };
857 result[@backingInt(Feature.reserve_x30)] = .{
858 .llvm_name = "reserve-x30",
859 .description = "Reserve X30",
860 .dependencies = featureSet(&[_]Feature{}),
861 };
862 result[@backingInt(Feature.reserve_x31)] = .{
863 .llvm_name = "reserve-x31",
864 .description = "Reserve X31",
865 .dependencies = featureSet(&[_]Feature{}),
866 };
867 result[@backingInt(Feature.reserve_x4)] = .{
868 .llvm_name = "reserve-x4",
869 .description = "Reserve X4",
870 .dependencies = featureSet(&[_]Feature{}),
871 };
872 result[@backingInt(Feature.reserve_x5)] = .{
873 .llvm_name = "reserve-x5",
874 .description = "Reserve X5",
875 .dependencies = featureSet(&[_]Feature{}),
876 };
877 result[@backingInt(Feature.reserve_x6)] = .{
878 .llvm_name = "reserve-x6",
879 .description = "Reserve X6",
880 .dependencies = featureSet(&[_]Feature{}),
881 };
882 result[@backingInt(Feature.reserve_x7)] = .{
883 .llvm_name = "reserve-x7",
884 .description = "Reserve X7",
885 .dependencies = featureSet(&[_]Feature{}),
886 };
887 result[@backingInt(Feature.reserve_x8)] = .{
888 .llvm_name = "reserve-x8",
889 .description = "Reserve X8",
890 .dependencies = featureSet(&[_]Feature{}),
891 };
892 result[@backingInt(Feature.reserve_x9)] = .{
893 .llvm_name = "reserve-x9",
894 .description = "Reserve X9",
895 .dependencies = featureSet(&[_]Feature{}),
896 };
897 result[@backingInt(Feature.rva20s64)] = .{
898 .llvm_name = "rva20s64",
899 .description = "RISC-V rva20s64 profile",
900 .dependencies = featureSet(&[_]Feature{
901 .@"64bit",
902 .a,
903 .c,
904 .d,
905 .i,
906 .m,
907 .ssccptr,
908 .sstvala,
909 .sstvecd,
910 .svade,
911 .svbare,
912 .za128rs,
913 .ziccamoa,
914 .ziccif,
915 .zicclsm,
916 .ziccrse,
917 .zicntr,
918 .zifencei,
919 }),
920 };
921 result[@backingInt(Feature.rva20u64)] = .{
922 .llvm_name = "rva20u64",
923 .description = "RISC-V rva20u64 profile",
924 .dependencies = featureSet(&[_]Feature{
925 .@"64bit",
926 .a,
927 .c,
928 .d,
929 .i,
930 .m,
931 .za128rs,
932 .ziccamoa,
933 .ziccif,
934 .zicclsm,
935 .ziccrse,
936 .zicntr,
937 }),
938 };
939 result[@backingInt(Feature.rva22s64)] = .{
940 .llvm_name = "rva22s64",
941 .description = "RISC-V rva22s64 profile",
942 .dependencies = featureSet(&[_]Feature{
943 .@"64bit",
944 .a,
945 .b,
946 .c,
947 .d,
948 .i,
949 .m,
950 .ssccptr,
951 .sscounterenw,
952 .sstvala,
953 .sstvecd,
954 .svade,
955 .svbare,
956 .svinval,
957 .svpbmt,
958 .za64rs,
959 .zfhmin,
960 .zic64b,
961 .zicbom,
962 .zicbop,
963 .zicboz,
964 .ziccamoa,
965 .ziccif,
966 .zicclsm,
967 .ziccrse,
968 .zicntr,
969 .zifencei,
970 .zihintpause,
971 .zihpm,
972 .zkt,
973 }),
974 };
975 result[@backingInt(Feature.rva22u64)] = .{
976 .llvm_name = "rva22u64",
977 .description = "RISC-V rva22u64 profile",
978 .dependencies = featureSet(&[_]Feature{
979 .@"64bit",
980 .a,
981 .b,
982 .c,
983 .d,
984 .i,
985 .m,
986 .za64rs,
987 .zfhmin,
988 .zic64b,
989 .zicbom,
990 .zicbop,
991 .zicboz,
992 .ziccamoa,
993 .ziccif,
994 .zicclsm,
995 .ziccrse,
996 .zicntr,
997 .zihintpause,
998 .zihpm,
999 .zkt,
1000 }),
1001 };
1002 result[@backingInt(Feature.rva23s64)] = .{
1003 .llvm_name = "rva23s64",
1004 .description = "RISC-V rva23s64 profile",
1005 .dependencies = featureSet(&[_]Feature{
1006 .@"64bit",
1007 .a,
1008 .b,
1009 .c,
1010 .i,
1011 .m,
1012 .sha,
1013 .ssccptr,
1014 .sscofpmf,
1015 .sscounterenw,
1016 .ssnpm,
1017 .sstc,
1018 .sstvala,
1019 .sstvecd,
1020 .ssu64xl,
1021 .supm,
1022 .svade,
1023 .svbare,
1024 .svinval,
1025 .svnapot,
1026 .svpbmt,
1027 .v,
1028 .za64rs,
1029 .zawrs,
1030 .zcb,
1031 .zcmop,
1032 .zfa,
1033 .zfhmin,
1034 .zic64b,
1035 .zicbom,
1036 .zicbop,
1037 .zicboz,
1038 .ziccamoa,
1039 .ziccif,
1040 .zicclsm,
1041 .ziccrse,
1042 .zicntr,
1043 .zicond,
1044 .zifencei,
1045 .zihintntl,
1046 .zihintpause,
1047 .zihpm,
1048 .zimop,
1049 .zkt,
1050 .zvbb,
1051 .zvfhmin,
1052 .zvkt,
1053 }),
1054 };
1055 result[@backingInt(Feature.rva23u64)] = .{
1056 .llvm_name = "rva23u64",
1057 .description = "RISC-V rva23u64 profile",
1058 .dependencies = featureSet(&[_]Feature{
1059 .@"64bit",
1060 .a,
1061 .b,
1062 .c,
1063 .i,
1064 .m,
1065 .supm,
1066 .v,
1067 .za64rs,
1068 .zawrs,
1069 .zcb,
1070 .zcmop,
1071 .zfa,
1072 .zfhmin,
1073 .zic64b,
1074 .zicbom,
1075 .zicbop,
1076 .zicboz,
1077 .ziccamoa,
1078 .ziccif,
1079 .zicclsm,
1080 .ziccrse,
1081 .zicntr,
1082 .zicond,
1083 .zihintntl,
1084 .zihintpause,
1085 .zihpm,
1086 .zimop,
1087 .zkt,
1088 .zvbb,
1089 .zvfhmin,
1090 .zvkt,
1091 }),
1092 };
1093 result[@backingInt(Feature.rvb23s64)] = .{
1094 .llvm_name = "rvb23s64",
1095 .description = "RISC-V rvb23s64 profile",
1096 .dependencies = featureSet(&[_]Feature{
1097 .@"64bit",
1098 .a,
1099 .b,
1100 .c,
1101 .d,
1102 .i,
1103 .m,
1104 .ssccptr,
1105 .sscofpmf,
1106 .sscounterenw,
1107 .sstc,
1108 .sstvala,
1109 .sstvecd,
1110 .ssu64xl,
1111 .svade,
1112 .svbare,
1113 .svinval,
1114 .svnapot,
1115 .svpbmt,
1116 .za64rs,
1117 .zawrs,
1118 .zcb,
1119 .zcmop,
1120 .zfa,
1121 .zic64b,
1122 .zicbom,
1123 .zicbop,
1124 .zicboz,
1125 .ziccamoa,
1126 .ziccif,
1127 .zicclsm,
1128 .ziccrse,
1129 .zicntr,
1130 .zicond,
1131 .zifencei,
1132 .zihintntl,
1133 .zihintpause,
1134 .zihpm,
1135 .zimop,
1136 .zkt,
1137 }),
1138 };
1139 result[@backingInt(Feature.rvb23u64)] = .{
1140 .llvm_name = "rvb23u64",
1141 .description = "RISC-V rvb23u64 profile",
1142 .dependencies = featureSet(&[_]Feature{
1143 .@"64bit",
1144 .a,
1145 .b,
1146 .c,
1147 .d,
1148 .i,
1149 .m,
1150 .za64rs,
1151 .zawrs,
1152 .zcb,
1153 .zcmop,
1154 .zfa,
1155 .zic64b,
1156 .zicbom,
1157 .zicbop,
1158 .zicboz,
1159 .ziccamoa,
1160 .ziccif,
1161 .zicclsm,
1162 .ziccrse,
1163 .zicntr,
1164 .zicond,
1165 .zihintntl,
1166 .zihintpause,
1167 .zihpm,
1168 .zimop,
1169 .zkt,
1170 }),
1171 };
1172 result[@backingInt(Feature.rvi20u32)] = .{
1173 .llvm_name = "rvi20u32",
1174 .description = "RISC-V rvi20u32 profile",
1175 .dependencies = featureSet(&[_]Feature{
1176 .@"32bit",
1177 .i,
1178 }),
1179 };
1180 result[@backingInt(Feature.rvi20u64)] = .{
1181 .llvm_name = "rvi20u64",
1182 .description = "RISC-V rvi20u64 profile",
1183 .dependencies = featureSet(&[_]Feature{
1184 .@"64bit",
1185 .i,
1186 }),
1187 };
1188 result[@backingInt(Feature.save_restore)] = .{
1189 .llvm_name = "save-restore",
1190 .description = "Enable save/restore.",
1191 .dependencies = featureSet(&[_]Feature{}),
1192 };
1193 result[@backingInt(Feature.sdext)] = .{
1194 .llvm_name = "sdext",
1195 .description = "'Sdext' (External debugger)",
1196 .dependencies = featureSet(&[_]Feature{}),
1197 };
1198 result[@backingInt(Feature.sdtrig)] = .{
1199 .llvm_name = "sdtrig",
1200 .description = "'Sdtrig' (Debugger triggers)",
1201 .dependencies = featureSet(&[_]Feature{}),
1202 };
1203 result[@backingInt(Feature.sha)] = .{
1204 .llvm_name = "sha",
1205 .description = "'Sha' (Augmented Hypervisor)",
1206 .dependencies = featureSet(&[_]Feature{
1207 .h,
1208 .shcounterenw,
1209 .shgatpa,
1210 .shtvala,
1211 .shvsatpa,
1212 .shvstvala,
1213 .shvstvecd,
1214 .ssstateen,
1215 }),
1216 };
1217 result[@backingInt(Feature.shcounterenw)] = .{
1218 .llvm_name = "shcounterenw",
1219 .description = "'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)",
1220 .dependencies = featureSet(&[_]Feature{}),
1221 };
1222 result[@backingInt(Feature.shgatpa)] = .{
1223 .llvm_name = "shgatpa",
1224 .description = "'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)",
1225 .dependencies = featureSet(&[_]Feature{}),
1226 };
1227 result[@backingInt(Feature.shifted_zextw_fusion)] = .{
1228 .llvm_name = "shifted-zextw-fusion",
1229 .description = "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension",
1230 .dependencies = featureSet(&[_]Feature{}),
1231 };
1232 result[@backingInt(Feature.shlcofideleg)] = .{
1233 .llvm_name = "shlcofideleg",
1234 .description = "'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode)",
1235 .dependencies = featureSet(&[_]Feature{}),
1236 };
1237 result[@backingInt(Feature.short_forward_branch_ialu)] = .{
1238 .llvm_name = "short-forward-branch-ialu",
1239 .description = "Enable short forward branch optimization for RVI base instructions",
1240 .dependencies = featureSet(&[_]Feature{}),
1241 };
1242 result[@backingInt(Feature.short_forward_branch_iload)] = .{
1243 .llvm_name = "short-forward-branch-iload",
1244 .description = "Enable short forward branch optimization for load instructions",
1245 .dependencies = featureSet(&[_]Feature{
1246 .short_forward_branch_ialu,
1247 }),
1248 };
1249 result[@backingInt(Feature.short_forward_branch_iminmax)] = .{
1250 .llvm_name = "short-forward-branch-iminmax",
1251 .description = "Enable short forward branch optimization for MIN,MAX instructions in Zbb",
1252 .dependencies = featureSet(&[_]Feature{
1253 .short_forward_branch_ialu,
1254 }),
1255 };
1256 result[@backingInt(Feature.short_forward_branch_imul)] = .{
1257 .llvm_name = "short-forward-branch-imul",
1258 .description = "Enable short forward branch optimization for MUL instruction",
1259 .dependencies = featureSet(&[_]Feature{
1260 .short_forward_branch_ialu,
1261 }),
1262 };
1263 result[@backingInt(Feature.shtvala)] = .{
1264 .llvm_name = "shtvala",
1265 .description = "'Shtvala' (htval provides all needed values)",
1266 .dependencies = featureSet(&[_]Feature{}),
1267 };
1268 result[@backingInt(Feature.shvsatpa)] = .{
1269 .llvm_name = "shvsatpa",
1270 .description = "'Shvsatpa' (vsatp supports all modes supported by satp)",
1271 .dependencies = featureSet(&[_]Feature{}),
1272 };
1273 result[@backingInt(Feature.shvstvala)] = .{
1274 .llvm_name = "shvstvala",
1275 .description = "'Shvstvala' (vstval provides all needed values)",
1276 .dependencies = featureSet(&[_]Feature{}),
1277 };
1278 result[@backingInt(Feature.shvstvecd)] = .{
1279 .llvm_name = "shvstvecd",
1280 .description = "'Shvstvecd' (vstvec supports Direct mode)",
1281 .dependencies = featureSet(&[_]Feature{}),
1282 };
1283 result[@backingInt(Feature.shxadd_load_fusion)] = .{
1284 .llvm_name = "shxadd-load-fusion",
1285 .description = "Enable SH(1|2|3)ADD(.UW) + load macrofusion",
1286 .dependencies = featureSet(&[_]Feature{}),
1287 };
1288 result[@backingInt(Feature.single_element_vec_fp64)] = .{
1289 .llvm_name = "single-element-vec-fp64",
1290 .description = "Certain vector FP64 operations produce a single result element per cycle",
1291 .dependencies = featureSet(&[_]Feature{}),
1292 };
1293 result[@backingInt(Feature.smaia)] = .{
1294 .llvm_name = "smaia",
1295 .description = "'Smaia' (Advanced Interrupt Architecture Machine Level)",
1296 .dependencies = featureSet(&[_]Feature{}),
1297 };
1298 result[@backingInt(Feature.smcdeleg)] = .{
1299 .llvm_name = "smcdeleg",
1300 .description = "'Smcdeleg' (Counter Delegation Machine Level)",
1301 .dependencies = featureSet(&[_]Feature{}),
1302 };
1303 result[@backingInt(Feature.smcntrpmf)] = .{
1304 .llvm_name = "smcntrpmf",
1305 .description = "'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering)",
1306 .dependencies = featureSet(&[_]Feature{}),
1307 };
1308 result[@backingInt(Feature.smcsrind)] = .{
1309 .llvm_name = "smcsrind",
1310 .description = "'Smcsrind' (Indirect CSR Access Machine Level)",
1311 .dependencies = featureSet(&[_]Feature{}),
1312 };
1313 result[@backingInt(Feature.smctr)] = .{
1314 .llvm_name = "smctr",
1315 .description = "'Smctr' (Control Transfer Records Machine Level)",
1316 .dependencies = featureSet(&[_]Feature{
1317 .sscsrind,
1318 }),
1319 };
1320 result[@backingInt(Feature.smdbltrp)] = .{
1321 .llvm_name = "smdbltrp",
1322 .description = "'Smdbltrp' (Double Trap Machine Level)",
1323 .dependencies = featureSet(&[_]Feature{
1324 .zicsr,
1325 }),
1326 };
1327 result[@backingInt(Feature.smepmp)] = .{
1328 .llvm_name = "smepmp",
1329 .description = "'Smepmp' (Enhanced Physical Memory Protection)",
1330 .dependencies = featureSet(&[_]Feature{}),
1331 };
1332 result[@backingInt(Feature.smmpm)] = .{
1333 .llvm_name = "smmpm",
1334 .description = "'Smmpm' (Machine-level Pointer Masking for M-mode)",
1335 .dependencies = featureSet(&[_]Feature{}),
1336 };
1337 result[@backingInt(Feature.smnpm)] = .{
1338 .llvm_name = "smnpm",
1339 .description = "'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)",
1340 .dependencies = featureSet(&[_]Feature{}),
1341 };
1342 result[@backingInt(Feature.smrnmi)] = .{
1343 .llvm_name = "smrnmi",
1344 .description = "'Smrnmi' (Resumable Non-Maskable Interrupts)",
1345 .dependencies = featureSet(&[_]Feature{}),
1346 };
1347 result[@backingInt(Feature.smstateen)] = .{
1348 .llvm_name = "smstateen",
1349 .description = "'Smstateen' (Machine-mode view of the state-enable extension)",
1350 .dependencies = featureSet(&[_]Feature{}),
1351 };
1352 result[@backingInt(Feature.ssaia)] = .{
1353 .llvm_name = "ssaia",
1354 .description = "'Ssaia' (Advanced Interrupt Architecture Supervisor Level)",
1355 .dependencies = featureSet(&[_]Feature{}),
1356 };
1357 result[@backingInt(Feature.ssccfg)] = .{
1358 .llvm_name = "ssccfg",
1359 .description = "'Ssccfg' (Counter Configuration Supervisor Level)",
1360 .dependencies = featureSet(&[_]Feature{}),
1361 };
1362 result[@backingInt(Feature.ssccptr)] = .{
1363 .llvm_name = "ssccptr",
1364 .description = "'Ssccptr' (Main memory supports page table reads)",
1365 .dependencies = featureSet(&[_]Feature{}),
1366 };
1367 result[@backingInt(Feature.sscofpmf)] = .{
1368 .llvm_name = "sscofpmf",
1369 .description = "'Sscofpmf' (Count Overflow and Mode-Based Filtering)",
1370 .dependencies = featureSet(&[_]Feature{}),
1371 };
1372 result[@backingInt(Feature.sscounterenw)] = .{
1373 .llvm_name = "sscounterenw",
1374 .description = "'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)",
1375 .dependencies = featureSet(&[_]Feature{}),
1376 };
1377 result[@backingInt(Feature.sscsrind)] = .{
1378 .llvm_name = "sscsrind",
1379 .description = "'Sscsrind' (Indirect CSR Access Supervisor Level)",
1380 .dependencies = featureSet(&[_]Feature{}),
1381 };
1382 result[@backingInt(Feature.ssctr)] = .{
1383 .llvm_name = "ssctr",
1384 .description = "'Ssctr' (Control Transfer Records Supervisor Level)",
1385 .dependencies = featureSet(&[_]Feature{
1386 .sscsrind,
1387 }),
1388 };
1389 result[@backingInt(Feature.ssdbltrp)] = .{
1390 .llvm_name = "ssdbltrp",
1391 .description = "'Ssdbltrp' (Double Trap Supervisor Level)",
1392 .dependencies = featureSet(&[_]Feature{
1393 .zicsr,
1394 }),
1395 };
1396 result[@backingInt(Feature.ssnpm)] = .{
1397 .llvm_name = "ssnpm",
1398 .description = "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)",
1399 .dependencies = featureSet(&[_]Feature{}),
1400 };
1401 result[@backingInt(Feature.sspm)] = .{
1402 .llvm_name = "sspm",
1403 .description = "'Sspm' (Indicates Supervisor-mode Pointer Masking)",
1404 .dependencies = featureSet(&[_]Feature{}),
1405 };
1406 result[@backingInt(Feature.ssqosid)] = .{
1407 .llvm_name = "ssqosid",
1408 .description = "'Ssqosid' (Quality-of-Service (QoS) Identifiers)",
1409 .dependencies = featureSet(&[_]Feature{}),
1410 };
1411 result[@backingInt(Feature.ssstateen)] = .{
1412 .llvm_name = "ssstateen",
1413 .description = "'Ssstateen' (Supervisor-mode view of the state-enable extension)",
1414 .dependencies = featureSet(&[_]Feature{}),
1415 };
1416 result[@backingInt(Feature.ssstrict)] = .{
1417 .llvm_name = "ssstrict",
1418 .description = "'Ssstrict' (No non-conforming extensions are present)",
1419 .dependencies = featureSet(&[_]Feature{}),
1420 };
1421 result[@backingInt(Feature.sstc)] = .{
1422 .llvm_name = "sstc",
1423 .description = "'Sstc' (Supervisor-mode timer interrupts)",
1424 .dependencies = featureSet(&[_]Feature{}),
1425 };
1426 result[@backingInt(Feature.sstvala)] = .{
1427 .llvm_name = "sstvala",
1428 .description = "'Sstvala' (stval provides all needed values)",
1429 .dependencies = featureSet(&[_]Feature{}),
1430 };
1431 result[@backingInt(Feature.sstvecd)] = .{
1432 .llvm_name = "sstvecd",
1433 .description = "'Sstvecd' (stvec supports Direct mode)",
1434 .dependencies = featureSet(&[_]Feature{}),
1435 };
1436 result[@backingInt(Feature.ssu64xl)] = .{
1437 .llvm_name = "ssu64xl",
1438 .description = "'Ssu64xl' (UXLEN=64 supported)",
1439 .dependencies = featureSet(&[_]Feature{}),
1440 };
1441 result[@backingInt(Feature.supm)] = .{
1442 .llvm_name = "supm",
1443 .description = "'Supm' (Indicates User-mode Pointer Masking)",
1444 .dependencies = featureSet(&[_]Feature{}),
1445 };
1446 result[@backingInt(Feature.svade)] = .{
1447 .llvm_name = "svade",
1448 .description = "'Svade' (Raise exceptions on improper A/D bits)",
1449 .dependencies = featureSet(&[_]Feature{}),
1450 };
1451 result[@backingInt(Feature.svadu)] = .{
1452 .llvm_name = "svadu",
1453 .description = "'Svadu' (Hardware A/D updates)",
1454 .dependencies = featureSet(&[_]Feature{}),
1455 };
1456 result[@backingInt(Feature.svbare)] = .{
1457 .llvm_name = "svbare",
1458 .description = "'Svbare' (satp mode Bare supported)",
1459 .dependencies = featureSet(&[_]Feature{}),
1460 };
1461 result[@backingInt(Feature.svinval)] = .{
1462 .llvm_name = "svinval",
1463 .description = "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)",
1464 .dependencies = featureSet(&[_]Feature{}),
1465 };
1466 result[@backingInt(Feature.svnapot)] = .{
1467 .llvm_name = "svnapot",
1468 .description = "'Svnapot' (NAPOT Translation Contiguity)",
1469 .dependencies = featureSet(&[_]Feature{}),
1470 };
1471 result[@backingInt(Feature.svpbmt)] = .{
1472 .llvm_name = "svpbmt",
1473 .description = "'Svpbmt' (Page-Based Memory Types)",
1474 .dependencies = featureSet(&[_]Feature{}),
1475 };
1476 result[@backingInt(Feature.svvptc)] = .{
1477 .llvm_name = "svvptc",
1478 .description = "'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)",
1479 .dependencies = featureSet(&[_]Feature{}),
1480 };
1481 result[@backingInt(Feature.tagged_globals)] = .{
1482 .llvm_name = "tagged-globals",
1483 .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
1484 .dependencies = featureSet(&[_]Feature{}),
1485 };
1486 result[@backingInt(Feature.unaligned_scalar_mem)] = .{
1487 .llvm_name = "unaligned-scalar-mem",
1488 .description = "Has reasonably performant unaligned scalar loads and stores",
1489 .dependencies = featureSet(&[_]Feature{}),
1490 };
1491 result[@backingInt(Feature.unaligned_vector_mem)] = .{
1492 .llvm_name = "unaligned-vector-mem",
1493 .description = "Has reasonably performant unaligned vector loads and stores",
1494 .dependencies = featureSet(&[_]Feature{}),
1495 };
1496 result[@backingInt(Feature.use_postra_scheduler)] = .{
1497 .llvm_name = "use-postra-scheduler",
1498 .description = "Schedule again after register allocation",
1499 .dependencies = featureSet(&[_]Feature{}),
1500 };
1501 result[@backingInt(Feature.v)] = .{
1502 .llvm_name = "v",
1503 .description = "'V' (Vector Extension for Application Processors)",
1504 .dependencies = featureSet(&[_]Feature{
1505 .zve64d,
1506 .zvl128b,
1507 }),
1508 };
1509 result[@backingInt(Feature.ventana_veyron)] = .{
1510 .llvm_name = "ventana-veyron",
1511 .description = "Ventana Veyron-Series processors",
1512 .dependencies = featureSet(&[_]Feature{}),
1513 };
1514 result[@backingInt(Feature.vl_dependent_latency)] = .{
1515 .llvm_name = "vl-dependent-latency",
1516 .description = "Latency of vector instructions is dependent on the dynamic value of vl",
1517 .dependencies = featureSet(&[_]Feature{}),
1518 };
1519 result[@backingInt(Feature.vxrm_pipeline_flush)] = .{
1520 .llvm_name = "vxrm-pipeline-flush",
1521 .description = "VXRM writes causes pipeline flush",
1522 .dependencies = featureSet(&[_]Feature{}),
1523 };
1524 result[@backingInt(Feature.xandesbfhcvt)] = .{
1525 .llvm_name = "xandesbfhcvt",
1526 .description = "'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)",
1527 .dependencies = featureSet(&[_]Feature{
1528 .f,
1529 }),
1530 };
1531 result[@backingInt(Feature.xandesperf)] = .{
1532 .llvm_name = "xandesperf",
1533 .description = "'XAndesPerf' (Andes Performance Extension)",
1534 .dependencies = featureSet(&[_]Feature{}),
1535 };
1536 result[@backingInt(Feature.xandesvbfhcvt)] = .{
1537 .llvm_name = "xandesvbfhcvt",
1538 .description = "'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)",
1539 .dependencies = featureSet(&[_]Feature{
1540 .zve32f,
1541 }),
1542 };
1543 result[@backingInt(Feature.xandesvdot)] = .{
1544 .llvm_name = "xandesvdot",
1545 .description = "'XAndesVDot' (Andes Vector Dot Product Extension)",
1546 .dependencies = featureSet(&[_]Feature{
1547 .zve32x,
1548 }),
1549 };
1550 result[@backingInt(Feature.xandesvpackfph)] = .{
1551 .llvm_name = "xandesvpackfph",
1552 .description = "'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)",
1553 .dependencies = featureSet(&[_]Feature{
1554 .f,
1555 }),
1556 };
1557 result[@backingInt(Feature.xandesvsinth)] = .{
1558 .llvm_name = "xandesvsinth",
1559 .description = "'XAndesVSIntH' (Andes Vector Small INT Handling Extension)",
1560 .dependencies = featureSet(&[_]Feature{
1561 .zve32x,
1562 }),
1563 };
1564 result[@backingInt(Feature.xandesvsintload)] = .{
1565 .llvm_name = "xandesvsintload",
1566 .description = "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)",
1567 .dependencies = featureSet(&[_]Feature{
1568 .zve32x,
1569 }),
1570 };
1571 result[@backingInt(Feature.xcvalu)] = .{
1572 .llvm_name = "xcvalu",
1573 .description = "'XCValu' (CORE-V ALU Operations)",
1574 .dependencies = featureSet(&[_]Feature{}),
1575 };
1576 result[@backingInt(Feature.xcvbi)] = .{
1577 .llvm_name = "xcvbi",
1578 .description = "'XCVbi' (CORE-V Immediate Branching)",
1579 .dependencies = featureSet(&[_]Feature{}),
1580 };
1581 result[@backingInt(Feature.xcvbitmanip)] = .{
1582 .llvm_name = "xcvbitmanip",
1583 .description = "'XCVbitmanip' (CORE-V Bit Manipulation)",
1584 .dependencies = featureSet(&[_]Feature{}),
1585 };
1586 result[@backingInt(Feature.xcvelw)] = .{
1587 .llvm_name = "xcvelw",
1588 .description = "'XCVelw' (CORE-V Event Load Word)",
1589 .dependencies = featureSet(&[_]Feature{}),
1590 };
1591 result[@backingInt(Feature.xcvmac)] = .{
1592 .llvm_name = "xcvmac",
1593 .description = "'XCVmac' (CORE-V Multiply-Accumulate)",
1594 .dependencies = featureSet(&[_]Feature{}),
1595 };
1596 result[@backingInt(Feature.xcvmem)] = .{
1597 .llvm_name = "xcvmem",
1598 .description = "'XCVmem' (CORE-V Post-incrementing Load & Store)",
1599 .dependencies = featureSet(&[_]Feature{}),
1600 };
1601 result[@backingInt(Feature.xcvsimd)] = .{
1602 .llvm_name = "xcvsimd",
1603 .description = "'XCVsimd' (CORE-V SIMD ALU)",
1604 .dependencies = featureSet(&[_]Feature{}),
1605 };
1606 result[@backingInt(Feature.xmipscbop)] = .{
1607 .llvm_name = "xmipscbop",
1608 .description = "'XMIPSCBOP' (MIPS Software Prefetch)",
1609 .dependencies = featureSet(&[_]Feature{}),
1610 };
1611 result[@backingInt(Feature.xmipscmov)] = .{
1612 .llvm_name = "xmipscmov",
1613 .description = "'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))",
1614 .dependencies = featureSet(&[_]Feature{}),
1615 };
1616 result[@backingInt(Feature.xmipsexectl)] = .{
1617 .llvm_name = "xmipsexectl",
1618 .description = "'XMIPSEXECTL' (MIPS execution control)",
1619 .dependencies = featureSet(&[_]Feature{}),
1620 };
1621 result[@backingInt(Feature.xmipslsp)] = .{
1622 .llvm_name = "xmipslsp",
1623 .description = "'XMIPSLSP' (MIPS optimization for hardware load-store bonding)",
1624 .dependencies = featureSet(&[_]Feature{}),
1625 };
1626 result[@backingInt(Feature.xqccmp)] = .{
1627 .llvm_name = "xqccmp",
1628 .description = "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)",
1629 .dependencies = featureSet(&[_]Feature{
1630 .zca,
1631 }),
1632 };
1633 result[@backingInt(Feature.xqci)] = .{
1634 .llvm_name = "xqci",
1635 .description = "'Xqci' (Qualcomm uC Extension)",
1636 .dependencies = featureSet(&[_]Feature{
1637 .xqcia,
1638 .xqciac,
1639 .xqcibi,
1640 .xqcibm,
1641 .xqcicli,
1642 .xqcicm,
1643 .xqcics,
1644 .xqcicsr,
1645 .xqciint,
1646 .xqciio,
1647 .xqcilb,
1648 .xqcili,
1649 .xqcilia,
1650 .xqcilo,
1651 .xqcilsm,
1652 .xqcisim,
1653 .xqcisls,
1654 .xqcisync,
1655 }),
1656 };
1657 result[@backingInt(Feature.xqcia)] = .{
1658 .llvm_name = "xqcia",
1659 .description = "'Xqcia' (Qualcomm uC Arithmetic Extension)",
1660 .dependencies = featureSet(&[_]Feature{}),
1661 };
1662 result[@backingInt(Feature.xqciac)] = .{
1663 .llvm_name = "xqciac",
1664 .description = "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)",
1665 .dependencies = featureSet(&[_]Feature{
1666 .zca,
1667 }),
1668 };
1669 result[@backingInt(Feature.xqcibi)] = .{
1670 .llvm_name = "xqcibi",
1671 .description = "'Xqcibi' (Qualcomm uC Branch Immediate Extension)",
1672 .dependencies = featureSet(&[_]Feature{
1673 .zca,
1674 }),
1675 };
1676 result[@backingInt(Feature.xqcibm)] = .{
1677 .llvm_name = "xqcibm",
1678 .description = "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)",
1679 .dependencies = featureSet(&[_]Feature{
1680 .zca,
1681 }),
1682 };
1683 result[@backingInt(Feature.xqcicli)] = .{
1684 .llvm_name = "xqcicli",
1685 .description = "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)",
1686 .dependencies = featureSet(&[_]Feature{}),
1687 };
1688 result[@backingInt(Feature.xqcicm)] = .{
1689 .llvm_name = "xqcicm",
1690 .description = "'Xqcicm' (Qualcomm uC Conditional Move Extension)",
1691 .dependencies = featureSet(&[_]Feature{
1692 .zca,
1693 }),
1694 };
1695 result[@backingInt(Feature.xqcics)] = .{
1696 .llvm_name = "xqcics",
1697 .description = "'Xqcics' (Qualcomm uC Conditional Select Extension)",
1698 .dependencies = featureSet(&[_]Feature{}),
1699 };
1700 result[@backingInt(Feature.xqcicsr)] = .{
1701 .llvm_name = "xqcicsr",
1702 .description = "'Xqcicsr' (Qualcomm uC CSR Extension)",
1703 .dependencies = featureSet(&[_]Feature{}),
1704 };
1705 result[@backingInt(Feature.xqciint)] = .{
1706 .llvm_name = "xqciint",
1707 .description = "'Xqciint' (Qualcomm uC Interrupts Extension)",
1708 .dependencies = featureSet(&[_]Feature{
1709 .zca,
1710 }),
1711 };
1712 result[@backingInt(Feature.xqciio)] = .{
1713 .llvm_name = "xqciio",
1714 .description = "'Xqciio' (Qualcomm uC External Input Output Extension)",
1715 .dependencies = featureSet(&[_]Feature{}),
1716 };
1717 result[@backingInt(Feature.xqcilb)] = .{
1718 .llvm_name = "xqcilb",
1719 .description = "'Xqcilb' (Qualcomm uC Long Branch Extension)",
1720 .dependencies = featureSet(&[_]Feature{
1721 .zca,
1722 }),
1723 };
1724 result[@backingInt(Feature.xqcili)] = .{
1725 .llvm_name = "xqcili",
1726 .description = "'Xqcili' (Qualcomm uC Load Large Immediate Extension)",
1727 .dependencies = featureSet(&[_]Feature{
1728 .zca,
1729 }),
1730 };
1731 result[@backingInt(Feature.xqcilia)] = .{
1732 .llvm_name = "xqcilia",
1733 .description = "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)",
1734 .dependencies = featureSet(&[_]Feature{
1735 .zca,
1736 }),
1737 };
1738 result[@backingInt(Feature.xqcilo)] = .{
1739 .llvm_name = "xqcilo",
1740 .description = "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)",
1741 .dependencies = featureSet(&[_]Feature{
1742 .zca,
1743 }),
1744 };
1745 result[@backingInt(Feature.xqcilsm)] = .{
1746 .llvm_name = "xqcilsm",
1747 .description = "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)",
1748 .dependencies = featureSet(&[_]Feature{}),
1749 };
1750 result[@backingInt(Feature.xqcisim)] = .{
1751 .llvm_name = "xqcisim",
1752 .description = "'Xqcisim' (Qualcomm uC Simulation Hint Extension)",
1753 .dependencies = featureSet(&[_]Feature{
1754 .zca,
1755 }),
1756 };
1757 result[@backingInt(Feature.xqcisls)] = .{
1758 .llvm_name = "xqcisls",
1759 .description = "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)",
1760 .dependencies = featureSet(&[_]Feature{}),
1761 };
1762 result[@backingInt(Feature.xqcisync)] = .{
1763 .llvm_name = "xqcisync",
1764 .description = "'Xqcisync' (Qualcomm uC Sync Delay Extension)",
1765 .dependencies = featureSet(&[_]Feature{
1766 .zca,
1767 }),
1768 };
1769 result[@backingInt(Feature.xsfcease)] = .{
1770 .llvm_name = "xsfcease",
1771 .description = "'XSfcease' (SiFive sf.cease Instruction)",
1772 .dependencies = featureSet(&[_]Feature{}),
1773 };
1774 result[@backingInt(Feature.xsfmm128t)] = .{
1775 .llvm_name = "xsfmm128t",
1776 .description = "'XSfmm128t' (TE=128 configuration)",
1777 .dependencies = featureSet(&[_]Feature{
1778 .xsfmmbase,
1779 .zvl512b,
1780 }),
1781 };
1782 result[@backingInt(Feature.xsfmm16t)] = .{
1783 .llvm_name = "xsfmm16t",
1784 .description = "'XSfmm16t' (TE=16 configuration)",
1785 .dependencies = featureSet(&[_]Feature{
1786 .xsfmmbase,
1787 .zvl64b,
1788 }),
1789 };
1790 result[@backingInt(Feature.xsfmm32a16f)] = .{
1791 .llvm_name = "xsfmm32a16f",
1792 .description = "'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF))",
1793 .dependencies = featureSet(&[_]Feature{
1794 .xsfmmbase,
1795 .zve32f,
1796 }),
1797 };
1798 result[@backingInt(Feature.xsfmm32a32f)] = .{
1799 .llvm_name = "xsfmm32a32f",
1800 .description = "'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b)",
1801 .dependencies = featureSet(&[_]Feature{
1802 .xsfmmbase,
1803 .zve32f,
1804 }),
1805 };
1806 result[@backingInt(Feature.xsfmm32a8f)] = .{
1807 .llvm_name = "xsfmm32a8f",
1808 .description = "'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8)",
1809 .dependencies = featureSet(&[_]Feature{
1810 .xsfmmbase,
1811 .zve32f,
1812 }),
1813 };
1814 result[@backingInt(Feature.xsfmm32a8i)] = .{
1815 .llvm_name = "xsfmm32a8i",
1816 .description = "'XSfmm32a8i' (TEW=32-bit accumulation, operands - int: 8b)",
1817 .dependencies = featureSet(&[_]Feature{
1818 .xsfmmbase,
1819 }),
1820 };
1821 result[@backingInt(Feature.xsfmm32t)] = .{
1822 .llvm_name = "xsfmm32t",
1823 .description = "'XSfmm32t' (TE=32 configuration)",
1824 .dependencies = featureSet(&[_]Feature{
1825 .xsfmmbase,
1826 .zvl128b,
1827 }),
1828 };
1829 result[@backingInt(Feature.xsfmm64a64f)] = .{
1830 .llvm_name = "xsfmm64a64f",
1831 .description = "'XSfmm64a64f' (TEW=64-bit accumulation, operands - float: fp64)",
1832 .dependencies = featureSet(&[_]Feature{
1833 .xsfmmbase,
1834 .zve64d,
1835 }),
1836 };
1837 result[@backingInt(Feature.xsfmm64t)] = .{
1838 .llvm_name = "xsfmm64t",
1839 .description = "'XSfmm64t' (TE=64 configuration)",
1840 .dependencies = featureSet(&[_]Feature{
1841 .xsfmmbase,
1842 .zvl256b,
1843 }),
1844 };
1845 result[@backingInt(Feature.xsfmmbase)] = .{
1846 .llvm_name = "xsfmmbase",
1847 .description = "'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero)",
1848 .dependencies = featureSet(&[_]Feature{
1849 .zve32x,
1850 }),
1851 };
1852 result[@backingInt(Feature.xsfvcp)] = .{
1853 .llvm_name = "xsfvcp",
1854 .description = "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
1855 .dependencies = featureSet(&[_]Feature{
1856 .zve32x,
1857 }),
1858 };
1859 result[@backingInt(Feature.xsfvfbfexp16e)] = .{
1860 .llvm_name = "xsfvfbfexp16e",
1861 .description = "'XSfvfbfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, BFloat16)",
1862 .dependencies = featureSet(&[_]Feature{}),
1863 };
1864 result[@backingInt(Feature.xsfvfexp16e)] = .{
1865 .llvm_name = "xsfvfexp16e",
1866 .description = "'XSfvfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, Half Precision)",
1867 .dependencies = featureSet(&[_]Feature{
1868 .zvfh,
1869 }),
1870 };
1871 result[@backingInt(Feature.xsfvfexp32e)] = .{
1872 .llvm_name = "xsfvfexp32e",
1873 .description = "'XSfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction, Single Precision)",
1874 .dependencies = featureSet(&[_]Feature{
1875 .zve32f,
1876 }),
1877 };
1878 result[@backingInt(Feature.xsfvfexpa)] = .{
1879 .llvm_name = "xsfvfexpa",
1880 .description = "'XSfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)",
1881 .dependencies = featureSet(&[_]Feature{
1882 .zve32f,
1883 }),
1884 };
1885 result[@backingInt(Feature.xsfvfexpa64e)] = .{
1886 .llvm_name = "xsfvfexpa64e",
1887 .description = "'XSfvfexpa64e' (SiFive Vector Floating-Point Exponential Approximation Instruction with Double-Precision)",
1888 .dependencies = featureSet(&[_]Feature{
1889 .xsfvfexpa,
1890 .zve64d,
1891 }),
1892 };
1893 result[@backingInt(Feature.xsfvfnrclipxfqf)] = .{
1894 .llvm_name = "xsfvfnrclipxfqf",
1895 .description = "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)",
1896 .dependencies = featureSet(&[_]Feature{
1897 .zve32f,
1898 }),
1899 };
1900 result[@backingInt(Feature.xsfvfwmaccqqq)] = .{
1901 .llvm_name = "xsfvfwmaccqqq",
1902 .description = "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))",
1903 .dependencies = featureSet(&[_]Feature{
1904 .zvfbfmin,
1905 .zvl128b,
1906 }),
1907 };
1908 result[@backingInt(Feature.xsfvqmaccdod)] = .{
1909 .llvm_name = "xsfvqmaccdod",
1910 .description = "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
1911 .dependencies = featureSet(&[_]Feature{
1912 .zve32x,
1913 .zvl128b,
1914 }),
1915 };
1916 result[@backingInt(Feature.xsfvqmaccqoq)] = .{
1917 .llvm_name = "xsfvqmaccqoq",
1918 .description = "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",
1919 .dependencies = featureSet(&[_]Feature{
1920 .zve32x,
1921 .zvl256b,
1922 }),
1923 };
1924 result[@backingInt(Feature.xsifivecdiscarddlone)] = .{
1925 .llvm_name = "xsifivecdiscarddlone",
1926 .description = "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)",
1927 .dependencies = featureSet(&[_]Feature{}),
1928 };
1929 result[@backingInt(Feature.xsifivecflushdlone)] = .{
1930 .llvm_name = "xsifivecflushdlone",
1931 .description = "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)",
1932 .dependencies = featureSet(&[_]Feature{}),
1933 };
1934 result[@backingInt(Feature.xsmtvdot)] = .{
1935 .llvm_name = "xsmtvdot",
1936 .description = "'XSMTVDot' (SpacemiT Vector Dot Product Extension)",
1937 .dependencies = featureSet(&[_]Feature{
1938 .zve32f,
1939 }),
1940 };
1941 result[@backingInt(Feature.xtheadba)] = .{
1942 .llvm_name = "xtheadba",
1943 .description = "'XTHeadBa' (T-Head address calculation instructions)",
1944 .dependencies = featureSet(&[_]Feature{}),
1945 };
1946 result[@backingInt(Feature.xtheadbb)] = .{
1947 .llvm_name = "xtheadbb",
1948 .description = "'XTHeadBb' (T-Head basic bit-manipulation instructions)",
1949 .dependencies = featureSet(&[_]Feature{}),
1950 };
1951 result[@backingInt(Feature.xtheadbs)] = .{
1952 .llvm_name = "xtheadbs",
1953 .description = "'XTHeadBs' (T-Head single-bit instructions)",
1954 .dependencies = featureSet(&[_]Feature{}),
1955 };
1956 result[@backingInt(Feature.xtheadcmo)] = .{
1957 .llvm_name = "xtheadcmo",
1958 .description = "'XTHeadCmo' (T-Head cache management instructions)",
1959 .dependencies = featureSet(&[_]Feature{}),
1960 };
1961 result[@backingInt(Feature.xtheadcondmov)] = .{
1962 .llvm_name = "xtheadcondmov",
1963 .description = "'XTHeadCondMov' (T-Head conditional move instructions)",
1964 .dependencies = featureSet(&[_]Feature{}),
1965 };
1966 result[@backingInt(Feature.xtheadfmemidx)] = .{
1967 .llvm_name = "xtheadfmemidx",
1968 .description = "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)",
1969 .dependencies = featureSet(&[_]Feature{}),
1970 };
1971 result[@backingInt(Feature.xtheadmac)] = .{
1972 .llvm_name = "xtheadmac",
1973 .description = "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)",
1974 .dependencies = featureSet(&[_]Feature{}),
1975 };
1976 result[@backingInt(Feature.xtheadmemidx)] = .{
1977 .llvm_name = "xtheadmemidx",
1978 .description = "'XTHeadMemIdx' (T-Head Indexed Memory Operations)",
1979 .dependencies = featureSet(&[_]Feature{}),
1980 };
1981 result[@backingInt(Feature.xtheadmempair)] = .{
1982 .llvm_name = "xtheadmempair",
1983 .description = "'XTHeadMemPair' (T-Head two-GPR Memory Operations)",
1984 .dependencies = featureSet(&[_]Feature{}),
1985 };
1986 result[@backingInt(Feature.xtheadsync)] = .{
1987 .llvm_name = "xtheadsync",
1988 .description = "'XTHeadSync' (T-Head multicore synchronization instructions)",
1989 .dependencies = featureSet(&[_]Feature{}),
1990 };
1991 result[@backingInt(Feature.xtheadvdot)] = .{
1992 .llvm_name = "xtheadvdot",
1993 .description = "'XTHeadVdot' (T-Head Vector Extensions for Dot)",
1994 .dependencies = featureSet(&[_]Feature{
1995 .v,
1996 }),
1997 };
1998 result[@backingInt(Feature.xventanacondops)] = .{
1999 .llvm_name = "xventanacondops",
2000 .description = "'XVentanaCondOps' (Ventana Conditional Ops)",
2001 .dependencies = featureSet(&[_]Feature{}),
2002 };
2003 result[@backingInt(Feature.xwchc)] = .{
2004 .llvm_name = "xwchc",
2005 .description = "'Xwchc' (WCH/QingKe additional compressed opcodes)",
2006 .dependencies = featureSet(&[_]Feature{
2007 .zca,
2008 }),
2009 };
2010 result[@backingInt(Feature.za128rs)] = .{
2011 .llvm_name = "za128rs",
2012 .description = "'Za128rs' (Reservation Set Size of at Most 128 Bytes)",
2013 .dependencies = featureSet(&[_]Feature{}),
2014 };
2015 result[@backingInt(Feature.za64rs)] = .{
2016 .llvm_name = "za64rs",
2017 .description = "'Za64rs' (Reservation Set Size of at Most 64 Bytes)",
2018 .dependencies = featureSet(&[_]Feature{}),
2019 };
2020 result[@backingInt(Feature.zaamo)] = .{
2021 .llvm_name = "zaamo",
2022 .description = "'Zaamo' (Atomic Memory Operations)",
2023 .dependencies = featureSet(&[_]Feature{}),
2024 };
2025 result[@backingInt(Feature.zabha)] = .{
2026 .llvm_name = "zabha",
2027 .description = "'Zabha' (Byte and Halfword Atomic Memory Operations)",
2028 .dependencies = featureSet(&[_]Feature{
2029 .zaamo,
2030 }),
2031 };
2032 result[@backingInt(Feature.zacas)] = .{
2033 .llvm_name = "zacas",
2034 .description = "'Zacas' (Atomic Compare-And-Swap Instructions)",
2035 .dependencies = featureSet(&[_]Feature{
2036 .zaamo,
2037 }),
2038 };
2039 result[@backingInt(Feature.zalasr)] = .{
2040 .llvm_name = "zalasr",
2041 .description = "'Zalasr' (Load-Acquire and Store-Release Instructions)",
2042 .dependencies = featureSet(&[_]Feature{}),
2043 };
2044 result[@backingInt(Feature.zalrsc)] = .{
2045 .llvm_name = "zalrsc",
2046 .description = "'Zalrsc' (Load-Reserved/Store-Conditional)",
2047 .dependencies = featureSet(&[_]Feature{}),
2048 };
2049 result[@backingInt(Feature.zama16b)] = .{
2050 .llvm_name = "zama16b",
2051 .description = "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)",
2052 .dependencies = featureSet(&[_]Feature{}),
2053 };
2054 result[@backingInt(Feature.zawrs)] = .{
2055 .llvm_name = "zawrs",
2056 .description = "'Zawrs' (Wait on Reservation Set)",
2057 .dependencies = featureSet(&[_]Feature{}),
2058 };
2059 result[@backingInt(Feature.zba)] = .{
2060 .llvm_name = "zba",
2061 .description = "'Zba' (Address Generation Instructions)",
2062 .dependencies = featureSet(&[_]Feature{}),
2063 };
2064 result[@backingInt(Feature.zbb)] = .{
2065 .llvm_name = "zbb",
2066 .description = "'Zbb' (Basic Bit-Manipulation)",
2067 .dependencies = featureSet(&[_]Feature{}),
2068 };
2069 result[@backingInt(Feature.zbc)] = .{
2070 .llvm_name = "zbc",
2071 .description = "'Zbc' (Carry-Less Multiplication)",
2072 .dependencies = featureSet(&[_]Feature{}),
2073 };
2074 result[@backingInt(Feature.zbkb)] = .{
2075 .llvm_name = "zbkb",
2076 .description = "'Zbkb' (Bitmanip instructions for Cryptography)",
2077 .dependencies = featureSet(&[_]Feature{}),
2078 };
2079 result[@backingInt(Feature.zbkc)] = .{
2080 .llvm_name = "zbkc",
2081 .description = "'Zbkc' (Carry-less multiply instructions for Cryptography)",
2082 .dependencies = featureSet(&[_]Feature{}),
2083 };
2084 result[@backingInt(Feature.zbkx)] = .{
2085 .llvm_name = "zbkx",
2086 .description = "'Zbkx' (Crossbar permutation instructions)",
2087 .dependencies = featureSet(&[_]Feature{}),
2088 };
2089 result[@backingInt(Feature.zbs)] = .{
2090 .llvm_name = "zbs",
2091 .description = "'Zbs' (Single-Bit Instructions)",
2092 .dependencies = featureSet(&[_]Feature{}),
2093 };
2094 result[@backingInt(Feature.zca)] = .{
2095 .llvm_name = "zca",
2096 .description = "'Zca' (part of the C extension, excluding compressed floating point loads/stores)",
2097 .dependencies = featureSet(&[_]Feature{}),
2098 };
2099 result[@backingInt(Feature.zcb)] = .{
2100 .llvm_name = "zcb",
2101 .description = "'Zcb' (Compressed basic bit manipulation instructions)",
2102 .dependencies = featureSet(&[_]Feature{
2103 .zca,
2104 }),
2105 };
2106 result[@backingInt(Feature.zcd)] = .{
2107 .llvm_name = "zcd",
2108 .description = "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
2109 .dependencies = featureSet(&[_]Feature{
2110 .d,
2111 .zca,
2112 }),
2113 };
2114 result[@backingInt(Feature.zce)] = .{
2115 .llvm_name = "zce",
2116 .description = "'Zce' (Compressed extensions for microcontrollers)",
2117 .dependencies = featureSet(&[_]Feature{
2118 .zcb,
2119 .zcmp,
2120 .zcmt,
2121 }),
2122 };
2123 result[@backingInt(Feature.zcf)] = .{
2124 .llvm_name = "zcf",
2125 .description = "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
2126 .dependencies = featureSet(&[_]Feature{
2127 .f,
2128 .zca,
2129 }),
2130 };
2131 result[@backingInt(Feature.zclsd)] = .{
2132 .llvm_name = "zclsd",
2133 .description = "'Zclsd' (Compressed Load/Store Pair Instructions)",
2134 .dependencies = featureSet(&[_]Feature{
2135 .zca,
2136 .zilsd,
2137 }),
2138 };
2139 result[@backingInt(Feature.zcmop)] = .{
2140 .llvm_name = "zcmop",
2141 .description = "'Zcmop' (Compressed May-Be-Operations)",
2142 .dependencies = featureSet(&[_]Feature{
2143 .zca,
2144 }),
2145 };
2146 result[@backingInt(Feature.zcmp)] = .{
2147 .llvm_name = "zcmp",
2148 .description = "'Zcmp' (sequenced instructions for code-size reduction)",
2149 .dependencies = featureSet(&[_]Feature{
2150 .zca,
2151 }),
2152 };
2153 result[@backingInt(Feature.zcmt)] = .{
2154 .llvm_name = "zcmt",
2155 .description = "'Zcmt' (table jump instructions for code-size reduction)",
2156 .dependencies = featureSet(&[_]Feature{
2157 .zca,
2158 .zicsr,
2159 }),
2160 };
2161 result[@backingInt(Feature.zdinx)] = .{
2162 .llvm_name = "zdinx",
2163 .description = "'Zdinx' (Double in Integer)",
2164 .dependencies = featureSet(&[_]Feature{
2165 .zfinx,
2166 }),
2167 };
2168 result[@backingInt(Feature.zexth_fusion)] = .{
2169 .llvm_name = "zexth-fusion",
2170 .description = "Enable SLLI+SRLI to be fused to zero extension of halfword",
2171 .dependencies = featureSet(&[_]Feature{}),
2172 };
2173 result[@backingInt(Feature.zextw_fusion)] = .{
2174 .llvm_name = "zextw-fusion",
2175 .description = "Enable SLLI+SRLI to be fused to zero extension of word",
2176 .dependencies = featureSet(&[_]Feature{}),
2177 };
2178 result[@backingInt(Feature.zfa)] = .{
2179 .llvm_name = "zfa",
2180 .description = "'Zfa' (Additional Floating-Point)",
2181 .dependencies = featureSet(&[_]Feature{
2182 .f,
2183 }),
2184 };
2185 result[@backingInt(Feature.zfbfmin)] = .{
2186 .llvm_name = "zfbfmin",
2187 .description = "'Zfbfmin' (Scalar BF16 Converts)",
2188 .dependencies = featureSet(&[_]Feature{
2189 .f,
2190 }),
2191 };
2192 result[@backingInt(Feature.zfh)] = .{
2193 .llvm_name = "zfh",
2194 .description = "'Zfh' (Half-Precision Floating-Point)",
2195 .dependencies = featureSet(&[_]Feature{
2196 .zfhmin,
2197 }),
2198 };
2199 result[@backingInt(Feature.zfhmin)] = .{
2200 .llvm_name = "zfhmin",
2201 .description = "'Zfhmin' (Half-Precision Floating-Point Minimal)",
2202 .dependencies = featureSet(&[_]Feature{
2203 .f,
2204 }),
2205 };
2206 result[@backingInt(Feature.zfinx)] = .{
2207 .llvm_name = "zfinx",
2208 .description = "'Zfinx' (Float in Integer)",
2209 .dependencies = featureSet(&[_]Feature{
2210 .zicsr,
2211 }),
2212 };
2213 result[@backingInt(Feature.zhinx)] = .{
2214 .llvm_name = "zhinx",
2215 .description = "'Zhinx' (Half Float in Integer)",
2216 .dependencies = featureSet(&[_]Feature{
2217 .zhinxmin,
2218 }),
2219 };
2220 result[@backingInt(Feature.zhinxmin)] = .{
2221 .llvm_name = "zhinxmin",
2222 .description = "'Zhinxmin' (Half Float in Integer Minimal)",
2223 .dependencies = featureSet(&[_]Feature{
2224 .zfinx,
2225 }),
2226 };
2227 result[@backingInt(Feature.zic64b)] = .{
2228 .llvm_name = "zic64b",
2229 .description = "'Zic64b' (Cache Block Size Is 64 Bytes)",
2230 .dependencies = featureSet(&[_]Feature{}),
2231 };
2232 result[@backingInt(Feature.zicbom)] = .{
2233 .llvm_name = "zicbom",
2234 .description = "'Zicbom' (Cache-Block Management Instructions)",
2235 .dependencies = featureSet(&[_]Feature{}),
2236 };
2237 result[@backingInt(Feature.zicbop)] = .{
2238 .llvm_name = "zicbop",
2239 .description = "'Zicbop' (Cache-Block Prefetch Instructions)",
2240 .dependencies = featureSet(&[_]Feature{}),
2241 };
2242 result[@backingInt(Feature.zicboz)] = .{
2243 .llvm_name = "zicboz",
2244 .description = "'Zicboz' (Cache-Block Zero Instructions)",
2245 .dependencies = featureSet(&[_]Feature{}),
2246 };
2247 result[@backingInt(Feature.ziccamoa)] = .{
2248 .llvm_name = "ziccamoa",
2249 .description = "'Ziccamoa' (Main Memory Supports All Atomics in A)",
2250 .dependencies = featureSet(&[_]Feature{}),
2251 };
2252 result[@backingInt(Feature.ziccamoc)] = .{
2253 .llvm_name = "ziccamoc",
2254 .description = "'Ziccamoc' (Main Memory Supports Atomics in Zacas)",
2255 .dependencies = featureSet(&[_]Feature{}),
2256 };
2257 result[@backingInt(Feature.ziccif)] = .{
2258 .llvm_name = "ziccif",
2259 .description = "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)",
2260 .dependencies = featureSet(&[_]Feature{}),
2261 };
2262 result[@backingInt(Feature.zicclsm)] = .{
2263 .llvm_name = "zicclsm",
2264 .description = "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)",
2265 .dependencies = featureSet(&[_]Feature{}),
2266 };
2267 result[@backingInt(Feature.ziccrse)] = .{
2268 .llvm_name = "ziccrse",
2269 .description = "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)",
2270 .dependencies = featureSet(&[_]Feature{}),
2271 };
2272 result[@backingInt(Feature.zicntr)] = .{
2273 .llvm_name = "zicntr",
2274 .description = "'Zicntr' (Base Counters and Timers)",
2275 .dependencies = featureSet(&[_]Feature{
2276 .zicsr,
2277 }),
2278 };
2279 result[@backingInt(Feature.zicond)] = .{
2280 .llvm_name = "zicond",
2281 .description = "'Zicond' (Integer Conditional Operations)",
2282 .dependencies = featureSet(&[_]Feature{}),
2283 };
2284 result[@backingInt(Feature.zicsr)] = .{
2285 .llvm_name = "zicsr",
2286 .description = "'Zicsr' (CSRs)",
2287 .dependencies = featureSet(&[_]Feature{}),
2288 };
2289 result[@backingInt(Feature.zifencei)] = .{
2290 .llvm_name = "zifencei",
2291 .description = "'Zifencei' (fence.i)",
2292 .dependencies = featureSet(&[_]Feature{}),
2293 };
2294 result[@backingInt(Feature.zihintntl)] = .{
2295 .llvm_name = "zihintntl",
2296 .description = "'Zihintntl' (Non-Temporal Locality Hints)",
2297 .dependencies = featureSet(&[_]Feature{}),
2298 };
2299 result[@backingInt(Feature.zihintpause)] = .{
2300 .llvm_name = "zihintpause",
2301 .description = "'Zihintpause' (Pause Hint)",
2302 .dependencies = featureSet(&[_]Feature{}),
2303 };
2304 result[@backingInt(Feature.zihpm)] = .{
2305 .llvm_name = "zihpm",
2306 .description = "'Zihpm' (Hardware Performance Counters)",
2307 .dependencies = featureSet(&[_]Feature{
2308 .zicsr,
2309 }),
2310 };
2311 result[@backingInt(Feature.zilsd)] = .{
2312 .llvm_name = "zilsd",
2313 .description = "'Zilsd' (Load/Store Pair Instructions)",
2314 .dependencies = featureSet(&[_]Feature{}),
2315 };
2316 result[@backingInt(Feature.zilsd_4byte_align)] = .{
2317 .llvm_name = "zilsd-4byte-align",
2318 .description = "Allow 4-byte alignment for Zilsd LD/SD instructions",
2319 .dependencies = featureSet(&[_]Feature{}),
2320 };
2321 result[@backingInt(Feature.zimop)] = .{
2322 .llvm_name = "zimop",
2323 .description = "'Zimop' (May-Be-Operations)",
2324 .dependencies = featureSet(&[_]Feature{}),
2325 };
2326 result[@backingInt(Feature.zk)] = .{
2327 .llvm_name = "zk",
2328 .description = "'Zk' (Standard scalar cryptography extension)",
2329 .dependencies = featureSet(&[_]Feature{
2330 .zkn,
2331 .zkr,
2332 .zkt,
2333 }),
2334 };
2335 result[@backingInt(Feature.zkn)] = .{
2336 .llvm_name = "zkn",
2337 .description = "'Zkn' (NIST Algorithm Suite)",
2338 .dependencies = featureSet(&[_]Feature{
2339 .zbkb,
2340 .zbkc,
2341 .zbkx,
2342 .zknd,
2343 .zkne,
2344 .zknh,
2345 }),
2346 };
2347 result[@backingInt(Feature.zknd)] = .{
2348 .llvm_name = "zknd",
2349 .description = "'Zknd' (NIST Suite: AES Decryption)",
2350 .dependencies = featureSet(&[_]Feature{}),
2351 };
2352 result[@backingInt(Feature.zkne)] = .{
2353 .llvm_name = "zkne",
2354 .description = "'Zkne' (NIST Suite: AES Encryption)",
2355 .dependencies = featureSet(&[_]Feature{}),
2356 };
2357 result[@backingInt(Feature.zknh)] = .{
2358 .llvm_name = "zknh",
2359 .description = "'Zknh' (NIST Suite: Hash Function Instructions)",
2360 .dependencies = featureSet(&[_]Feature{}),
2361 };
2362 result[@backingInt(Feature.zkr)] = .{
2363 .llvm_name = "zkr",
2364 .description = "'Zkr' (Entropy Source Extension)",
2365 .dependencies = featureSet(&[_]Feature{}),
2366 };
2367 result[@backingInt(Feature.zks)] = .{
2368 .llvm_name = "zks",
2369 .description = "'Zks' (ShangMi Algorithm Suite)",
2370 .dependencies = featureSet(&[_]Feature{
2371 .zbkb,
2372 .zbkc,
2373 .zbkx,
2374 .zksed,
2375 .zksh,
2376 }),
2377 };
2378 result[@backingInt(Feature.zksed)] = .{
2379 .llvm_name = "zksed",
2380 .description = "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)",
2381 .dependencies = featureSet(&[_]Feature{}),
2382 };
2383 result[@backingInt(Feature.zksh)] = .{
2384 .llvm_name = "zksh",
2385 .description = "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)",
2386 .dependencies = featureSet(&[_]Feature{}),
2387 };
2388 result[@backingInt(Feature.zkt)] = .{
2389 .llvm_name = "zkt",
2390 .description = "'Zkt' (Data Independent Execution Latency)",
2391 .dependencies = featureSet(&[_]Feature{}),
2392 };
2393 result[@backingInt(Feature.zmmul)] = .{
2394 .llvm_name = "zmmul",
2395 .description = "'Zmmul' (Integer Multiplication)",
2396 .dependencies = featureSet(&[_]Feature{}),
2397 };
2398 result[@backingInt(Feature.ztso)] = .{
2399 .llvm_name = "ztso",
2400 .description = "'Ztso' (Memory Model - Total Store Order)",
2401 .dependencies = featureSet(&[_]Feature{}),
2402 };
2403 result[@backingInt(Feature.zvbb)] = .{
2404 .llvm_name = "zvbb",
2405 .description = "'Zvbb' (Vector basic bit-manipulation instructions)",
2406 .dependencies = featureSet(&[_]Feature{
2407 .zvkb,
2408 }),
2409 };
2410 result[@backingInt(Feature.zvbc)] = .{
2411 .llvm_name = "zvbc",
2412 .description = "'Zvbc' (Vector Carryless Multiplication)",
2413 .dependencies = featureSet(&[_]Feature{
2414 .zve64x,
2415 }),
2416 };
2417 result[@backingInt(Feature.zve32f)] = .{
2418 .llvm_name = "zve32f",
2419 .description = "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)",
2420 .dependencies = featureSet(&[_]Feature{
2421 .f,
2422 .zve32x,
2423 }),
2424 };
2425 result[@backingInt(Feature.zve32x)] = .{
2426 .llvm_name = "zve32x",
2427 .description = "'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)",
2428 .dependencies = featureSet(&[_]Feature{
2429 .zicsr,
2430 .zvl32b,
2431 }),
2432 };
2433 result[@backingInt(Feature.zve64d)] = .{
2434 .llvm_name = "zve64d",
2435 .description = "'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)",
2436 .dependencies = featureSet(&[_]Feature{
2437 .d,
2438 .zve64f,
2439 }),
2440 };
2441 result[@backingInt(Feature.zve64f)] = .{
2442 .llvm_name = "zve64f",
2443 .description = "'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)",
2444 .dependencies = featureSet(&[_]Feature{
2445 .zve32f,
2446 .zve64x,
2447 }),
2448 };
2449 result[@backingInt(Feature.zve64x)] = .{
2450 .llvm_name = "zve64x",
2451 .description = "'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)",
2452 .dependencies = featureSet(&[_]Feature{
2453 .zve32x,
2454 .zvl64b,
2455 }),
2456 };
2457 result[@backingInt(Feature.zvfbfmin)] = .{
2458 .llvm_name = "zvfbfmin",
2459 .description = "'Zvfbfmin' (Vector BF16 Converts)",
2460 .dependencies = featureSet(&[_]Feature{
2461 .zve32f,
2462 }),
2463 };
2464 result[@backingInt(Feature.zvfbfwma)] = .{
2465 .llvm_name = "zvfbfwma",
2466 .description = "'Zvfbfwma' (Vector BF16 widening mul-add)",
2467 .dependencies = featureSet(&[_]Feature{
2468 .zfbfmin,
2469 .zvfbfmin,
2470 }),
2471 };
2472 result[@backingInt(Feature.zvfh)] = .{
2473 .llvm_name = "zvfh",
2474 .description = "'Zvfh' (Vector Half-Precision Floating-Point)",
2475 .dependencies = featureSet(&[_]Feature{
2476 .zfhmin,
2477 .zvfhmin,
2478 }),
2479 };
2480 result[@backingInt(Feature.zvfhmin)] = .{
2481 .llvm_name = "zvfhmin",
2482 .description = "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
2483 .dependencies = featureSet(&[_]Feature{
2484 .zve32f,
2485 }),
2486 };
2487 result[@backingInt(Feature.zvkb)] = .{
2488 .llvm_name = "zvkb",
2489 .description = "'Zvkb' (Vector Bit-manipulation used in Cryptography)",
2490 .dependencies = featureSet(&[_]Feature{
2491 .zve32x,
2492 }),
2493 };
2494 result[@backingInt(Feature.zvkg)] = .{
2495 .llvm_name = "zvkg",
2496 .description = "'Zvkg' (Vector GCM instructions for Cryptography)",
2497 .dependencies = featureSet(&[_]Feature{
2498 .zve32x,
2499 }),
2500 };
2501 result[@backingInt(Feature.zvkn)] = .{
2502 .llvm_name = "zvkn",
2503 .description = "'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt')",
2504 .dependencies = featureSet(&[_]Feature{
2505 .zvkb,
2506 .zvkned,
2507 .zvknhb,
2508 .zvkt,
2509 }),
2510 };
2511 result[@backingInt(Feature.zvknc)] = .{
2512 .llvm_name = "zvknc",
2513 .description = "'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
2514 .dependencies = featureSet(&[_]Feature{
2515 .zvbc,
2516 .zvkn,
2517 }),
2518 };
2519 result[@backingInt(Feature.zvkned)] = .{
2520 .llvm_name = "zvkned",
2521 .description = "'Zvkned' (Vector AES Encryption & Decryption (Single Round))",
2522 .dependencies = featureSet(&[_]Feature{
2523 .zve32x,
2524 }),
2525 };
2526 result[@backingInt(Feature.zvkng)] = .{
2527 .llvm_name = "zvkng",
2528 .description = "'Zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
2529 .dependencies = featureSet(&[_]Feature{
2530 .zvkg,
2531 .zvkn,
2532 }),
2533 };
2534 result[@backingInt(Feature.zvknha)] = .{
2535 .llvm_name = "zvknha",
2536 .description = "'Zvknha' (Vector SHA-2 (SHA-256 only))",
2537 .dependencies = featureSet(&[_]Feature{
2538 .zve32x,
2539 }),
2540 };
2541 result[@backingInt(Feature.zvknhb)] = .{
2542 .llvm_name = "zvknhb",
2543 .description = "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
2544 .dependencies = featureSet(&[_]Feature{
2545 .zve64x,
2546 }),
2547 };
2548 result[@backingInt(Feature.zvks)] = .{
2549 .llvm_name = "zvks",
2550 .description = "'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt')",
2551 .dependencies = featureSet(&[_]Feature{
2552 .zvkb,
2553 .zvksed,
2554 .zvksh,
2555 .zvkt,
2556 }),
2557 };
2558 result[@backingInt(Feature.zvksc)] = .{
2559 .llvm_name = "zvksc",
2560 .description = "'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
2561 .dependencies = featureSet(&[_]Feature{
2562 .zvbc,
2563 .zvks,
2564 }),
2565 };
2566 result[@backingInt(Feature.zvksed)] = .{
2567 .llvm_name = "zvksed",
2568 .description = "'Zvksed' (SM4 Block Cipher Instructions)",
2569 .dependencies = featureSet(&[_]Feature{
2570 .zve32x,
2571 }),
2572 };
2573 result[@backingInt(Feature.zvksg)] = .{
2574 .llvm_name = "zvksg",
2575 .description = "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
2576 .dependencies = featureSet(&[_]Feature{
2577 .zvkg,
2578 .zvks,
2579 }),
2580 };
2581 result[@backingInt(Feature.zvksh)] = .{
2582 .llvm_name = "zvksh",
2583 .description = "'Zvksh' (SM3 Hash Function Instructions)",
2584 .dependencies = featureSet(&[_]Feature{
2585 .zve32x,
2586 }),
2587 };
2588 result[@backingInt(Feature.zvkt)] = .{
2589 .llvm_name = "zvkt",
2590 .description = "'Zvkt' (Vector Data-Independent Execution Latency)",
2591 .dependencies = featureSet(&[_]Feature{}),
2592 };
2593 result[@backingInt(Feature.zvl1024b)] = .{
2594 .llvm_name = "zvl1024b",
2595 .description = "'Zvl1024b' (Minimum Vector Length 1024)",
2596 .dependencies = featureSet(&[_]Feature{
2597 .zvl512b,
2598 }),
2599 };
2600 result[@backingInt(Feature.zvl128b)] = .{
2601 .llvm_name = "zvl128b",
2602 .description = "'Zvl128b' (Minimum Vector Length 128)",
2603 .dependencies = featureSet(&[_]Feature{
2604 .zvl64b,
2605 }),
2606 };
2607 result[@backingInt(Feature.zvl16384b)] = .{
2608 .llvm_name = "zvl16384b",
2609 .description = "'Zvl16384b' (Minimum Vector Length 16384)",
2610 .dependencies = featureSet(&[_]Feature{
2611 .zvl8192b,
2612 }),
2613 };
2614 result[@backingInt(Feature.zvl2048b)] = .{
2615 .llvm_name = "zvl2048b",
2616 .description = "'Zvl2048b' (Minimum Vector Length 2048)",
2617 .dependencies = featureSet(&[_]Feature{
2618 .zvl1024b,
2619 }),
2620 };
2621 result[@backingInt(Feature.zvl256b)] = .{
2622 .llvm_name = "zvl256b",
2623 .description = "'Zvl256b' (Minimum Vector Length 256)",
2624 .dependencies = featureSet(&[_]Feature{
2625 .zvl128b,
2626 }),
2627 };
2628 result[@backingInt(Feature.zvl32768b)] = .{
2629 .llvm_name = "zvl32768b",
2630 .description = "'Zvl32768b' (Minimum Vector Length 32768)",
2631 .dependencies = featureSet(&[_]Feature{
2632 .zvl16384b,
2633 }),
2634 };
2635 result[@backingInt(Feature.zvl32b)] = .{
2636 .llvm_name = "zvl32b",
2637 .description = "'Zvl32b' (Minimum Vector Length 32)",
2638 .dependencies = featureSet(&[_]Feature{}),
2639 };
2640 result[@backingInt(Feature.zvl4096b)] = .{
2641 .llvm_name = "zvl4096b",
2642 .description = "'Zvl4096b' (Minimum Vector Length 4096)",
2643 .dependencies = featureSet(&[_]Feature{
2644 .zvl2048b,
2645 }),
2646 };
2647 result[@backingInt(Feature.zvl512b)] = .{
2648 .llvm_name = "zvl512b",
2649 .description = "'Zvl512b' (Minimum Vector Length 512)",
2650 .dependencies = featureSet(&[_]Feature{
2651 .zvl256b,
2652 }),
2653 };
2654 result[@backingInt(Feature.zvl64b)] = .{
2655 .llvm_name = "zvl64b",
2656 .description = "'Zvl64b' (Minimum Vector Length 64)",
2657 .dependencies = featureSet(&[_]Feature{
2658 .zvl32b,
2659 }),
2660 };
2661 result[@backingInt(Feature.zvl65536b)] = .{
2662 .llvm_name = "zvl65536b",
2663 .description = "'Zvl65536b' (Minimum Vector Length 65536)",
2664 .dependencies = featureSet(&[_]Feature{
2665 .zvl32768b,
2666 }),
2667 };
2668 result[@backingInt(Feature.zvl8192b)] = .{
2669 .llvm_name = "zvl8192b",
2670 .description = "'Zvl8192b' (Minimum Vector Length 8192)",
2671 .dependencies = featureSet(&[_]Feature{
2672 .zvl4096b,
2673 }),
2674 };
2675 const ti = @typeInfo(Feature);
2676 for (&result, 0..) |*elem, i| {
2677 elem.index = i;
2678 elem.name = ti.@"enum".field_names[i];
2679 }
2680 break :blk result;
2681};
2682
2683pub const cpu = struct {
2684 pub const andes_45_series: CpuModel = .{
2685 .name = "andes_45_series",
2686 .llvm_name = "andes-45-series",
2687 .features = featureSet(&[_]Feature{
2688 .andes45,
2689 .no_default_unroll,
2690 .short_forward_branch_ialu,
2691 .use_postra_scheduler,
2692 }),
2693 };
2694 pub const andes_a25: CpuModel = .{
2695 .name = "andes_a25",
2696 .llvm_name = "andes-a25",
2697 .features = featureSet(&[_]Feature{
2698 .@"32bit",
2699 .a,
2700 .c,
2701 .d,
2702 .i,
2703 .m,
2704 .xandesperf,
2705 .zifencei,
2706 }),
2707 };
2708 pub const andes_a45: CpuModel = .{
2709 .name = "andes_a45",
2710 .llvm_name = "andes-a45",
2711 .features = featureSet(&[_]Feature{
2712 .@"32bit",
2713 .a,
2714 .andes45,
2715 .c,
2716 .d,
2717 .i,
2718 .m,
2719 .no_default_unroll,
2720 .short_forward_branch_ialu,
2721 .use_postra_scheduler,
2722 .xandesperf,
2723 .zifencei,
2724 }),
2725 };
2726 pub const andes_ax25: CpuModel = .{
2727 .name = "andes_ax25",
2728 .llvm_name = "andes-ax25",
2729 .features = featureSet(&[_]Feature{
2730 .@"64bit",
2731 .a,
2732 .c,
2733 .d,
2734 .i,
2735 .m,
2736 .xandesperf,
2737 .zifencei,
2738 }),
2739 };
2740 pub const andes_ax45: CpuModel = .{
2741 .name = "andes_ax45",
2742 .llvm_name = "andes-ax45",
2743 .features = featureSet(&[_]Feature{
2744 .@"64bit",
2745 .a,
2746 .andes45,
2747 .c,
2748 .d,
2749 .i,
2750 .m,
2751 .no_default_unroll,
2752 .short_forward_branch_ialu,
2753 .use_postra_scheduler,
2754 .xandesperf,
2755 .zifencei,
2756 }),
2757 };
2758 pub const andes_ax45mpv: CpuModel = .{
2759 .name = "andes_ax45mpv",
2760 .llvm_name = "andes-ax45mpv",
2761 .features = featureSet(&[_]Feature{
2762 .@"64bit",
2763 .a,
2764 .andes45,
2765 .c,
2766 .i,
2767 .m,
2768 .no_default_unroll,
2769 .short_forward_branch_ialu,
2770 .use_postra_scheduler,
2771 .v,
2772 .xandesperf,
2773 .zifencei,
2774 }),
2775 };
2776 pub const andes_n45: CpuModel = .{
2777 .name = "andes_n45",
2778 .llvm_name = "andes-n45",
2779 .features = featureSet(&[_]Feature{
2780 .@"32bit",
2781 .a,
2782 .andes45,
2783 .c,
2784 .d,
2785 .i,
2786 .m,
2787 .no_default_unroll,
2788 .short_forward_branch_ialu,
2789 .use_postra_scheduler,
2790 .xandesperf,
2791 .zifencei,
2792 }),
2793 };
2794 pub const andes_nx45: CpuModel = .{
2795 .name = "andes_nx45",
2796 .llvm_name = "andes-nx45",
2797 .features = featureSet(&[_]Feature{
2798 .@"64bit",
2799 .a,
2800 .andes45,
2801 .c,
2802 .d,
2803 .i,
2804 .m,
2805 .no_default_unroll,
2806 .short_forward_branch_ialu,
2807 .use_postra_scheduler,
2808 .xandesperf,
2809 .zifencei,
2810 }),
2811 };
2812 pub const baseline_rv32: CpuModel = .{
2813 .name = "baseline_rv32",
2814 .llvm_name = null,
2815 .features = featureSet(&[_]Feature{
2816 .@"32bit",
2817 .a,
2818 .c,
2819 .d,
2820 .i,
2821 .m,
2822 }),
2823 };
2824 pub const baseline_rv64: CpuModel = .{
2825 .name = "baseline_rv64",
2826 .llvm_name = null,
2827 .features = featureSet(&[_]Feature{
2828 .@"64bit",
2829 .a,
2830 .c,
2831 .d,
2832 .i,
2833 .m,
2834 }),
2835 };
2836 pub const generic: CpuModel = .{
2837 .name = "generic",
2838 .llvm_name = "generic",
2839 .features = featureSet(&[_]Feature{}),
2840 };
2841 pub const generic_ooo: CpuModel = .{
2842 .name = "generic_ooo",
2843 .llvm_name = "generic-ooo",
2844 .features = featureSet(&[_]Feature{}),
2845 };
2846 pub const generic_rv32: CpuModel = .{
2847 .name = "generic_rv32",
2848 .llvm_name = "generic-rv32",
2849 .features = featureSet(&[_]Feature{
2850 .@"32bit",
2851 .i,
2852 .optimized_nf2_segment_load_store,
2853 }),
2854 };
2855 pub const generic_rv64: CpuModel = .{
2856 .name = "generic_rv64",
2857 .llvm_name = "generic-rv64",
2858 .features = featureSet(&[_]Feature{
2859 .@"64bit",
2860 .i,
2861 .optimized_nf2_segment_load_store,
2862 }),
2863 };
2864 pub const mips_p8700: CpuModel = .{
2865 .name = "mips_p8700",
2866 .llvm_name = "mips-p8700",
2867 .features = featureSet(&[_]Feature{
2868 .@"64bit",
2869 .a,
2870 .c,
2871 .d,
2872 .i,
2873 .m,
2874 .mips_p8700,
2875 .xmipscbop,
2876 .xmipscmov,
2877 .xmipsexectl,
2878 .xmipslsp,
2879 .zba,
2880 .zbb,
2881 .zifencei,
2882 }),
2883 };
2884 pub const rocket: CpuModel = .{
2885 .name = "rocket",
2886 .llvm_name = "rocket",
2887 .features = featureSet(&[_]Feature{}),
2888 };
2889 pub const rocket_rv32: CpuModel = .{
2890 .name = "rocket_rv32",
2891 .llvm_name = "rocket-rv32",
2892 .features = featureSet(&[_]Feature{
2893 .@"32bit",
2894 .i,
2895 .zicsr,
2896 .zifencei,
2897 }),
2898 };
2899 pub const rocket_rv64: CpuModel = .{
2900 .name = "rocket_rv64",
2901 .llvm_name = "rocket-rv64",
2902 .features = featureSet(&[_]Feature{
2903 .@"64bit",
2904 .i,
2905 .zicsr,
2906 .zifencei,
2907 }),
2908 };
2909 pub const rp2350_hazard3: CpuModel = .{
2910 .name = "rp2350_hazard3",
2911 .llvm_name = "rp2350-hazard3",
2912 .features = featureSet(&[_]Feature{
2913 .@"32bit",
2914 .a,
2915 .c,
2916 .i,
2917 .m,
2918 .zba,
2919 .zbb,
2920 .zbkb,
2921 .zbs,
2922 .zcb,
2923 .zcmp,
2924 .zicsr,
2925 .zifencei,
2926 }),
2927 };
2928 pub const sifive_7_series: CpuModel = .{
2929 .name = "sifive_7_series",
2930 .llvm_name = "sifive-7-series",
2931 .features = featureSet(&[_]Feature{
2932 .no_default_unroll,
2933 .short_forward_branch_ialu,
2934 .use_postra_scheduler,
2935 }),
2936 };
2937 pub const sifive_e20: CpuModel = .{
2938 .name = "sifive_e20",
2939 .llvm_name = "sifive-e20",
2940 .features = featureSet(&[_]Feature{
2941 .@"32bit",
2942 .c,
2943 .i,
2944 .m,
2945 .zicsr,
2946 .zifencei,
2947 }),
2948 };
2949 pub const sifive_e21: CpuModel = .{
2950 .name = "sifive_e21",
2951 .llvm_name = "sifive-e21",
2952 .features = featureSet(&[_]Feature{
2953 .@"32bit",
2954 .a,
2955 .c,
2956 .i,
2957 .m,
2958 .zicsr,
2959 .zifencei,
2960 }),
2961 };
2962 pub const sifive_e24: CpuModel = .{
2963 .name = "sifive_e24",
2964 .llvm_name = "sifive-e24",
2965 .features = featureSet(&[_]Feature{
2966 .@"32bit",
2967 .a,
2968 .c,
2969 .f,
2970 .i,
2971 .m,
2972 .zifencei,
2973 }),
2974 };
2975 pub const sifive_e31: CpuModel = .{
2976 .name = "sifive_e31",
2977 .llvm_name = "sifive-e31",
2978 .features = featureSet(&[_]Feature{
2979 .@"32bit",
2980 .a,
2981 .c,
2982 .i,
2983 .m,
2984 .zicsr,
2985 .zifencei,
2986 }),
2987 };
2988 pub const sifive_e34: CpuModel = .{
2989 .name = "sifive_e34",
2990 .llvm_name = "sifive-e34",
2991 .features = featureSet(&[_]Feature{
2992 .@"32bit",
2993 .a,
2994 .c,
2995 .f,
2996 .i,
2997 .m,
2998 .zifencei,
2999 }),
3000 };
3001 pub const sifive_e76: CpuModel = .{
3002 .name = "sifive_e76",
3003 .llvm_name = "sifive-e76",
3004 .features = featureSet(&[_]Feature{
3005 .@"32bit",
3006 .a,
3007 .c,
3008 .f,
3009 .i,
3010 .m,
3011 .no_default_unroll,
3012 .short_forward_branch_ialu,
3013 .use_postra_scheduler,
3014 .zifencei,
3015 }),
3016 };
3017 pub const sifive_p450: CpuModel = .{
3018 .name = "sifive_p450",
3019 .llvm_name = "sifive-p450",
3020 .features = featureSet(&[_]Feature{
3021 .@"64bit",
3022 .a,
3023 .auipc_addi_fusion,
3024 .b,
3025 .c,
3026 .conditional_cmv_fusion,
3027 .d,
3028 .i,
3029 .lui_addi_fusion,
3030 .m,
3031 .no_default_unroll,
3032 .unaligned_scalar_mem,
3033 .unaligned_vector_mem,
3034 .use_postra_scheduler,
3035 .za64rs,
3036 .zfhmin,
3037 .zic64b,
3038 .zicbom,
3039 .zicbop,
3040 .zicboz,
3041 .ziccamoa,
3042 .ziccif,
3043 .zicclsm,
3044 .ziccrse,
3045 .zifencei,
3046 .zihintntl,
3047 .zihintpause,
3048 .zihpm,
3049 .zkt,
3050 }),
3051 };
3052 pub const sifive_p470: CpuModel = .{
3053 .name = "sifive_p470",
3054 .llvm_name = "sifive-p470",
3055 .features = featureSet(&[_]Feature{
3056 .@"64bit",
3057 .a,
3058 .auipc_addi_fusion,
3059 .b,
3060 .c,
3061 .conditional_cmv_fusion,
3062 .i,
3063 .lui_addi_fusion,
3064 .m,
3065 .no_default_unroll,
3066 .no_sink_splat_operands,
3067 .unaligned_scalar_mem,
3068 .unaligned_vector_mem,
3069 .use_postra_scheduler,
3070 .v,
3071 .vxrm_pipeline_flush,
3072 .xsifivecdiscarddlone,
3073 .xsifivecflushdlone,
3074 .za64rs,
3075 .zfhmin,
3076 .zic64b,
3077 .zicbom,
3078 .zicbop,
3079 .zicboz,
3080 .ziccamoa,
3081 .ziccif,
3082 .zicclsm,
3083 .ziccrse,
3084 .zifencei,
3085 .zihintntl,
3086 .zihintpause,
3087 .zihpm,
3088 .zkt,
3089 .zvbb,
3090 .zvknc,
3091 .zvkng,
3092 .zvksc,
3093 .zvksg,
3094 }),
3095 };
3096 pub const sifive_p550: CpuModel = .{
3097 .name = "sifive_p550",
3098 .llvm_name = "sifive-p550",
3099 .features = featureSet(&[_]Feature{
3100 .@"64bit",
3101 .a,
3102 .auipc_addi_fusion,
3103 .c,
3104 .conditional_cmv_fusion,
3105 .d,
3106 .i,
3107 .lui_addi_fusion,
3108 .m,
3109 .no_default_unroll,
3110 .use_postra_scheduler,
3111 .zba,
3112 .zbb,
3113 .zifencei,
3114 }),
3115 };
3116 pub const sifive_p670: CpuModel = .{
3117 .name = "sifive_p670",
3118 .llvm_name = "sifive-p670",
3119 .features = featureSet(&[_]Feature{
3120 .@"64bit",
3121 .a,
3122 .auipc_addi_fusion,
3123 .b,
3124 .c,
3125 .conditional_cmv_fusion,
3126 .i,
3127 .lui_addi_fusion,
3128 .m,
3129 .no_default_unroll,
3130 .no_sink_splat_operands,
3131 .unaligned_scalar_mem,
3132 .unaligned_vector_mem,
3133 .use_postra_scheduler,
3134 .v,
3135 .vxrm_pipeline_flush,
3136 .za64rs,
3137 .zfhmin,
3138 .zic64b,
3139 .zicbom,
3140 .zicbop,
3141 .zicboz,
3142 .ziccamoa,
3143 .ziccif,
3144 .zicclsm,
3145 .ziccrse,
3146 .zifencei,
3147 .zihintntl,
3148 .zihintpause,
3149 .zihpm,
3150 .zkt,
3151 .zvbb,
3152 .zvknc,
3153 .zvkng,
3154 .zvksc,
3155 .zvksg,
3156 }),
3157 };
3158 pub const sifive_p870: CpuModel = .{
3159 .name = "sifive_p870",
3160 .llvm_name = "sifive-p870",
3161 .features = featureSet(&[_]Feature{
3162 .@"64bit",
3163 .a,
3164 .auipc_addi_fusion,
3165 .b,
3166 .c,
3167 .conditional_cmv_fusion,
3168 .i,
3169 .lui_addi_fusion,
3170 .m,
3171 .no_default_unroll,
3172 .no_sink_splat_operands,
3173 .supm,
3174 .unaligned_scalar_mem,
3175 .unaligned_vector_mem,
3176 .use_postra_scheduler,
3177 .v,
3178 .vxrm_pipeline_flush,
3179 .za64rs,
3180 .zama16b,
3181 .zawrs,
3182 .zcb,
3183 .zcmop,
3184 .zfa,
3185 .zfh,
3186 .zic64b,
3187 .zicbom,
3188 .zicbop,
3189 .zicboz,
3190 .ziccamoa,
3191 .ziccif,
3192 .zicclsm,
3193 .ziccrse,
3194 .zicntr,
3195 .zicond,
3196 .zifencei,
3197 .zihintntl,
3198 .zihintpause,
3199 .zihpm,
3200 .zimop,
3201 .zkr,
3202 .zkt,
3203 .zvbb,
3204 .zvfbfwma,
3205 .zvfh,
3206 .zvknc,
3207 .zvkng,
3208 .zvksc,
3209 .zvksg,
3210 }),
3211 };
3212 pub const sifive_s21: CpuModel = .{
3213 .name = "sifive_s21",
3214 .llvm_name = "sifive-s21",
3215 .features = featureSet(&[_]Feature{
3216 .@"64bit",
3217 .a,
3218 .c,
3219 .i,
3220 .m,
3221 .zicsr,
3222 .zifencei,
3223 }),
3224 };
3225 pub const sifive_s51: CpuModel = .{
3226 .name = "sifive_s51",
3227 .llvm_name = "sifive-s51",
3228 .features = featureSet(&[_]Feature{
3229 .@"64bit",
3230 .a,
3231 .c,
3232 .i,
3233 .m,
3234 .zicsr,
3235 .zifencei,
3236 }),
3237 };
3238 pub const sifive_s54: CpuModel = .{
3239 .name = "sifive_s54",
3240 .llvm_name = "sifive-s54",
3241 .features = featureSet(&[_]Feature{
3242 .@"64bit",
3243 .a,
3244 .c,
3245 .d,
3246 .i,
3247 .m,
3248 .zifencei,
3249 }),
3250 };
3251 pub const sifive_s76: CpuModel = .{
3252 .name = "sifive_s76",
3253 .llvm_name = "sifive-s76",
3254 .features = featureSet(&[_]Feature{
3255 .@"64bit",
3256 .a,
3257 .c,
3258 .d,
3259 .i,
3260 .m,
3261 .no_default_unroll,
3262 .short_forward_branch_ialu,
3263 .use_postra_scheduler,
3264 .zifencei,
3265 .zihintpause,
3266 }),
3267 };
3268 pub const sifive_u54: CpuModel = .{
3269 .name = "sifive_u54",
3270 .llvm_name = "sifive-u54",
3271 .features = featureSet(&[_]Feature{
3272 .@"64bit",
3273 .a,
3274 .c,
3275 .d,
3276 .i,
3277 .m,
3278 .zifencei,
3279 }),
3280 };
3281 pub const sifive_u74: CpuModel = .{
3282 .name = "sifive_u74",
3283 .llvm_name = "sifive-u74",
3284 .features = featureSet(&[_]Feature{
3285 .@"64bit",
3286 .a,
3287 .c,
3288 .d,
3289 .i,
3290 .m,
3291 .no_default_unroll,
3292 .short_forward_branch_ialu,
3293 .use_postra_scheduler,
3294 .zifencei,
3295 }),
3296 };
3297 pub const sifive_x280: CpuModel = .{
3298 .name = "sifive_x280",
3299 .llvm_name = "sifive-x280",
3300 .features = featureSet(&[_]Feature{
3301 .@"64bit",
3302 .a,
3303 .c,
3304 .dlen_factor_2,
3305 .i,
3306 .m,
3307 .no_default_unroll,
3308 .optimized_nf2_segment_load_store,
3309 .optimized_zero_stride_load,
3310 .short_forward_branch_ialu,
3311 .use_postra_scheduler,
3312 .v,
3313 .vl_dependent_latency,
3314 .zba,
3315 .zbb,
3316 .zfh,
3317 .zifencei,
3318 .zvfh,
3319 .zvl512b,
3320 }),
3321 };
3322 pub const sifive_x390: CpuModel = .{
3323 .name = "sifive_x390",
3324 .llvm_name = "sifive-x390",
3325 .features = featureSet(&[_]Feature{
3326 .@"64bit",
3327 .a,
3328 .b,
3329 .c,
3330 .dlen_factor_2,
3331 .experimental_zicfilp,
3332 .experimental_zicfiss,
3333 .i,
3334 .m,
3335 .no_default_unroll,
3336 .optimized_nf2_segment_load_store,
3337 .optimized_zero_stride_load,
3338 .short_forward_branch_ialu,
3339 .single_element_vec_fp64,
3340 .use_postra_scheduler,
3341 .v,
3342 .vl_dependent_latency,
3343 .xsifivecdiscarddlone,
3344 .xsifivecflushdlone,
3345 .za64rs,
3346 .zawrs,
3347 .zcb,
3348 .zcmop,
3349 .zfa,
3350 .zfh,
3351 .zic64b,
3352 .zicbom,
3353 .zicbop,
3354 .zicboz,
3355 .ziccamoa,
3356 .ziccif,
3357 .ziccrse,
3358 .zicntr,
3359 .zicond,
3360 .zifencei,
3361 .zihintntl,
3362 .zihintpause,
3363 .zihpm,
3364 .zkr,
3365 .zkt,
3366 .zvbb,
3367 .zvfbfwma,
3368 .zvfh,
3369 .zvkt,
3370 .zvl1024b,
3371 }),
3372 };
3373 pub const spacemit_a100: CpuModel = .{
3374 .name = "spacemit_a100",
3375 .llvm_name = null,
3376 .features = featureSet(&[_]Feature{
3377 .@"64bit",
3378 .a,
3379 .b,
3380 .c,
3381 .dlen_factor_2,
3382 .i,
3383 .m,
3384 .optimized_nf2_segment_load_store,
3385 .optimized_nf3_segment_load_store,
3386 .optimized_nf4_segment_load_store,
3387 .smepmp,
3388 .smnpm,
3389 .smstateen,
3390 .ssccptr,
3391 .sscofpmf,
3392 .sscounterenw,
3393 .ssnpm,
3394 .sspm,
3395 .sstc,
3396 .sstvala,
3397 .sstvecd,
3398 .ssu64xl,
3399 .supm,
3400 .svade,
3401 .svbare,
3402 .svinval,
3403 .svnapot,
3404 .svpbmt,
3405 .unaligned_scalar_mem,
3406 .v,
3407 .vxrm_pipeline_flush,
3408 .za64rs,
3409 .zawrs,
3410 .zbc,
3411 .zbkc,
3412 .zcb,
3413 .zcmop,
3414 .zfa,
3415 .zfh,
3416 .zic64b,
3417 .zicbom,
3418 .zicbop,
3419 .zicboz,
3420 .ziccamoa,
3421 .ziccif,
3422 .zicclsm,
3423 .ziccrse,
3424 .zicntr,
3425 .zicond,
3426 .zifencei,
3427 .zihintntl,
3428 .zihintpause,
3429 .zihpm,
3430 .zimop,
3431 .zkt,
3432 .zvbb,
3433 .zvfbfwma,
3434 .zvfh,
3435 .zvkng,
3436 .zvknha,
3437 .zvksc,
3438 .zvksg,
3439 .zvl1024b,
3440 }),
3441 };
3442 pub const spacemit_x100: CpuModel = .{
3443 .name = "spacemit_x100",
3444 .llvm_name = null,
3445 .features = featureSet(&[_]Feature{
3446 .dlen_factor_2,
3447 .optimized_nf2_segment_load_store,
3448 .optimized_nf3_segment_load_store,
3449 .optimized_nf4_segment_load_store,
3450 .rva23s64,
3451 .smepmp,
3452 .smnpm,
3453 .smstateen,
3454 .sspm,
3455 .unaligned_scalar_mem,
3456 .vxrm_pipeline_flush,
3457 .xsmtvdot,
3458 .zbc,
3459 .zbkc,
3460 .zfh,
3461 .zvfbfwma,
3462 .zvfh,
3463 .zvkng,
3464 .zvknha,
3465 .zvksc,
3466 .zvksg,
3467 .zvl256b,
3468 }),
3469 };
3470 pub const spacemit_x60: CpuModel = .{
3471 .name = "spacemit_x60",
3472 .llvm_name = "spacemit-x60",
3473 .features = featureSet(&[_]Feature{
3474 .@"64bit",
3475 .a,
3476 .b,
3477 .c,
3478 .dlen_factor_2,
3479 .i,
3480 .m,
3481 .optimized_nf2_segment_load_store,
3482 .optimized_nf3_segment_load_store,
3483 .optimized_nf4_segment_load_store,
3484 .ssccptr,
3485 .sscofpmf,
3486 .sscounterenw,
3487 .sstc,
3488 .sstvala,
3489 .sstvecd,
3490 .svade,
3491 .svbare,
3492 .svinval,
3493 .svnapot,
3494 .svpbmt,
3495 .unaligned_scalar_mem,
3496 .v,
3497 .vxrm_pipeline_flush,
3498 .xsmtvdot,
3499 .za64rs,
3500 .zbc,
3501 .zbkc,
3502 .zfh,
3503 .zic64b,
3504 .zicbom,
3505 .zicbop,
3506 .zicboz,
3507 .ziccamoa,
3508 .ziccif,
3509 .zicclsm,
3510 .ziccrse,
3511 .zicntr,
3512 .zicond,
3513 .zifencei,
3514 .zihintpause,
3515 .zihpm,
3516 .zkt,
3517 .zvfh,
3518 .zvkt,
3519 .zvl256b,
3520 }),
3521 };
3522 pub const syntacore_scr1_base: CpuModel = .{
3523 .name = "syntacore_scr1_base",
3524 .llvm_name = "syntacore-scr1-base",
3525 .features = featureSet(&[_]Feature{
3526 .@"32bit",
3527 .c,
3528 .i,
3529 .no_default_unroll,
3530 .zicsr,
3531 .zifencei,
3532 }),
3533 };
3534 pub const syntacore_scr1_max: CpuModel = .{
3535 .name = "syntacore_scr1_max",
3536 .llvm_name = "syntacore-scr1-max",
3537 .features = featureSet(&[_]Feature{
3538 .@"32bit",
3539 .c,
3540 .i,
3541 .m,
3542 .no_default_unroll,
3543 .zicsr,
3544 .zifencei,
3545 }),
3546 };
3547 pub const syntacore_scr3_rv32: CpuModel = .{
3548 .name = "syntacore_scr3_rv32",
3549 .llvm_name = "syntacore-scr3-rv32",
3550 .features = featureSet(&[_]Feature{
3551 .@"32bit",
3552 .c,
3553 .i,
3554 .m,
3555 .no_default_unroll,
3556 .use_postra_scheduler,
3557 .zicsr,
3558 .zifencei,
3559 }),
3560 };
3561 pub const syntacore_scr3_rv64: CpuModel = .{
3562 .name = "syntacore_scr3_rv64",
3563 .llvm_name = "syntacore-scr3-rv64",
3564 .features = featureSet(&[_]Feature{
3565 .@"64bit",
3566 .a,
3567 .c,
3568 .i,
3569 .m,
3570 .no_default_unroll,
3571 .use_postra_scheduler,
3572 .zicsr,
3573 .zifencei,
3574 }),
3575 };
3576 pub const syntacore_scr4_rv32: CpuModel = .{
3577 .name = "syntacore_scr4_rv32",
3578 .llvm_name = "syntacore-scr4-rv32",
3579 .features = featureSet(&[_]Feature{
3580 .@"32bit",
3581 .c,
3582 .d,
3583 .i,
3584 .m,
3585 .no_default_unroll,
3586 .use_postra_scheduler,
3587 .zifencei,
3588 }),
3589 };
3590 pub const syntacore_scr4_rv64: CpuModel = .{
3591 .name = "syntacore_scr4_rv64",
3592 .llvm_name = "syntacore-scr4-rv64",
3593 .features = featureSet(&[_]Feature{
3594 .@"64bit",
3595 .a,
3596 .c,
3597 .d,
3598 .i,
3599 .m,
3600 .no_default_unroll,
3601 .use_postra_scheduler,
3602 .zifencei,
3603 }),
3604 };
3605 pub const syntacore_scr5_rv32: CpuModel = .{
3606 .name = "syntacore_scr5_rv32",
3607 .llvm_name = "syntacore-scr5-rv32",
3608 .features = featureSet(&[_]Feature{
3609 .@"32bit",
3610 .a,
3611 .c,
3612 .d,
3613 .i,
3614 .m,
3615 .no_default_unroll,
3616 .use_postra_scheduler,
3617 .zifencei,
3618 }),
3619 };
3620 pub const syntacore_scr5_rv64: CpuModel = .{
3621 .name = "syntacore_scr5_rv64",
3622 .llvm_name = "syntacore-scr5-rv64",
3623 .features = featureSet(&[_]Feature{
3624 .@"64bit",
3625 .a,
3626 .c,
3627 .d,
3628 .i,
3629 .m,
3630 .no_default_unroll,
3631 .use_postra_scheduler,
3632 .zifencei,
3633 }),
3634 };
3635 pub const syntacore_scr7: CpuModel = .{
3636 .name = "syntacore_scr7",
3637 .llvm_name = "syntacore-scr7",
3638 .features = featureSet(&[_]Feature{
3639 .@"64bit",
3640 .a,
3641 .c,
3642 .i,
3643 .m,
3644 .no_default_unroll,
3645 .use_postra_scheduler,
3646 .v,
3647 .zba,
3648 .zbb,
3649 .zbc,
3650 .zbs,
3651 .zifencei,
3652 .zkn,
3653 }),
3654 };
3655 pub const tt_ascalon_d8: CpuModel = .{
3656 .name = "tt_ascalon_d8",
3657 .llvm_name = "tt-ascalon-d8",
3658 .features = featureSet(&[_]Feature{
3659 .@"64bit",
3660 .a,
3661 .b,
3662 .c,
3663 .i,
3664 .log_vrgather,
3665 .m,
3666 .no_default_unroll,
3667 .optimized_nf2_segment_load_store,
3668 .optimized_nf3_segment_load_store,
3669 .optimized_nf4_segment_load_store,
3670 .optimized_nf5_segment_load_store,
3671 .optimized_nf6_segment_load_store,
3672 .optimized_nf7_segment_load_store,
3673 .optimized_nf8_segment_load_store,
3674 .optimized_zero_stride_load,
3675 .sha,
3676 .smaia,
3677 .ssaia,
3678 .ssccptr,
3679 .sscofpmf,
3680 .sscounterenw,
3681 .ssnpm,
3682 .ssstrict,
3683 .sstc,
3684 .sstvala,
3685 .sstvecd,
3686 .ssu64xl,
3687 .supm,
3688 .svade,
3689 .svbare,
3690 .svinval,
3691 .svnapot,
3692 .svpbmt,
3693 .unaligned_scalar_mem,
3694 .unaligned_vector_mem,
3695 .use_postra_scheduler,
3696 .v,
3697 .za64rs,
3698 .zawrs,
3699 .zcb,
3700 .zcmop,
3701 .zfa,
3702 .zfh,
3703 .zic64b,
3704 .zicbom,
3705 .zicbop,
3706 .zicboz,
3707 .ziccamoa,
3708 .ziccif,
3709 .zicclsm,
3710 .ziccrse,
3711 .zicntr,
3712 .zicond,
3713 .zifencei,
3714 .zihintntl,
3715 .zihintpause,
3716 .zihpm,
3717 .zimop,
3718 .zkt,
3719 .zvbb,
3720 .zvbc,
3721 .zvfbfwma,
3722 .zvfh,
3723 .zvkng,
3724 .zvl256b,
3725 }),
3726 };
3727 pub const veyron_v1: CpuModel = .{
3728 .name = "veyron_v1",
3729 .llvm_name = "veyron-v1",
3730 .features = featureSet(&[_]Feature{
3731 .@"64bit",
3732 .a,
3733 .add_load_fusion,
3734 .auipc_addi_fusion,
3735 .auipc_load_fusion,
3736 .c,
3737 .d,
3738 .disable_misched_load_clustering,
3739 .disable_postmisched_load_clustering,
3740 .disable_postmisched_store_clustering,
3741 .i,
3742 .lui_addi_fusion,
3743 .lui_load_fusion,
3744 .m,
3745 .shifted_zextw_fusion,
3746 .ventana_veyron,
3747 .xventanacondops,
3748 .zba,
3749 .zbb,
3750 .zbc,
3751 .zbs,
3752 .zexth_fusion,
3753 .zextw_fusion,
3754 .zicbom,
3755 .zicbop,
3756 .zicboz,
3757 .zicntr,
3758 .zifencei,
3759 .zihintpause,
3760 .zihpm,
3761 }),
3762 };
3763 pub const xiangshan_kunminghu: CpuModel = .{
3764 .name = "xiangshan_kunminghu",
3765 .llvm_name = "xiangshan-kunminghu",
3766 .features = featureSet(&[_]Feature{
3767 .@"64bit",
3768 .a,
3769 .b,
3770 .c,
3771 .i,
3772 .m,
3773 .no_default_unroll,
3774 .sha,
3775 .shifted_zextw_fusion,
3776 .smaia,
3777 .smcsrind,
3778 .smdbltrp,
3779 .smmpm,
3780 .smnpm,
3781 .smrnmi,
3782 .smstateen,
3783 .ssaia,
3784 .ssccptr,
3785 .sscofpmf,
3786 .sscounterenw,
3787 .sscsrind,
3788 .ssdbltrp,
3789 .ssnpm,
3790 .sspm,
3791 .ssstrict,
3792 .sstc,
3793 .sstvala,
3794 .sstvecd,
3795 .ssu64xl,
3796 .supm,
3797 .svade,
3798 .svbare,
3799 .svinval,
3800 .svnapot,
3801 .svpbmt,
3802 .v,
3803 .za64rs,
3804 .zacas,
3805 .zawrs,
3806 .zbc,
3807 .zcb,
3808 .zcmop,
3809 .zexth_fusion,
3810 .zextw_fusion,
3811 .zfa,
3812 .zfh,
3813 .zic64b,
3814 .zicbom,
3815 .zicbop,
3816 .zicboz,
3817 .ziccamoa,
3818 .ziccif,
3819 .zicclsm,
3820 .ziccrse,
3821 .zicntr,
3822 .zicond,
3823 .zifencei,
3824 .zihintntl,
3825 .zihintpause,
3826 .zihpm,
3827 .zimop,
3828 .zkn,
3829 .zks,
3830 .zkt,
3831 .zvbb,
3832 .zvfh,
3833 .zvkt,
3834 }),
3835 };
3836 pub const xiangshan_nanhu: CpuModel = .{
3837 .name = "xiangshan_nanhu",
3838 .llvm_name = "xiangshan-nanhu",
3839 .features = featureSet(&[_]Feature{
3840 .@"64bit",
3841 .a,
3842 .c,
3843 .d,
3844 .i,
3845 .m,
3846 .no_default_unroll,
3847 .shifted_zextw_fusion,
3848 .svinval,
3849 .zba,
3850 .zbb,
3851 .zbc,
3852 .zbs,
3853 .zexth_fusion,
3854 .zextw_fusion,
3855 .zicbom,
3856 .zicboz,
3857 .zifencei,
3858 .zkn,
3859 .zksed,
3860 .zksh,
3861 }),
3862 };
3863};