authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2026-06-26 01:08:08-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2026-07-27 14:35:12-04:00
log0c0be6da880fd1a6bdd3266125d6c5bcaac2803f
tree630652d279009d6e67e9b1f149fc1335153ad790
parent1e4b0e0022fcbda51032fe555d948ae59db3f640

llvm: implement c cabi for s390x

Closes #35799

6 files changed, 121 insertions(+), 130 deletions(-)

CMakeLists.txt+1
...@@ -358,6 +358,7 @@ set(ZIG_STAGE2_SOURCES...@@ -358,6 +358,7 @@ set(ZIG_STAGE2_SOURCES
358 src/codegen/c/type/render_defs.zig358 src/codegen/c/type/render_defs.zig
359 src/codegen/llvm.zig359 src/codegen/llvm.zig
360 src/codegen/llvm/bindings.zig360 src/codegen/llvm/bindings.zig
361 src/codegen/s390x/abi.zig
361 src/crash_report.zig362 src/crash_report.zig
362 src/dev.zig363 src/dev.zig
363 src/libs/freebsd.zig364 src/libs/freebsd.zig
src/codegen/aarch64/abi.zig+1-1
...@@ -1,4 +1,4 @@...@@ -1,4 +1,4 @@
1const assert = @import("std").debug.assert;1const assert = std.debug.assert;
2const std = @import("std");2const std = @import("std");
3const InternPool = @import("../../InternPool.zig");3const InternPool = @import("../../InternPool.zig");
4const Type = @import("../../Type.zig");4const Type = @import("../../Type.zig");
src/codegen/llvm/FuncGen.zig+28-3
...@@ -6808,6 +6808,24 @@ const ParamTypeIterator = struct {...@@ -6808,6 +6808,24 @@ const ParamTypeIterator = struct {
6808 },6808 },
6809 }6809 }
6810 },6810 },
6811 .s390x_sysv, .s390x_sysv_vx => {
6812 it.zig_index += 1;
6813 switch (s390x_c_abi.classifyType(ty, .arg, zcu)) {
6814 .none => return .no_bits,
6815 .double_or_float, .vector, .simple => {
6816 it.llvm_index += 1;
6817 return .byval;
6818 },
6819 .simple_aggregate => {
6820 it.llvm_index += 1;
6821 return .abi_sized_int;
6822 },
6823 .pointer => {
6824 it.llvm_index += 1;
6825 return .byref_mut;
6826 },
6827 }
6828 },
6811 .wasm_mvp => switch (wasm_c_abi.classifyType(ty, zcu)) {6829 .wasm_mvp => switch (wasm_c_abi.classifyType(ty, zcu)) {
6812 .direct => |scalar_ty| {6830 .direct => |scalar_ty| {
6813 if (isScalar(zcu, ty)) {6831 if (isScalar(zcu, ty)) {
...@@ -7086,6 +7104,12 @@ pub fn fnReturnStrat(o: *Object, fn_info: InternPool.Key.FuncType) Allocator.Err...@@ -7086,6 +7104,12 @@ pub fn fnReturnStrat(o: *Object, fn_info: InternPool.Key.FuncType) Allocator.Err
7086 return .{ .mem_cast = try o.builder.structType(.normal, types[0..types_len]) };7104 return .{ .mem_cast = try o.builder.structType(.normal, types[0..types_len]) };
7087 },7105 },
7088 },7106 },
7107 .s390x_sysv, .s390x_sysv_vx => return switch (s390x_c_abi.classifyType(ret_ty, .ret, zcu)) {
7108 .none => .void,
7109 .double_or_float, .vector, .simple => .by_val,
7110 .simple_aggregate => unreachable,
7111 .pointer => .sret,
7112 },
7089 .wasm_mvp => switch (wasm_c_abi.classifyType(ret_ty, zcu)) {7113 .wasm_mvp => switch (wasm_c_abi.classifyType(ret_ty, zcu)) {
7090 .direct => |scalar_ty| if (scalar_ty.toIntern() == ret_ty.toIntern()) {7114 .direct => |scalar_ty| if (scalar_ty.toIntern() == ret_ty.toIntern()) {
7091 assert(!isByRef(ret_ty, zcu));7115 assert(!isByRef(ret_ty, zcu));
...@@ -7823,12 +7847,13 @@ const Builder = std.zig.llvm.Builder;...@@ -7823,12 +7847,13 @@ const Builder = std.zig.llvm.Builder;
7823const assert = std.debug.assert;7847const assert = std.debug.assert;
7824const math = std.math;7848const math = std.math;
78257849
7826const x86_64_abi = @import("../x86_64/abi.zig");
7827const wasm_c_abi = @import("../wasm/abi.zig");
7828const aarch64_c_abi = @import("../aarch64/abi.zig");7850const aarch64_c_abi = @import("../aarch64/abi.zig");
7829const arm_c_abi = @import("../arm/abi.zig");7851const arm_c_abi = @import("../arm/abi.zig");
7830const riscv_c_abi = @import("../riscv64/abi.zig");
7831const mips_c_abi = @import("../mips/abi.zig");7852const mips_c_abi = @import("../mips/abi.zig");
7853const riscv_c_abi = @import("../riscv64/abi.zig");
7854const s390x_c_abi = @import("../s390x/abi.zig");
7855const wasm_c_abi = @import("../wasm/abi.zig");
7856const x86_64_abi = @import("../x86_64/abi.zig");
78327857
7833const Zcu = @import("../../Zcu.zig");7858const Zcu = @import("../../Zcu.zig");
7834const Air = @import("../../Air.zig");7859const Air = @import("../../Air.zig");
src/codegen/s390x/abi.zig created+90
...@@ -0,0 +1,90 @@
1const assert = std.debug.assert;
2const std = @import("std");
3const InternPool = @import("../../InternPool.zig");
4const Type = @import("../../Type.zig");
5const Zcu = @import("../../Zcu.zig");
6
7pub const Context = enum { ret, arg };
8
9pub const Class = enum {
10 none,
11 double_or_float,
12 vector,
13 simple,
14 simple_aggregate,
15 pointer,
16};
17
18pub fn classifyType(ty: Type, context: Context, zcu: *Zcu) Class {
19 tag: switch (ty.zigTypeTag(zcu)) {
20 .type,
21 .comptime_float,
22 .comptime_int,
23 .undefined,
24 .null,
25 .error_union,
26 .error_set,
27 .@"fn",
28 .@"opaque",
29 .frame,
30 .@"anyframe",
31 .enum_literal,
32 .spirv,
33 => unreachable,
34 .void, .noreturn => return .none,
35 .bool => return .simple,
36 .int, .@"enum" => return switch (ty.intInfo(zcu).bits) {
37 0 => .none,
38 1...64 => .simple,
39 else => .pointer,
40 },
41 .float => return switch (ty.floatBits(zcu.getTarget())) {
42 16, 32, 64 => .double_or_float,
43 else => .pointer,
44 },
45 .pointer, .optional => return .simple,
46 .array => switch (ty.arrayLen(zcu)) {
47 0 => return .none,
48 1 => switch (context) {
49 .ret => {},
50 .arg => return classifyType(ty.childType(zcu), context, zcu),
51 },
52 else => {},
53 },
54 .@"struct", .@"union" => |tag| switch (ty.containerLayout(zcu)) {
55 .auto => unreachable,
56 .@"extern" => switch (context) {
57 .ret => {},
58 .arg => {
59 var class: Class = .none;
60 for (0..switch (tag) {
61 else => unreachable,
62 .@"struct" => ty.structFieldCount(zcu),
63 .@"union" => ty.unionTagTypeHypothetical(zcu).enumFieldCount(zcu),
64 }) |field_index| {
65 switch (tag) {
66 else => unreachable,
67 .@"struct" => if (ty.structFieldIsComptime(field_index, zcu)) continue,
68 .@"union" => {},
69 }
70 const field_class = classifyType(ty.fieldType(field_index, zcu), context, zcu);
71 if (field_class == .none) continue;
72 if (class != .none) break :tag;
73 class = field_class;
74 }
75 return class;
76 },
77 },
78 .@"packed" => return classifyType(ty.backingIntType(zcu), context, zcu),
79 },
80 .vector => return if (ty.abiSize(zcu) <= 16) .vector else .pointer,
81 }
82 return switch (ty.abiSize(zcu)) {
83 0 => .none,
84 1, 2, 4, 8 => switch (context) {
85 .ret => .pointer,
86 .arg => .simple_aggregate,
87 },
88 else => .pointer,
89 };
90}
test/c_abi/cfuncs.c-12
...@@ -15564,7 +15564,6 @@ void run_c_tests(void) {...@@ -15564,7 +15564,6 @@ void run_c_tests(void) {
15564#ifndef __loongarch__15564#ifndef __loongarch__
15565#ifndef ZIG_MIPS6415565#ifndef ZIG_MIPS64
15566#ifndef __powerpc__15566#ifndef __powerpc__
15567#ifndef __s390x__
15568 {15567 {
15569 struct Struct_i32_i32 s = {1, 2};15568 struct Struct_i32_i32 s = {1, 2};
15570 zig_struct_i32_i32(s);15569 zig_struct_i32_i32(s);
...@@ -15573,13 +15572,11 @@ void run_c_tests(void) {...@@ -15573,13 +15572,11 @@ void run_c_tests(void) {
15573#endif15572#endif
15574#endif15573#endif
15575#endif15574#endif
15576#endif
1557715575
15578#ifndef __hexagon__15576#ifndef __hexagon__
15579#ifndef __loongarch__15577#ifndef __loongarch__
15580#ifndef ZIG_MIPS6415578#ifndef ZIG_MIPS64
15581#ifndef __powerpc__15579#ifndef __powerpc__
15582#ifndef __s390x__
15583 {15580 {
15584 struct BigStruct s = {1, 2, 3, 4, 5};15581 struct BigStruct s = {1, 2, 3, 4, 5};
15585 zig_big_struct(s);15582 zig_big_struct(s);
...@@ -15588,7 +15585,6 @@ void run_c_tests(void) {...@@ -15588,7 +15585,6 @@ void run_c_tests(void) {
15588#endif15585#endif
15589#endif15586#endif
15590#endif15587#endif
15591#endif
1559215588
15593#ifndef ZIG_NO_I12815589#ifndef ZIG_NO_I128
15594 {15590 {
...@@ -15613,7 +15609,6 @@ void run_c_tests(void) {...@@ -15613,7 +15609,6 @@ void run_c_tests(void) {
15613#ifndef __loongarch__15609#ifndef __loongarch__
15614#ifndef ZIG_MIPS6415610#ifndef ZIG_MIPS64
15615#ifndef __powerpc__15611#ifndef __powerpc__
15616#ifndef __s390x__
15617 {15612 {
15618 struct SplitStructInts s = {1234, 100, 1337};15613 struct SplitStructInts s = {1234, 100, 1337};
15619 zig_split_struct_ints(s);15614 zig_split_struct_ints(s);
...@@ -15623,13 +15618,11 @@ void run_c_tests(void) {...@@ -15623,13 +15618,11 @@ void run_c_tests(void) {
15623#endif15618#endif
15624#endif15619#endif
15625#endif15620#endif
15626#endif
1562715621
15628#ifndef __hexagon__15622#ifndef __hexagon__
15629#ifndef __loongarch__15623#ifndef __loongarch__
15630#ifndef ZIG_MIPS6415624#ifndef ZIG_MIPS64
15631#ifndef __powerpc__15625#ifndef __powerpc__
15632#ifndef __s390x__
15633 {15626 {
15634 struct MedStructMixed s = {1234, 100.0f, 1337.0f};15627 struct MedStructMixed s = {1234, 100.0f, 1337.0f};
15635 zig_med_struct_mixed(s);15628 zig_med_struct_mixed(s);
...@@ -15638,14 +15631,12 @@ void run_c_tests(void) {...@@ -15638,14 +15631,12 @@ void run_c_tests(void) {
15638#endif15631#endif
15639#endif15632#endif
15640#endif15633#endif
15641#endif
1564215634
15643#ifndef __hexagon__15635#ifndef __hexagon__
15644#ifndef __i386__15636#ifndef __i386__
15645#ifndef __loongarch__15637#ifndef __loongarch__
15646#ifndef ZIG_MIPS6415638#ifndef ZIG_MIPS64
15647#ifndef __powerpc__15639#ifndef __powerpc__
15648#ifndef __s390x__
15649 {15640 {
15650 struct SplitStructMixed s = {1234, 100, 1337.0f};15641 struct SplitStructMixed s = {1234, 100, 1337.0f};
15651 zig_split_struct_mixed(s);15642 zig_split_struct_mixed(s);
...@@ -15655,13 +15646,11 @@ void run_c_tests(void) {...@@ -15655,13 +15646,11 @@ void run_c_tests(void) {
15655#endif15646#endif
15656#endif15647#endif
15657#endif15648#endif
15658#endif
1565915649
15660#ifndef __hexagon__15650#ifndef __hexagon__
15661#ifndef __loongarch__15651#ifndef __loongarch__
15662#ifndef ZIG_MIPS6415652#ifndef ZIG_MIPS64
15663#ifndef __powerpc__15653#ifndef __powerpc__
15664#ifndef __s390x__
15665 {15654 {
15666 struct BigStruct s = {30, 31, 32, 33, 34};15655 struct BigStruct s = {30, 31, 32, 33, 34};
15667 struct BigStruct res = zig_big_struct_both(s);15656 struct BigStruct res = zig_big_struct_both(s);
...@@ -15674,7 +15663,6 @@ void run_c_tests(void) {...@@ -15674,7 +15663,6 @@ void run_c_tests(void) {
15674#endif15663#endif
15675#endif15664#endif
15676#endif15665#endif
15677#endif
15678#endif15666#endif
1567915667
15680 {15668 {
test/c_abi/main.zig+1-114
...@@ -13,7 +13,7 @@ const expectEqual = std.testing.expectEqual;...@@ -13,7 +13,7 @@ const expectEqual = std.testing.expectEqual;
13const have_i128 = builtin.cpu.arch != .x86 and !builtin.cpu.arch.isArm() and13const have_i128 = builtin.cpu.arch != .x86 and !builtin.cpu.arch.isArm() and
14 !builtin.cpu.arch.isMIPS() and !builtin.cpu.arch.isPowerPC32() and builtin.cpu.arch != .riscv32 and14 !builtin.cpu.arch.isMIPS() and !builtin.cpu.arch.isPowerPC32() and builtin.cpu.arch != .riscv32 and
15 builtin.cpu.arch != .hexagon and15 builtin.cpu.arch != .hexagon and
16 builtin.cpu.arch != .s390x; // https://github.com/llvm/llvm-project/issues/16846016 builtin.cpu.arch != .s390x;
1717
18const have_f128 = builtin.cpu.arch.isWasm() or (builtin.cpu.arch.isX86() and !builtin.os.tag.isDarwin() and builtin.abi != .msvc);18const have_f128 = builtin.cpu.arch.isWasm() or (builtin.cpu.arch.isX86() and !builtin.os.tag.isDarwin() and builtin.abi != .msvc);
19const have_f80 = builtin.cpu.arch.isX86() and builtin.abi != .msvc;19const have_f80 = builtin.cpu.arch.isX86() and builtin.abi != .msvc;
...@@ -5136,7 +5136,6 @@ test "@Vector(24, u8)" {...@@ -5136,7 +5136,6 @@ test "@Vector(24, u8)" {
5136 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;5136 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
5137 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;5137 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
5138 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;5138 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
5139 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
51405139
5141 const v = c_ret_vector_24_u8();5140 const v = c_ret_vector_24_u8();
5142 try expect(v[0] == 57);5141 try expect(v[0] == 57);
...@@ -5220,7 +5219,6 @@ test "@Vector(32, u8)" {...@@ -5220,7 +5219,6 @@ test "@Vector(32, u8)" {
5220 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;5219 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
5221 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;5220 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
5222 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;5221 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
5223 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
52245222
5225 const v = c_ret_vector_32_u8();5223 const v = c_ret_vector_32_u8();
5226 try expect(v[0] == 69);5224 try expect(v[0] == 69);
...@@ -5330,7 +5328,6 @@ test "@Vector(48, u8)" {...@@ -5330,7 +5328,6 @@ test "@Vector(48, u8)" {
5330 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;5328 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
5331 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;5329 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
5332 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;5330 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
5333 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
53345331
5335 const v = c_ret_vector_48_u8();5332 const v = c_ret_vector_48_u8();
5336 try expect(v[0] == 29);5333 try expect(v[0] == 29);
...@@ -5473,7 +5470,6 @@ test "@Vector(64, u8)" {...@@ -5473,7 +5470,6 @@ test "@Vector(64, u8)" {
5473 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;5470 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
5474 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;5471 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
5475 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;5472 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
5476 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
54775473
5478 const v = c_ret_vector_64_u8();5474 const v = c_ret_vector_64_u8();
5479 try expect(v[0] == 53);5475 try expect(v[0] == 53);
...@@ -5668,7 +5664,6 @@ test "@Vector(96, u8)" {...@@ -5668,7 +5664,6 @@ test "@Vector(96, u8)" {
5668 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;5664 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
5669 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;5665 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
5670 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;5666 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
5671 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
56725667
5673 const v = c_ret_vector_96_u8();5668 const v = c_ret_vector_96_u8();
5674 try expect(v[0] == 82);5669 try expect(v[0] == 82);
...@@ -5931,7 +5926,6 @@ test "@Vector(128, u8)" {...@@ -5931,7 +5926,6 @@ test "@Vector(128, u8)" {
5931 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;5926 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
5932 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;5927 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
5933 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;5928 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
5934 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
59355929
5936 const v = c_ret_vector_128_u8();5930 const v = c_ret_vector_128_u8();
5937 try expect(v[0] == 30);5931 try expect(v[0] == 30);
...@@ -6296,7 +6290,6 @@ test "@Vector(192, u8)" {...@@ -6296,7 +6290,6 @@ test "@Vector(192, u8)" {
6296 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;6290 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
6297 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;6291 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
6298 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;6292 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
6299 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
63006293
6301 const v = c_ret_vector_192_u8();6294 const v = c_ret_vector_192_u8();
6302 try expect(v[0] == 70);6295 try expect(v[0] == 70);
...@@ -6797,7 +6790,6 @@ test "@Vector(256, u8)" {...@@ -6797,7 +6790,6 @@ test "@Vector(256, u8)" {
6797 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;6790 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
6798 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;6791 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
6799 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;6792 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
6800 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
68016793
6802 const v = c_ret_vector_256_u8();6794 const v = c_ret_vector_256_u8();
6803 try expect(v[0] == 66);6795 try expect(v[0] == 66);
...@@ -7502,7 +7494,6 @@ test "@Vector(384, u8)" {...@@ -7502,7 +7494,6 @@ test "@Vector(384, u8)" {
7502 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;7494 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
7503 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;7495 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
7504 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;7496 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
7505 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
75067497
7507 const v = c_ret_vector_384_u8();7498 const v = c_ret_vector_384_u8();
7508 try expect(v[0] == 46);7499 try expect(v[0] == 46);
...@@ -8479,7 +8470,6 @@ test "@Vector(512, u8)" {...@@ -8479,7 +8470,6 @@ test "@Vector(512, u8)" {
8479 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;8470 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
8480 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;8471 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
8481 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;8472 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
8482 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
84838473
8484 const v = c_ret_vector_512_u8();8474 const v = c_ret_vector_512_u8();
8485 try expect(v[0] == 38);8475 try expect(v[0] == 38);
...@@ -9250,7 +9240,6 @@ test "@Vector(12, u16)" {...@@ -9250,7 +9240,6 @@ test "@Vector(12, u16)" {
9250 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;9240 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
9251 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;9241 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
9252 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;9242 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
9253 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
92549243
9255 const v = c_ret_vector_12_u16();9244 const v = c_ret_vector_12_u16();
9256 try expect(v[0] == 121);9245 try expect(v[0] == 121);
...@@ -9300,7 +9289,6 @@ test "@Vector(16, u16)" {...@@ -9300,7 +9289,6 @@ test "@Vector(16, u16)" {
9300 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;9289 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
9301 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;9290 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
9302 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;9291 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
9303 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
93049292
9305 const v = c_ret_vector_16_u16();9293 const v = c_ret_vector_16_u16();
9306 try expect(v[0] == 177);9294 try expect(v[0] == 177);
...@@ -9366,7 +9354,6 @@ test "@Vector(24, u16)" {...@@ -9366,7 +9354,6 @@ test "@Vector(24, u16)" {
9366 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;9354 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
9367 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;9355 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
9368 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;9356 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
9369 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
93709357
9371 const v = c_ret_vector_24_u16();9358 const v = c_ret_vector_24_u16();
9372 try expect(v[0] == 257);9359 try expect(v[0] == 257);
...@@ -9450,7 +9437,6 @@ test "@Vector(32, u16)" {...@@ -9450,7 +9437,6 @@ test "@Vector(32, u16)" {
9450 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;9437 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
9451 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;9438 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
9452 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;9439 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
9453 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
94549440
9455 const v = c_ret_vector_32_u16();9441 const v = c_ret_vector_32_u16();
9456 try expect(v[0] == 369);9442 try expect(v[0] == 369);
...@@ -9560,7 +9546,6 @@ test "@Vector(48, u16)" {...@@ -9560,7 +9546,6 @@ test "@Vector(48, u16)" {
9560 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;9546 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
9561 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;9547 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
9562 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;9548 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
9563 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
95649549
9565 const v = c_ret_vector_48_u16();9550 const v = c_ret_vector_48_u16();
9566 try expect(v[0] == 529);9551 try expect(v[0] == 529);
...@@ -9704,7 +9689,6 @@ test "@Vector(64, u16)" {...@@ -9704,7 +9689,6 @@ test "@Vector(64, u16)" {
9704 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;9689 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
9705 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;9690 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
9706 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;9691 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
9707 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
97089692
9709 const v = c_ret_vector_64_u16();9693 const v = c_ret_vector_64_u16();
9710 try expect(v[0] == 753);9694 try expect(v[0] == 753);
...@@ -9899,7 +9883,6 @@ test "@Vector(96, u16)" {...@@ -9899,7 +9883,6 @@ test "@Vector(96, u16)" {
9899 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;9883 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
9900 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;9884 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
9901 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;9885 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
9902 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
99039886
9904 const v = c_ret_vector_96_u16();9887 const v = c_ret_vector_96_u16();
9905 try expect(v[0] == 1082);9888 try expect(v[0] == 1082);
...@@ -10162,7 +10145,6 @@ test "@Vector(128, u16)" {...@@ -10162,7 +10145,6 @@ test "@Vector(128, u16)" {
10162 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;10145 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
10163 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;10146 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
10164 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;10147 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
10165 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1016610148
10167 const v = c_ret_vector_128_u16();10149 const v = c_ret_vector_128_u16();
10168 try expect(v[0] == 1530);10150 try expect(v[0] == 1530);
...@@ -10527,7 +10509,6 @@ test "@Vector(192, u16)" {...@@ -10527,7 +10509,6 @@ test "@Vector(192, u16)" {
10527 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;10509 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
10528 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;10510 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
10529 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;10511 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
10530 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1053110512
10532 const v = c_ret_vector_192_u16();10513 const v = c_ret_vector_192_u16();
10533 try expect(v[0] == 2170);10514 try expect(v[0] == 2170);
...@@ -11028,7 +11009,6 @@ test "@Vector(256, u16)" {...@@ -11028,7 +11009,6 @@ test "@Vector(256, u16)" {
11028 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;11009 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
11029 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;11010 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
11030 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;11011 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
11031 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1103211012
11033 const v = c_ret_vector_256_u16();11013 const v = c_ret_vector_256_u16();
11034 try expect(v[0] == 3066);11014 try expect(v[0] == 3066);
...@@ -11445,7 +11425,6 @@ test "@Vector(6, u32)" {...@@ -11445,7 +11425,6 @@ test "@Vector(6, u32)" {
11445 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;11425 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
11446 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;11426 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
11447 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;11427 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
11448 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1144911428
11450 const v = c_ret_vector_6_u32();11429 const v = c_ret_vector_6_u32();
11451 try expect(v[0] == 53);11430 try expect(v[0] == 53);
...@@ -11481,7 +11460,6 @@ test "@Vector(8, u32)" {...@@ -11481,7 +11460,6 @@ test "@Vector(8, u32)" {
11481 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;11460 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
11482 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;11461 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
11483 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;11462 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
11484 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1148511463
11486 const v = c_ret_vector_8_u32();11464 const v = c_ret_vector_8_u32();
11487 try expect(v[0] == 81);11465 try expect(v[0] == 81);
...@@ -11524,7 +11502,6 @@ test "@Vector(12, u32)" {...@@ -11524,7 +11502,6 @@ test "@Vector(12, u32)" {
11524 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;11502 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
11525 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;11503 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
11526 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;11504 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
11527 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1152811505
11529 const v = c_ret_vector_12_u32();11506 const v = c_ret_vector_12_u32();
11530 try expect(v[0] == 121);11507 try expect(v[0] == 121);
...@@ -11574,7 +11551,6 @@ test "@Vector(16, u32)" {...@@ -11574,7 +11551,6 @@ test "@Vector(16, u32)" {
11574 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;11551 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
11575 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;11552 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
11576 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;11553 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
11577 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1157811554
11579 const v = c_ret_vector_16_u32();11555 const v = c_ret_vector_16_u32();
11580 try expect(v[0] == 177);11556 try expect(v[0] == 177);
...@@ -11640,7 +11616,6 @@ test "@Vector(24, u32)" {...@@ -11640,7 +11616,6 @@ test "@Vector(24, u32)" {
11640 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;11616 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
11641 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;11617 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
11642 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;11618 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
11643 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1164411619
11645 const v = c_ret_vector_24_u32();11620 const v = c_ret_vector_24_u32();
11646 try expect(v[0] == 257);11621 try expect(v[0] == 257);
...@@ -11725,7 +11700,6 @@ test "@Vector(32, u32)" {...@@ -11725,7 +11700,6 @@ test "@Vector(32, u32)" {
11725 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;11700 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
11726 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;11701 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
11727 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;11702 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
11728 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1172911703
11730 const v = c_ret_vector_32_u32();11704 const v = c_ret_vector_32_u32();
11731 try expect(v[0] == 369);11705 try expect(v[0] == 369);
...@@ -11835,7 +11809,6 @@ test "@Vector(48, u32)" {...@@ -11835,7 +11809,6 @@ test "@Vector(48, u32)" {
11835 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;11809 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
11836 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;11810 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
11837 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;11811 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
11838 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1183911812
11840 const v = c_ret_vector_48_u32();11813 const v = c_ret_vector_48_u32();
11841 try expect(v[0] == 529);11814 try expect(v[0] == 529);
...@@ -11979,7 +11952,6 @@ test "@Vector(64, u32)" {...@@ -11979,7 +11952,6 @@ test "@Vector(64, u32)" {
11979 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;11952 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
11980 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;11953 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
11981 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;11954 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
11982 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1198311955
11984 const v = c_ret_vector_64_u32();11956 const v = c_ret_vector_64_u32();
11985 try expect(v[0] == 753);11957 try expect(v[0] == 753);
...@@ -12174,7 +12146,6 @@ test "@Vector(96, u32)" {...@@ -12174,7 +12146,6 @@ test "@Vector(96, u32)" {
12174 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;12146 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
12175 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;12147 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
12176 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;12148 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
12177 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1217812149
12179 const v = c_ret_vector_96_u32();12150 const v = c_ret_vector_96_u32();
12180 try expect(v[0] == 1082);12151 try expect(v[0] == 1082);
...@@ -12437,7 +12408,6 @@ test "@Vector(128, u32)" {...@@ -12437,7 +12408,6 @@ test "@Vector(128, u32)" {
12437 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;12408 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
12438 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;12409 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
12439 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;12410 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
12440 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1244112411
12442 const v = c_ret_vector_128_u32();12412 const v = c_ret_vector_128_u32();
12443 try expect(v[0] == 1530);12413 try expect(v[0] == 1530);
...@@ -12644,7 +12614,6 @@ test "@Vector(3, u64)" {...@@ -12644,7 +12614,6 @@ test "@Vector(3, u64)" {
12644 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;12614 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
12645 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;12615 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
12646 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;12616 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
12647 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1264812617
12649 const v = c_ret_vector_3_u64();12618 const v = c_ret_vector_3_u64();
12650 try expect(v[0] == 19);12619 try expect(v[0] == 19);
...@@ -12673,7 +12642,6 @@ test "@Vector(4, u64)" {...@@ -12673,7 +12642,6 @@ test "@Vector(4, u64)" {
12673 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;12642 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
12674 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;12643 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
12675 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;12644 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
12676 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1267712645
12678 const v = c_ret_vector_4_u64();12646 const v = c_ret_vector_4_u64();
12679 try expect(v[0] == 33);12647 try expect(v[0] == 33);
...@@ -12740,7 +12708,6 @@ test "@Vector(8, u64)" {...@@ -12740,7 +12708,6 @@ test "@Vector(8, u64)" {
12740 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;12708 if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
12741 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;12709 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
12742 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;12710 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
12743 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1274412711
12745 const v = c_ret_vector_8_u64();12712 const v = c_ret_vector_8_u64();
12746 try expect(v[0] == 81);12713 try expect(v[0] == 81);
...@@ -12832,7 +12799,6 @@ test "@Vector(16, u64)" {...@@ -12832,7 +12799,6 @@ test "@Vector(16, u64)" {
12832 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;12799 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
12833 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;12800 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
12834 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;12801 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
12835 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1283612802
12837 const v = c_ret_vector_16_u64();12803 const v = c_ret_vector_16_u64();
12838 try expect(v[0] == 177);12804 try expect(v[0] == 177);
...@@ -12981,7 +12947,6 @@ test "@Vector(32, u64)" {...@@ -12981,7 +12947,6 @@ test "@Vector(32, u64)" {
12981 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;12947 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
12982 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;12948 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
12983 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;12949 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
12984 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1298512950
12986 const v = c_ret_vector_32_u64();12951 const v = c_ret_vector_32_u64();
12987 try expect(v[0] == 369);12952 try expect(v[0] == 369);
...@@ -13233,7 +13198,6 @@ test "@Vector(64, u64)" {...@@ -13233,7 +13198,6 @@ test "@Vector(64, u64)" {
13233 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;13198 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
13234 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;13199 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
13235 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;13200 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
13236 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1323713201
13238 const v = c_ret_vector_64_u64();13202 const v = c_ret_vector_64_u64();
13239 try expect(v[0] == 753);13203 try expect(v[0] == 753);
...@@ -13449,7 +13413,6 @@ test "@Vector(6, f32)" {...@@ -13449,7 +13413,6 @@ test "@Vector(6, f32)" {
13449 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;13413 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
13450 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;13414 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
13451 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;13415 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
13452 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1345313416
13454 const v = c_ret_vector_6_f32();13417 const v = c_ret_vector_6_f32();
13455 try expect(v[0] == 53);13418 try expect(v[0] == 53);
...@@ -13486,7 +13449,6 @@ test "@Vector(8, f32)" {...@@ -13486,7 +13449,6 @@ test "@Vector(8, f32)" {
13486 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;13449 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
13487 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;13450 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
13488 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;13451 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
13489 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1349013452
13491 const v = c_ret_vector_8_f32();13453 const v = c_ret_vector_8_f32();
13492 try expect(v[0] == 81);13454 try expect(v[0] == 81);
...@@ -13529,7 +13491,6 @@ test "@Vector(12, f32)" {...@@ -13529,7 +13491,6 @@ test "@Vector(12, f32)" {
13529 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;13491 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
13530 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;13492 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
13531 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;13493 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
13532 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1353313494
13534 const v = c_ret_vector_12_f32();13495 const v = c_ret_vector_12_f32();
13535 try expect(v[0] == 121);13496 try expect(v[0] == 121);
...@@ -13580,7 +13541,6 @@ test "@Vector(16, f32)" {...@@ -13580,7 +13541,6 @@ test "@Vector(16, f32)" {
13580 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;13541 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
13581 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;13542 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
13582 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;13543 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
13583 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1358413544
13585 const v = c_ret_vector_16_f32();13545 const v = c_ret_vector_16_f32();
13586 try expect(v[0] == 177);13546 try expect(v[0] == 177);
...@@ -13646,7 +13606,6 @@ test "@Vector(24, f32)" {...@@ -13646,7 +13606,6 @@ test "@Vector(24, f32)" {
13646 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;13606 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
13647 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;13607 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
13648 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;13608 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
13649 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1365013609
13651 const v = c_ret_vector_24_f32();13610 const v = c_ret_vector_24_f32();
13652 try expect(v[0] == 257);13611 try expect(v[0] == 257);
...@@ -13731,7 +13690,6 @@ test "@Vector(32, f32)" {...@@ -13731,7 +13690,6 @@ test "@Vector(32, f32)" {
13731 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;13690 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
13732 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;13691 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
13733 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;13692 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
13734 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1373513693
13736 const v = c_ret_vector_32_f32();13694 const v = c_ret_vector_32_f32();
13737 try expect(v[0] == 369);13695 try expect(v[0] == 369);
...@@ -13841,7 +13799,6 @@ test "@Vector(48, f32)" {...@@ -13841,7 +13799,6 @@ test "@Vector(48, f32)" {
13841 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;13799 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
13842 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;13800 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
13843 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;13801 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
13844 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1384513802
13846 const v = c_ret_vector_48_f32();13803 const v = c_ret_vector_48_f32();
13847 try expect(v[0] == 529);13804 try expect(v[0] == 529);
...@@ -13985,7 +13942,6 @@ test "@Vector(64, f32)" {...@@ -13985,7 +13942,6 @@ test "@Vector(64, f32)" {
13985 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;13942 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
13986 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;13943 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
13987 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;13944 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
13988 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1398913945
13990 const v = c_ret_vector_64_f32();13946 const v = c_ret_vector_64_f32();
13991 try expect(v[0] == 753);13947 try expect(v[0] == 753);
...@@ -14180,7 +14136,6 @@ test "@Vector(96, f32)" {...@@ -14180,7 +14136,6 @@ test "@Vector(96, f32)" {
14180 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;14136 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
14181 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;14137 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
14182 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;14138 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
14183 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1418414139
14185 const v = c_ret_vector_96_f32();14140 const v = c_ret_vector_96_f32();
14186 try expect(v[0] == 1082);14141 try expect(v[0] == 1082);
...@@ -14443,7 +14398,6 @@ test "@Vector(128, f32)" {...@@ -14443,7 +14398,6 @@ test "@Vector(128, f32)" {
14443 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;14398 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
14444 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;14399 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
14445 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;14400 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
14446 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1444714401
14448 const v = c_ret_vector_128_f32();14402 const v = c_ret_vector_128_f32();
14449 try expect(v[0] == 1530);14403 try expect(v[0] == 1530);
...@@ -14651,7 +14605,6 @@ test "@Vector(3, f64)" {...@@ -14651,7 +14605,6 @@ test "@Vector(3, f64)" {
14651 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;14605 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
14652 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;14606 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
14653 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;14607 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
14654 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1465514608
14656 const v = c_ret_vector_3_f64();14609 const v = c_ret_vector_3_f64();
14657 try expect(v[0] == 19);14610 try expect(v[0] == 19);
...@@ -14680,7 +14633,6 @@ test "@Vector(4, f64)" {...@@ -14680,7 +14633,6 @@ test "@Vector(4, f64)" {
14680 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;14633 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
14681 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;14634 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
14682 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;14635 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
14683 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
14684 if (builtin.cpu.arch.isArm()) return error.SkipZigTest; // https://codeberg.org/ziglang/zig/issues/3589914636 if (builtin.cpu.arch.isArm()) return error.SkipZigTest; // https://codeberg.org/ziglang/zig/issues/35899
1468514637
14686 const v = c_ret_vector_4_f64();14638 const v = c_ret_vector_4_f64();
...@@ -14714,7 +14666,6 @@ test "@Vector(6, f64)" {...@@ -14714,7 +14666,6 @@ test "@Vector(6, f64)" {
14714 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;14666 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
14715 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;14667 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
14716 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;14668 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
14717 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1471814669
14719 const v = c_ret_vector_6_f64();14670 const v = c_ret_vector_6_f64();
14720 try expect(v[0] == 53);14671 try expect(v[0] == 53);
...@@ -14750,7 +14701,6 @@ test "@Vector(8, f64)" {...@@ -14750,7 +14701,6 @@ test "@Vector(8, f64)" {
14750 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;14701 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
14751 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;14702 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
14752 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;14703 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
14753 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
14754 if (builtin.cpu.arch.isArm()) return error.SkipZigTest; // https://codeberg.org/ziglang/zig/issues/3589914704 if (builtin.cpu.arch.isArm()) return error.SkipZigTest; // https://codeberg.org/ziglang/zig/issues/35899
1475514705
14756 const v = c_ret_vector_8_f64();14706 const v = c_ret_vector_8_f64();
...@@ -14794,7 +14744,6 @@ test "@Vector(12, f64)" {...@@ -14794,7 +14744,6 @@ test "@Vector(12, f64)" {
14794 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;14744 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
14795 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;14745 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
14796 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;14746 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
14797 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1479814747
14799 const v = c_ret_vector_12_f64();14748 const v = c_ret_vector_12_f64();
14800 try expect(v[0] == 121);14749 try expect(v[0] == 121);
...@@ -14845,7 +14794,6 @@ test "@Vector(16, f64)" {...@@ -14845,7 +14794,6 @@ test "@Vector(16, f64)" {
14845 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;14794 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
14846 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;14795 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
14847 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;14796 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
14848 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1484914797
14850 const v = c_ret_vector_16_f64();14798 const v = c_ret_vector_16_f64();
14851 try expect(v[0] == 177);14799 try expect(v[0] == 177);
...@@ -14911,7 +14859,6 @@ test "@Vector(24, f64)" {...@@ -14911,7 +14859,6 @@ test "@Vector(24, f64)" {
14911 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;14859 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
14912 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;14860 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
14913 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;14861 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
14914 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1491514862
14916 const v = c_ret_vector_24_f64();14863 const v = c_ret_vector_24_f64();
14917 try expect(v[0] == 257);14864 try expect(v[0] == 257);
...@@ -14996,7 +14943,6 @@ test "@Vector(32, f64)" {...@@ -14996,7 +14943,6 @@ test "@Vector(32, f64)" {
14996 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;14943 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
14997 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;14944 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
14998 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;14945 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
14999 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1500014946
15001 const v = c_ret_vector_32_f64();14947 const v = c_ret_vector_32_f64();
15002 try expect(v[0] == 369);14948 try expect(v[0] == 369);
...@@ -15106,7 +15052,6 @@ test "@Vector(48, f64)" {...@@ -15106,7 +15052,6 @@ test "@Vector(48, f64)" {
15106 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;15052 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
15107 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;15053 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
15108 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;15054 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
15109 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1511015055
15111 const v = c_ret_vector_48_f64();15056 const v = c_ret_vector_48_f64();
15112 try expect(v[0] == 529);15057 try expect(v[0] == 529);
...@@ -15250,7 +15195,6 @@ test "@Vector(64, f64)" {...@@ -15250,7 +15195,6 @@ test "@Vector(64, f64)" {
15250 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;15195 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
15251 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;15196 if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
15252 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;15197 if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
15253 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1525415198
15255 const v = c_ret_vector_64_f64();15199 const v = c_ret_vector_64_f64();
15256 try expect(v[0] == 753);15200 try expect(v[0] == 753);
...@@ -15345,7 +15289,6 @@ extern fn c_test_struct_u8() void;...@@ -15345,7 +15289,6 @@ extern fn c_test_struct_u8() void;
15345test "struct u8" {15289test "struct u8" {
15346 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15290 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15347 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;15291 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
15348 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15349 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;15292 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;
1535015293
15351 const s = c_ret_struct_u8();15294 const s = c_ret_struct_u8();
...@@ -15377,7 +15320,6 @@ test "struct u8, u8" {...@@ -15377,7 +15320,6 @@ test "struct u8, u8" {
15377 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;15320 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
15378 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15321 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15379 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15322 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
15380 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15381 if (builtin.cpu.arch == .x86) return error.SkipZigTest;15323 if (builtin.cpu.arch == .x86) return error.SkipZigTest;
1538215324
15383 const s = c_ret_struct_u8_u8();15325 const s = c_ret_struct_u8_u8();
...@@ -15412,7 +15354,6 @@ test "struct u8, u8, u8" {...@@ -15412,7 +15354,6 @@ test "struct u8, u8, u8" {
15412 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;15354 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
15413 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15355 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15414 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15356 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
15415 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15416 if (builtin.cpu.arch == .x86) return error.SkipZigTest;15357 if (builtin.cpu.arch == .x86) return error.SkipZigTest;
1541715358
15418 const s = c_ret_struct_u8_u8_u8();15359 const s = c_ret_struct_u8_u8_u8();
...@@ -15450,7 +15391,6 @@ test "struct u8, u8, u8, u8" {...@@ -15450,7 +15391,6 @@ test "struct u8, u8, u8, u8" {
15450 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;15391 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
15451 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15392 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15452 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15393 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
15453 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15454 if (builtin.cpu.arch == .x86) return error.SkipZigTest;15394 if (builtin.cpu.arch == .x86) return error.SkipZigTest;
1545515395
15456 const s = c_ret_struct_u8_u8_u8_u8();15396 const s = c_ret_struct_u8_u8_u8_u8();
...@@ -15481,7 +15421,6 @@ extern fn c_test_struct_u16() void;...@@ -15481,7 +15421,6 @@ extern fn c_test_struct_u16() void;
15481test "struct u16" {15421test "struct u16" {
15482 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15422 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15483 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;15423 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
15484 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15485 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;15424 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;
1548615425
15487 const s = c_ret_struct_u16();15426 const s = c_ret_struct_u16();
...@@ -15513,7 +15452,6 @@ test "struct u16, u16" {...@@ -15513,7 +15452,6 @@ test "struct u16, u16" {
15513 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;15452 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
15514 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15453 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15515 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15454 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
15516 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15517 if (builtin.cpu.arch == .x86) return error.SkipZigTest;15455 if (builtin.cpu.arch == .x86) return error.SkipZigTest;
1551815456
15519 const s = c_ret_struct_u16_u16();15457 const s = c_ret_struct_u16_u16();
...@@ -15549,7 +15487,6 @@ test "struct u16, u16, u16" {...@@ -15549,7 +15487,6 @@ test "struct u16, u16, u16" {
15549 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15487 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15550 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15488 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
15551 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;15489 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;
15552 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15553 if (builtin.cpu.arch == .x86) return error.SkipZigTest;15490 if (builtin.cpu.arch == .x86) return error.SkipZigTest;
1555415491
15555 const s = c_ret_struct_u16_u16_u16();15492 const s = c_ret_struct_u16_u16_u16();
...@@ -15588,7 +15525,6 @@ test "struct u16, u16, u16, u16" {...@@ -15588,7 +15525,6 @@ test "struct u16, u16, u16, u16" {
15588 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15525 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15589 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15526 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
15590 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;15527 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;
15591 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15592 if (builtin.cpu.arch == .x86) return error.SkipZigTest;15528 if (builtin.cpu.arch == .x86) return error.SkipZigTest;
1559315529
15594 const s = c_ret_struct_u16_u16_u16_u16();15530 const s = c_ret_struct_u16_u16_u16_u16();
...@@ -15619,7 +15555,6 @@ extern fn c_test_struct_u32() void;...@@ -15619,7 +15555,6 @@ extern fn c_test_struct_u32() void;
15619test "struct u32" {15555test "struct u32" {
15620 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15556 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15621 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;15557 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
15622 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15623 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;15558 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;
1562415559
15625 const s = c_ret_struct_u32();15560 const s = c_ret_struct_u32();
...@@ -15651,7 +15586,6 @@ test "struct u32, u32" {...@@ -15651,7 +15586,6 @@ test "struct u32, u32" {
15651 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15586 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15652 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15587 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
15653 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;15588 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;
15654 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15655 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;15589 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;
1565615590
15657 const s = c_ret_struct_u32_u32();15591 const s = c_ret_struct_u32_u32();
...@@ -15686,7 +15620,6 @@ test "struct u32, u32, u32" {...@@ -15686,7 +15620,6 @@ test "struct u32, u32, u32" {
15686 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;15620 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
15687 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15621 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15688 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15622 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
15689 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1569015623
15691 const s = c_ret_struct_u32_u32_u32();15624 const s = c_ret_struct_u32_u32_u32();
15692 try expect(s.a == 8);15625 try expect(s.a == 8);
...@@ -15723,7 +15656,6 @@ test "struct u32, u32, u32, u32" {...@@ -15723,7 +15656,6 @@ test "struct u32, u32, u32, u32" {
15723 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;15656 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
15724 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15657 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15725 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15658 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
15726 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1572715659
15728 const s = c_ret_struct_u32_u32_u32_u32();15660 const s = c_ret_struct_u32_u32_u32_u32();
15729 try expect(s.a == 10);15661 try expect(s.a == 10);
...@@ -15753,7 +15685,6 @@ extern fn c_test_struct_u64() void;...@@ -15753,7 +15685,6 @@ extern fn c_test_struct_u64() void;
15753test "struct u64" {15685test "struct u64" {
15754 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;15686 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
15755 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;15687 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;
15756 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15757 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;15688 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;
1575815689
15759 const s = c_ret_struct_u64();15690 const s = c_ret_struct_u64();
...@@ -15831,7 +15762,6 @@ extern fn c_test_struct_u64_u64() void;...@@ -15831,7 +15762,6 @@ extern fn c_test_struct_u64_u64() void;
15831test "struct u64, u64" {15762test "struct u64, u64" {
15832 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;15763 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
15833 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;15764 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
15834 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1583515765
15836 const s = c_ret_struct_u64_u64();15766 const s = c_ret_struct_u64_u64();
15837 try expect(s.a == 21);15767 try expect(s.a == 21);
...@@ -15872,7 +15802,6 @@ test "struct u64, u64, u64" {...@@ -15872,7 +15802,6 @@ test "struct u64, u64, u64" {
15872 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;15802 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
15873 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;15803 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
15874 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15804 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
15875 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1587615805
15877 const s = c_ret_struct_u64_u64_u64();15806 const s = c_ret_struct_u64_u64_u64();
15878 try expect(s.a == 8);15807 try expect(s.a == 8);
...@@ -15908,7 +15837,6 @@ test "struct u64, u64, u64, u64" {...@@ -15908,7 +15837,6 @@ test "struct u64, u64, u64, u64" {
15908 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;15837 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
15909 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;15838 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
15910 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15839 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
15911 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1591215840
15913 const s = c_ret_struct_u64_u64_u64_u64();15841 const s = c_ret_struct_u64_u64_u64_u64();
15914 try expect(s.a == 10);15842 try expect(s.a == 10);
...@@ -15938,7 +15866,6 @@ extern fn c_test_struct_f32() void;...@@ -15938,7 +15866,6 @@ extern fn c_test_struct_f32() void;
15938test "struct f32" {15866test "struct f32" {
15939 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15867 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15940 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;15868 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
15941 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15942 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;15869 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;
1594315870
15944 const s = c_ret_struct_f32();15871 const s = c_ret_struct_f32();
...@@ -15971,7 +15898,6 @@ test "struct f32, f32" {...@@ -15971,7 +15898,6 @@ test "struct f32, f32" {
15971 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15898 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
15972 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15899 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
15973 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;15900 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;
15974 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
15975 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;15901 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;
1597615902
15977 const s = c_ret_struct_f32_f32();15903 const s = c_ret_struct_f32_f32();
...@@ -16007,7 +15933,6 @@ test "struct f32, f32, f32" {...@@ -16007,7 +15933,6 @@ test "struct f32, f32, f32" {
16007 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;15933 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
16008 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15934 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16009 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15935 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16010 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1601115936
16012 const s = c_ret_struct_f32_f32_f32();15937 const s = c_ret_struct_f32_f32_f32();
16013 try expect(s.a == 8);15938 try expect(s.a == 8);
...@@ -16045,7 +15970,6 @@ test "struct f32, f32, f32, f32" {...@@ -16045,7 +15970,6 @@ test "struct f32, f32, f32, f32" {
16045 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;15970 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
16046 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;15971 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16047 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;15972 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16048 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1604915973
16050 const s = c_ret_struct_f32_f32_f32_f32();15974 const s = c_ret_struct_f32_f32_f32_f32();
16051 try expect(s.a == 10);15975 try expect(s.a == 10);
...@@ -16085,7 +16009,6 @@ test "struct f32, f32, f32, f32, f32" {...@@ -16085,7 +16009,6 @@ test "struct f32, f32, f32, f32, f32" {
16085 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;16009 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
16086 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16010 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16087 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16011 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16088 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1608916012
16090 const s = c_ret_struct_f32_f32_f32_f32_f32();16013 const s = c_ret_struct_f32_f32_f32_f32_f32();
16091 try expect(s.a == 12);16014 try expect(s.a == 12);
...@@ -16120,7 +16043,6 @@ test "struct f32 align(8)" {...@@ -16120,7 +16043,6 @@ test "struct f32 align(8)" {
16120 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16043 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16121 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16044 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16122 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;16045 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;
16123 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16124 if (builtin.cpu.arch == .x86) return error.SkipZigTest;16046 if (builtin.cpu.arch == .x86) return error.SkipZigTest;
1612516047
16126 const s = c_ret_struct_f32a8();16048 const s = c_ret_struct_f32a8();
...@@ -16154,7 +16076,6 @@ test "struct f32 align(8), f32 align(8)" {...@@ -16154,7 +16076,6 @@ test "struct f32 align(8), f32 align(8)" {
16154 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16076 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16155 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16077 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16156 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;16078 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
16157 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16158 if (builtin.cpu.arch == .x86) return error.SkipZigTest;16079 if (builtin.cpu.arch == .x86) return error.SkipZigTest;
1615916080
16160 const s = c_ret_struct_f32a8_f32a8();16081 const s = c_ret_struct_f32a8_f32a8();
...@@ -16188,7 +16109,6 @@ test "struct {f32, f32}, f32" {...@@ -16188,7 +16109,6 @@ test "struct {f32, f32}, f32" {
16188 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;16109 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
16189 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16110 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16190 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;16111 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
16191 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1619216112
16193 const s = c_ret_struct_f32f32_f32();16113 const s = c_ret_struct_f32f32_f32();
16194 try expect(s.a.b == 1.0);16114 try expect(s.a.b == 1.0);
...@@ -16222,7 +16142,6 @@ test "struct f32, {f32, f32}" {...@@ -16222,7 +16142,6 @@ test "struct f32, {f32, f32}" {
16222 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;16142 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
16223 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16143 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16224 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;16144 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
16225 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1622616145
16227 const s = c_ret_struct_f32_f32f32();16146 const s = c_ret_struct_f32_f32f32();
16228 try expect(s.a == 1.0);16147 try expect(s.a == 1.0);
...@@ -16252,7 +16171,6 @@ test "struct f64" {...@@ -16252,7 +16171,6 @@ test "struct f64" {
16252 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;16171 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
16253 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;16172 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
16254 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;16173 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;
16255 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16256 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;16174 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;
1625716175
16258 const s = c_ret_struct_f64();16176 const s = c_ret_struct_f64();
...@@ -16283,7 +16201,6 @@ test "struct f64, f64" {...@@ -16283,7 +16201,6 @@ test "struct f64, f64" {
16283 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;16201 if (builtin.cpu.arch.isArm() and builtin.abi.float() == .soft) return error.SkipZigTest;
16284 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16202 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16285 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;16203 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
16286 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1628716204
16288 const s = c_ret_struct_f64_f64();16205 const s = c_ret_struct_f64_f64();
16289 try expect(s.a == 6);16206 try expect(s.a == 6);
...@@ -16316,7 +16233,6 @@ test "struct f64, f64, f64" {...@@ -16316,7 +16233,6 @@ test "struct f64, f64, f64" {
16316 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16233 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16317 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;16234 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
16318 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;16235 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
16319 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1632016236
16321 const s = c_ret_struct_f64_f64_f64();16237 const s = c_ret_struct_f64_f64_f64();
16322 try expect(s.a == 8);16238 try expect(s.a == 8);
...@@ -16352,7 +16268,6 @@ test "struct f64, f64, f64, f64" {...@@ -16352,7 +16268,6 @@ test "struct f64, f64, f64, f64" {
16352 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16268 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16353 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;16269 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
16354 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;16270 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
16355 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1635616271
16357 const s = c_ret_struct_f64_f64_f64_f64();16272 const s = c_ret_struct_f64_f64_f64_f64();
16358 try expect(s.a == 10);16273 try expect(s.a == 10);
...@@ -16391,7 +16306,6 @@ test "struct f64, f64, f64, f64, f64" {...@@ -16391,7 +16306,6 @@ test "struct f64, f64, f64, f64, f64" {
16391 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16306 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16392 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;16307 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
16393 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;16308 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
16394 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1639516309
16396 const s = c_ret_struct_f64_f64_f64_f64_f64();16310 const s = c_ret_struct_f64_f64_f64_f64_f64();
16397 try expect(s.a == 12);16311 try expect(s.a == 12);
...@@ -16431,7 +16345,6 @@ test "struct{u32,union{u32,struct{u32,u32}}}" {...@@ -16431,7 +16345,6 @@ test "struct{u32,union{u32,struct{u32,u32}}}" {
16431 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;16345 if (builtin.cpu.arch == .loongarch64) return error.SkipZigTest;
16432 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16346 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16433 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16347 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16434 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1643516348
16436 const s = c_ret_struct_u32_union_u32_u32u32();16349 const s = c_ret_struct_u32_union_u32_u32u32();
16437 try expect(s.a == 1);16350 try expect(s.a == 1);
...@@ -16453,7 +16366,6 @@ test "struct i32 i32" {...@@ -16453,7 +16366,6 @@ test "struct i32 i32" {
16453 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16366 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16454 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;16367 if (builtin.cpu.arch.isRiscv32()) return error.SkipZigTest;
16455 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16368 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16456 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16457 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;16369 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;
1645816370
16459 const s: Struct_i32_i32 = .{16371 const s: Struct_i32_i32 = .{
...@@ -16487,7 +16399,6 @@ test "big struct" {...@@ -16487,7 +16399,6 @@ test "big struct" {
16487 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16399 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16488 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16400 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16489 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16401 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16490 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1649116402
16492 const s = BigStruct{16403 const s = BigStruct{
16493 .a = 1,16404 .a = 1,
...@@ -16516,7 +16427,6 @@ test "big union" {...@@ -16516,7 +16427,6 @@ test "big union" {
16516 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;16427 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
16517 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16428 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16518 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16429 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16519 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1652016430
16521 const x = BigUnion{16431 const x = BigUnion{
16522 .a = BigStruct{16432 .a = BigStruct{
...@@ -16552,7 +16462,6 @@ test "medium struct of ints and floats" {...@@ -16552,7 +16462,6 @@ test "medium struct of ints and floats" {
16552 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16462 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16553 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16463 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16554 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16464 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16555 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1655616465
16557 const s = MedStructMixed{16466 const s = MedStructMixed{
16558 .a = 1234,16467 .a = 1234,
...@@ -16633,7 +16542,6 @@ test "split struct of ints" {...@@ -16633,7 +16542,6 @@ test "split struct of ints" {
16633 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16542 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16634 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16543 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16635 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16544 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16636 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1663716545
16638 const s = SplitStructInt{16546 const s = SplitStructInt{
16639 .a = 1234,16547 .a = 1234,
...@@ -16663,7 +16571,6 @@ test "split struct of ints and floats" {...@@ -16663,7 +16571,6 @@ test "split struct of ints and floats" {
16663 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16571 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16664 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16572 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16665 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16573 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16666 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1666716574
16668 const s = SplitStructMixed{16575 const s = SplitStructMixed{
16669 .a = 1234,16576 .a = 1234,
...@@ -16690,7 +16597,6 @@ test "sret and byval together" {...@@ -16690,7 +16597,6 @@ test "sret and byval together" {
16690 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16597 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16691 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16598 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16692 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16599 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16693 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1669416600
16695 const s = BigStruct{16601 const s = BigStruct{
16696 .a = 1,16602 .a = 1,
...@@ -16805,7 +16711,6 @@ test "Struct with array as padding." {...@@ -16805,7 +16711,6 @@ test "Struct with array as padding." {
16805 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16711 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16806 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16712 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16807 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16713 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16808 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1680916714
16810 c_struct_with_array(.{ .a = 1, .padding = undefined, .b = 2 });16715 c_struct_with_array(.{ .a = 1, .padding = undefined, .b = 2 });
1681116716
...@@ -16833,7 +16738,6 @@ test "Float array like struct" {...@@ -16833,7 +16738,6 @@ test "Float array like struct" {
16833 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;16738 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
16834 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16739 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16835 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16740 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16836 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1683716741
16838 c_float_array_struct(.{16742 c_float_array_struct(.{
16839 .origin = .{16743 .origin = .{
...@@ -16869,7 +16773,6 @@ test "DC: Zig passes to C" {...@@ -16869,7 +16773,6 @@ test "DC: Zig passes to C" {
16869 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16773 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16870 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16774 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16871 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16775 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16872 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16873 try expectOk(c_assert_DC(.{ .v1 = -0.25, .v2 = 15 }));16776 try expectOk(c_assert_DC(.{ .v1 = -0.25, .v2 = 15 }));
16874}16777}
16875test "DC: Zig returns to C" {16778test "DC: Zig returns to C" {
...@@ -16877,7 +16780,6 @@ test "DC: Zig returns to C" {...@@ -16877,7 +16780,6 @@ test "DC: Zig returns to C" {
16877 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;16780 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
16878 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16781 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16879 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16782 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16880 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16881 try expectOk(c_assert_ret_DC());16783 try expectOk(c_assert_ret_DC());
16882}16784}
16883test "DC: C passes to Zig" {16785test "DC: C passes to Zig" {
...@@ -16886,7 +16788,6 @@ test "DC: C passes to Zig" {...@@ -16886,7 +16788,6 @@ test "DC: C passes to Zig" {
16886 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16788 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16887 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16789 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16888 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16790 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16889 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16890 try expectOk(c_send_DC());16791 try expectOk(c_send_DC());
16891}16792}
16892test "DC: C returns to Zig" {16793test "DC: C returns to Zig" {
...@@ -16894,7 +16795,6 @@ test "DC: C returns to Zig" {...@@ -16894,7 +16795,6 @@ test "DC: C returns to Zig" {
16894 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;16795 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
16895 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16796 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16896 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16797 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16897 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16898 try expectEqual(DC{ .v1 = -0.25, .v2 = 15 }, c_ret_DC());16798 try expectEqual(DC{ .v1 = -0.25, .v2 = 15 }, c_ret_DC());
16899}16799}
1690016800
...@@ -16922,14 +16822,12 @@ test "CFF: Zig passes to C" {...@@ -16922,14 +16822,12 @@ test "CFF: Zig passes to C" {
16922 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16822 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16923 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16823 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16924 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16824 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16925 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16926 try expectOk(c_assert_CFF(.{ .v1 = 39, .v2 = 0.875, .v3 = 1.0 }));16825 try expectOk(c_assert_CFF(.{ .v1 = 39, .v2 = 0.875, .v3 = 1.0 }));
16927}16826}
16928test "CFF: Zig returns to C" {16827test "CFF: Zig returns to C" {
16929 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16828 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16930 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16829 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16931 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16830 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16932 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16933 try expectOk(c_assert_ret_CFF());16831 try expectOk(c_assert_ret_CFF());
16934}16832}
16935test "CFF: C passes to Zig" {16833test "CFF: C passes to Zig" {
...@@ -16939,7 +16837,6 @@ test "CFF: C passes to Zig" {...@@ -16939,7 +16837,6 @@ test "CFF: C passes to Zig" {
16939 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16837 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16940 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16838 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16941 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16839 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16942 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1694316840
16944 try expectOk(c_send_CFF());16841 try expectOk(c_send_CFF());
16945}16842}
...@@ -16948,7 +16845,6 @@ test "CFF: C returns to Zig" {...@@ -16948,7 +16845,6 @@ test "CFF: C returns to Zig" {
16948 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16845 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16949 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16846 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16950 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16847 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16951 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16952 try expectEqual(CFF{ .v1 = 39, .v2 = 0.875, .v3 = 1.0 }, c_ret_CFF());16848 try expectEqual(CFF{ .v1 = 39, .v2 = 0.875, .v3 = 1.0 }, c_ret_CFF());
16953}16849}
16954pub extern fn c_assert_CFF(lv: CFF) c_int;16850pub extern fn c_assert_CFF(lv: CFF) c_int;
...@@ -16975,7 +16871,6 @@ test "PD: Zig passes to C" {...@@ -16975,7 +16871,6 @@ test "PD: Zig passes to C" {
16975 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16871 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16976 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16872 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16977 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16873 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16978 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16979 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;16874 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;
16980 try expectOk(c_assert_PD(.{ .v1 = null, .v2 = 0.5 }));16875 try expectOk(c_assert_PD(.{ .v1 = null, .v2 = 0.5 }));
16981}16876}
...@@ -16983,7 +16878,6 @@ test "PD: Zig returns to C" {...@@ -16983,7 +16878,6 @@ test "PD: Zig returns to C" {
16983 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16878 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16984 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16879 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16985 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16880 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16986 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16987 try expectOk(c_assert_ret_PD());16881 try expectOk(c_assert_ret_PD());
16988}16882}
16989test "PD: C passes to Zig" {16883test "PD: C passes to Zig" {
...@@ -16991,7 +16885,6 @@ test "PD: C passes to Zig" {...@@ -16991,7 +16885,6 @@ test "PD: C passes to Zig" {
16991 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16885 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16992 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16886 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
16993 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16887 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
16994 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
16995 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;16888 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;
16996 try expectOk(c_send_PD());16889 try expectOk(c_send_PD());
16997}16890}
...@@ -16999,7 +16892,6 @@ test "PD: C returns to Zig" {...@@ -16999,7 +16892,6 @@ test "PD: C returns to Zig" {
16999 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16892 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
17000 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16893 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
17001 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16894 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
17002 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
17003 try expectEqual(PD{ .v1 = null, .v2 = 0.5 }, c_ret_PD());16895 try expectEqual(PD{ .v1 = null, .v2 = 0.5 }, c_ret_PD());
17004}16896}
17005pub extern fn c_assert_PD(lv: PD) c_int;16897pub extern fn c_assert_PD(lv: PD) c_int;
...@@ -17033,7 +16925,6 @@ extern fn c_modify_by_ref_param(ByRef) ByRef;...@@ -17033,7 +16925,6 @@ extern fn c_modify_by_ref_param(ByRef) ByRef;
17033test "C function modifies by ref param" {16925test "C function modifies by ref param" {
17034 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;16926 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
17035 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16927 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
17036 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1703716928
17038 const res = c_modify_by_ref_param(.{ .val = 1, .arr = undefined });16929 const res = c_modify_by_ref_param(.{ .val = 1, .arr = undefined });
17039 try expect(res.val == 42);16930 try expect(res.val == 42);
...@@ -17058,7 +16949,6 @@ test "C function that takes byval struct called via function pointer" {...@@ -17058,7 +16949,6 @@ test "C function that takes byval struct called via function pointer" {
17058 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;16949 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
17059 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;16950 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
17060 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;16951 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
17061 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1706216952
17063 var fn_ptr = &c_func_ptr_byval;16953 var fn_ptr = &c_func_ptr_byval;
17064 _ = &fn_ptr;16954 _ = &fn_ptr;
...@@ -17211,7 +17101,6 @@ test "Stdcall ABI structs" {...@@ -17211,7 +17101,6 @@ test "Stdcall ABI structs" {
17211 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;17101 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
17212 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;17102 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
17213 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;17103 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
17214 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
17215 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;17104 if (builtin.cpu.arch == .x86 and builtin.os.tag == .windows) return error.SkipZigTest;
1721617105
17217 const res = stdcall_coord2(17106 const res = stdcall_coord2(
...@@ -17228,7 +17117,6 @@ test "Stdcall ABI big union" {...@@ -17228,7 +17117,6 @@ test "Stdcall ABI big union" {
17228 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;17117 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
17229 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;17118 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
17230 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;17119 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
17231 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1723217120
17233 const x = BigUnion{17121 const x = BigUnion{
17234 .a = BigStruct{17122 .a = BigStruct{
...@@ -17304,7 +17192,6 @@ test "byval tail callsite attribute" {...@@ -17304,7 +17192,6 @@ test "byval tail callsite attribute" {
17304 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;17192 if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
17305 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;17193 if (builtin.cpu.arch.isLoongArch()) return error.SkipZigTest;
17306 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;17194 if (builtin.cpu.arch == .hexagon) return error.SkipZigTest;
17307 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1730817195
17309 // Originally reported at https://github.com/ziglang/zig/issues/1629017196 // Originally reported at https://github.com/ziglang/zig/issues/16290
17310 // the bug was that the extern function had the byval attribute, but17197 // the bug was that the extern function had the byval attribute, but