authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-10-20 01:41:40+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-10-20 03:29:33+02:00
log0f09c3c55a2db5b05a38ea431d0b312320a7f178
tree3aa68049eb54c03c539eb6f7cc3bb7c3cbbc48a1
parent39ca9cae4381798df67ce6640aaf9bd32b03c358
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

update_cpu_features: flesh out xcore data

LLVM's backend is very outdated so we can't extract any useful data from it.

3 files changed, 93 insertions(+), 9 deletions(-)

lib/std/Target.zig+1-1
...@@ -2070,6 +2070,7 @@ pub const Cpu = struct {...@@ -2070,6 +2070,7 @@ pub const Cpu = struct {
2070 .x86_16 => &x86.cpu.i86,2070 .x86_16 => &x86.cpu.i86,
2071 .x86 => &x86.cpu.i386,2071 .x86 => &x86.cpu.i386,
2072 .x86_64 => &x86.cpu.x86_64,2072 .x86_64 => &x86.cpu.x86_64,
2073 .xcore => &xcore.cpu.xs1b,
2073 inline else => |a| &@field(Target, @tagName(a.family())).cpu.generic,2074 inline else => |a| &@field(Target, @tagName(a.family())).cpu.generic,
2074 };2075 };
2075 }2076 }
...@@ -2157,7 +2158,6 @@ pub const Cpu = struct {...@@ -2157,7 +2158,6 @@ pub const Cpu = struct {
2157 .ps5 => &x86.cpu.znver2,2158 .ps5 => &x86.cpu.znver2,
2158 else => generic(arch),2159 else => generic(arch),
2159 },2160 },
2160 .xcore => &xcore.cpu.xs1b_generic,
2161 .xtensa => &xtensa.cpu.esp32,2161 .xtensa => &xtensa.cpu.esp32,
2162 .wasm32, .wasm64 => &wasm.cpu.lime1,2162 .wasm32, .wasm64 => &wasm.cpu.lime1,
21632163
lib/std/Target/xcore.zig+49-8
...@@ -4,7 +4,12 @@ const std = @import("../std.zig");...@@ -4,7 +4,12 @@ const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
66
7pub const Feature = enum {};7pub const Feature = enum {
8 fpu,
9 vpu,
10 xs2,
11 xs3,
12};
813
9pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;14pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
10pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;15pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
...@@ -15,6 +20,32 @@ pub const all_features = blk: {...@@ -15,6 +20,32 @@ pub const all_features = blk: {
15 const len = @typeInfo(Feature).@"enum".field_names.len;20 const len = @typeInfo(Feature).@"enum".field_names.len;
16 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);21 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
17 var result: [len]CpuFeature = undefined;22 var result: [len]CpuFeature = undefined;
23 result[@backingInt(Feature.fpu)] = .{
24 .llvm_name = null,
25 .description = "Enable single-precision floating point unit",
26 .dependencies = featureSet(&[_]Feature{
27 .xs3,
28 }),
29 };
30 result[@backingInt(Feature.vpu)] = .{
31 .llvm_name = null,
32 .description = "Enable vector processing unit",
33 .dependencies = featureSet(&[_]Feature{
34 .xs3,
35 }),
36 };
37 result[@backingInt(Feature.xs2)] = .{
38 .llvm_name = null,
39 .description = "Enable XS2 architecture",
40 .dependencies = featureSet(&[_]Feature{}),
41 };
42 result[@backingInt(Feature.xs3)] = .{
43 .llvm_name = null,
44 .description = "Enable XS3 architecture",
45 .dependencies = featureSet(&[_]Feature{
46 .xs2,
47 }),
48 };
18 const ti = @typeInfo(Feature);49 const ti = @typeInfo(Feature);
19 for (&result, 0..) |*elem, i| {50 for (&result, 0..) |*elem, i| {
20 elem.index = i;51 elem.index = i;
...@@ -24,14 +55,24 @@ pub const all_features = blk: {...@@ -24,14 +55,24 @@ pub const all_features = blk: {
24};55};
2556
26pub const cpu = struct {57pub const cpu = struct {
27 pub const generic: CpuModel = .{58 pub const xs1b: CpuModel = .{
28 .name = "generic",59 .name = "xs1b",
29 .llvm_name = "generic",60 .llvm_name = null,
30 .features = featureSet(&[_]Feature{}),61 .features = featureSet(&[_]Feature{}),
31 };62 };
32 pub const xs1b_generic: CpuModel = .{63 pub const xs2a: CpuModel = .{
33 .name = "xs1b_generic",64 .name = "xs2a",
34 .llvm_name = "xs1b-generic",65 .llvm_name = null,
35 .features = featureSet(&[_]Feature{}),66 .features = featureSet(&[_]Feature{
67 .xs2,
68 }),
69 };
70 pub const xs3a: CpuModel = .{
71 .name = "xs3a",
72 .llvm_name = null,
73 .features = featureSet(&[_]Feature{
74 .fpu,
75 .vpu,
76 }),
36 };77 };
37};78};
tools/update_cpu_features.zig+43
...@@ -2096,6 +2096,49 @@ const targets = [_]ArchTarget{...@@ -2096,6 +2096,49 @@ const targets = [_]ArchTarget{
2096 .name = "XCore",2096 .name = "XCore",
2097 .td_name = "XCore",2097 .td_name = "XCore",
2098 },2098 },
2099 .extra_features = &.{
2100 .{
2101 .zig_name = "xs2",
2102 .desc = "Enable XS2 architecture",
2103 .deps = &.{},
2104 },
2105 .{
2106 .zig_name = "xs3",
2107 .desc = "Enable XS3 architecture",
2108 .deps = &.{"xs2"},
2109 },
2110 .{
2111 .zig_name = "fpu",
2112 .desc = "Enable single-precision floating point unit",
2113 .deps = &.{"xs3"},
2114 },
2115 .{
2116 .zig_name = "vpu",
2117 .desc = "Enable vector processing unit",
2118 .deps = &.{"xs3"},
2119 },
2120 },
2121 .extra_cpus = &.{
2122 .{
2123 .llvm_name = null,
2124 .zig_name = "xs1b",
2125 .features = &.{},
2126 },
2127 .{
2128 .llvm_name = null,
2129 .zig_name = "xs2a",
2130 .features = &.{"xs2"},
2131 },
2132 .{
2133 .llvm_name = null,
2134 .zig_name = "xs3a",
2135 .features = &.{ "fpu", "vpu" },
2136 },
2137 },
2138 .omit_cpus = &.{
2139 "generic",
2140 "xs1b-generic",
2141 },
2099 },2142 },
2100 .{2143 .{
2101 .zig_name = "xtensa",2144 .zig_name = "xtensa",