authorgravatar for me@gasinfinity.devGasInfinity <me@gasinfinity.dev> 2025-10-27 11:19:51+01:00
committergravatar for me@gasinfinity.devGasInfinity <me@gasinfinity.dev> 2025-10-27 11:19:51+01:00
log104c272ae5dc0ab2fc6f81da5918f1b8abf7e131
treedf07283bc81040a74df18bc4149123bd1fa85d51
parent9d3bd3c502c4a2413c1c83a581b0711eceb37838
signaturebadge-check Signed by SSH key SHA256:p3IHbr0lyK2ekfDC1Zi7dOEV/9T6lGghNawhl5sBnM4

feat: init x86_16 arch via CBE

11 files changed, 63 insertions(+), 9 deletions(-)

lib/std/Target.zig+23-7
...@@ -1101,7 +1101,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {...@@ -1101,7 +1101,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
1101 .sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC,1101 .sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC,
1102 .sparc64 => .SPARCV9,1102 .sparc64 => .SPARCV9,
1103 .ve => .VE,1103 .ve => .VE,
1104 .x86 => .@"386",1104 .x86_16, .x86 => .@"386",
1105 .x86_64 => .X86_64,1105 .x86_64 => .X86_64,
1106 .xcore => .XCORE,1106 .xcore => .XCORE,
1107 .xtensa, .xtensaeb => .XTENSA,1107 .xtensa, .xtensaeb => .XTENSA,
...@@ -1172,6 +1172,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {...@@ -1172,6 +1172,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
1172 .ve,1172 .ve,
1173 .wasm32,1173 .wasm32,
1174 .wasm64,1174 .wasm64,
1175 .x86_16,
1175 .xcore,1176 .xcore,
1176 .xtensa,1177 .xtensa,
1177 .xtensaeb,1178 .xtensaeb,
...@@ -1394,6 +1395,7 @@ pub const Cpu = struct {...@@ -1394,6 +1395,7 @@ pub const Cpu = struct {
1394 ve,1395 ve,
1395 wasm32,1396 wasm32,
1396 wasm64,1397 wasm64,
1398 x86_16,
1397 x86,1399 x86,
1398 x86_64,1400 x86_64,
1399 xcore,1401 xcore,
...@@ -1485,7 +1487,7 @@ pub const Cpu = struct {...@@ -1485,7 +1487,7 @@ pub const Cpu = struct {
1485 .spirv32, .spirv64 => .spirv,1487 .spirv32, .spirv64 => .spirv,
1486 .ve => .ve,1488 .ve => .ve,
1487 .wasm32, .wasm64 => .wasm,1489 .wasm32, .wasm64 => .wasm,
1488 .x86, .x86_64 => .x86,1490 .x86_16, .x86, .x86_64 => .x86,
1489 .xcore => .xcore,1491 .xcore => .xcore,
1490 .xtensa, .xtensaeb => .xtensa,1492 .xtensa, .xtensaeb => .xtensa,
1491 };1493 };
...@@ -1493,7 +1495,7 @@ pub const Cpu = struct {...@@ -1493,7 +1495,7 @@ pub const Cpu = struct {
14931495
1494 pub inline fn isX86(arch: Arch) bool {1496 pub inline fn isX86(arch: Arch) bool {
1495 return switch (arch) {1497 return switch (arch) {
1496 .x86, .x86_64 => true,1498 .x86_16, .x86, .x86_64 => true,
1497 else => false,1499 else => false,
1498 };1500 };
1499 }1501 }
...@@ -1687,6 +1689,7 @@ pub const Cpu = struct {...@@ -1687,6 +1689,7 @@ pub const Cpu = struct {
1687 .ve,1689 .ve,
1688 .wasm32,1690 .wasm32,
1689 .wasm64,1691 .wasm64,
1692 .x86_16,
1690 .x86,1693 .x86,
1691 .x86_64,1694 .x86_64,
1692 .xcore,1695 .xcore,
...@@ -1807,6 +1810,12 @@ pub const Cpu = struct {...@@ -1807,6 +1810,12 @@ pub const Cpu = struct {
1807 .x86_interrupt,1810 .x86_interrupt,
1808 => &.{.x86},1811 => &.{.x86},
18091812
1813 .x86_16_cdecl,
1814 .x86_16_stdcall,
1815 .x86_16_regparmcall,
1816 .x86_16_interrupt,
1817 => &.{.x86_16},
1818
1810 .aarch64_aapcs,1819 .aarch64_aapcs,
1811 .aarch64_aapcs_darwin,1820 .aarch64_aapcs_darwin,
1812 .aarch64_aapcs_win,1821 .aarch64_aapcs_win,
...@@ -1989,6 +1998,7 @@ pub const Cpu = struct {...@@ -1989,6 +1998,7 @@ pub const Cpu = struct {
1989 .riscv64, .riscv64be => &riscv.cpu.generic_rv64,1998 .riscv64, .riscv64be => &riscv.cpu.generic_rv64,
1990 .sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.1999 .sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.
1991 .wasm32, .wasm64 => &wasm.cpu.mvp,2000 .wasm32, .wasm64 => &wasm.cpu.mvp,
2001 .x86_16 => &x86.cpu.i86,
1992 .x86 => &x86.cpu.i386,2002 .x86 => &x86.cpu.i386,
1993 .x86_64 => &x86.cpu.x86_64,2003 .x86_64 => &x86.cpu.x86_64,
1994 inline else => |a| &@field(Target, @tagName(a.family())).cpu.generic,2004 inline else => |a| &@field(Target, @tagName(a.family())).cpu.generic,
...@@ -2260,7 +2270,10 @@ pub fn supportsAddressSpace(...@@ -2260,7 +2270,10 @@ pub fn supportsAddressSpace(
22602270
2261 return switch (address_space) {2271 return switch (address_space) {
2262 .generic => true,2272 .generic => true,
2263 .fs, .gs, .ss => (arch == .x86_64 or arch == .x86) and (context == null or context == .pointer),2273 .fs, .gs, .ss => (arch == .x86_64 or arch == .x86 or arch == .x86_16) and (context == null or context == .pointer),
2274 // Technically x86 can use segmentation...
2275 .far => (arch == .x86_16),
2276
2264 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr, // TODO this should also check how many flash banks the cpu has2277 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr, // TODO this should also check how many flash banks the cpu has
2265 .cog, .hub => arch == .propeller,2278 .cog, .hub => arch == .propeller,
2266 .lut => arch == .propeller and std.Target.propeller.featureSetHas(target.cpu.features, .p2),2279 .lut => arch == .propeller and std.Target.propeller.featureSetHas(target.cpu.features, .p2),
...@@ -2833,6 +2846,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {...@@ -2833,6 +2846,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
2833 return switch (cpu_arch) {2846 return switch (cpu_arch) {
2834 .avr,2847 .avr,
2835 .msp430,2848 .msp430,
2849 .x86_16,
2836 => 16,2850 => 16,
28372851
2838 .arc,2852 .arc,
...@@ -3046,7 +3060,7 @@ pub fn cTypeByteSize(t: *const Target, c_type: CType) u16 {...@@ -3046,7 +3060,7 @@ pub fn cTypeByteSize(t: *const Target, c_type: CType) u16 {
3046pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {3060pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
3047 switch (target.os.tag) {3061 switch (target.os.tag) {
3048 .freestanding, .other => switch (target.cpu.arch) {3062 .freestanding, .other => switch (target.cpu.arch) {
3049 .msp430 => switch (c_type) {3063 .msp430, .x86_16 => switch (c_type) {
3050 .char => return 8,3064 .char => return 8,
3051 .short, .ushort, .int, .uint => return 16,3065 .short, .ushort, .int, .uint => return 16,
3052 .float, .long, .ulong => return 32,3066 .float, .long, .ulong => return 32,
...@@ -3404,6 +3418,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {...@@ -3404,6 +3418,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
3404 std.math.ceilPowerOfTwoAssert(u16, (cTypeBitSize(target, c_type) + 7) / 8),3418 std.math.ceilPowerOfTwoAssert(u16, (cTypeBitSize(target, c_type) + 7) / 8),
3405 @as(u16, switch (target.cpu.arch) {3419 @as(u16, switch (target.cpu.arch) {
3406 .msp430,3420 .msp430,
3421 .x86_16,
3407 => 2,3422 => 2,
34083423
3409 .arc,3424 .arc,
...@@ -3511,7 +3526,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {...@@ -3511,7 +3526,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
3511 return @min(3526 return @min(
3512 std.math.ceilPowerOfTwoAssert(u16, (cTypeBitSize(target, c_type) + 7) / 8),3527 std.math.ceilPowerOfTwoAssert(u16, (cTypeBitSize(target, c_type) + 7) / 8),
3513 @as(u16, switch (target.cpu.arch) {3528 @as(u16, switch (target.cpu.arch) {
3514 .msp430 => 2,3529 .x86_16, .msp430 => 2,
35153530
3516 .arc,3531 .arc,
3517 .arceb,3532 .arceb,
...@@ -3583,7 +3598,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {...@@ -3583,7 +3598,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
3583 return switch (target.cpu.arch) {3598 return switch (target.cpu.arch) {
3584 .avr => 1,3599 .avr => 1,
35853600
3586 .msp430 => 2,3601 .msp430, .x86_16 => 2,
35873602
3588 .arc,3603 .arc,
3589 .arceb,3604 .arceb,
...@@ -3660,6 +3675,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention...@@ -3660,6 +3675,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3660 .windows, .uefi => .{ .x86_win = .{} },3675 .windows, .uefi => .{ .x86_win = .{} },
3661 else => .{ .x86_sysv = .{} },3676 else => .{ .x86_sysv = .{} },
3662 },3677 },
3678 .x86_16 => .{ .x86_16_cdecl = .{} },
3663 .aarch64, .aarch64_be => if (target.os.tag.isDarwin())3679 .aarch64, .aarch64_be => if (target.os.tag.isDarwin())
3664 .{ .aarch64_aapcs_darwin = .{} }3680 .{ .aarch64_aapcs_darwin = .{} }
3665 else switch (target.os.tag) {3681 else switch (target.os.tag) {
lib/std/Target/x86.zig+5
...@@ -3081,6 +3081,11 @@ pub const cpu = struct {...@@ -3081,6 +3081,11 @@ pub const cpu = struct {
3081 .xsaveopt,3081 .xsaveopt,
3082 }),3082 }),
3083 };3083 };
3084 pub const @"i86": CpuModel = .{
3085 .name = "i86",
3086 .llvm_name = null,
3087 .features = featureSet(&[_]Feature{}),
3088 };
3084 pub const @"i386": CpuModel = .{3089 pub const @"i386": CpuModel = .{
3085 .name = "i386",3090 .name = "i386",
3086 .llvm_name = "i386",3091 .llvm_name = "i386",
lib/std/builtin.zig+11
...@@ -223,6 +223,13 @@ pub const CallingConvention = union(enum(u8)) {...@@ -223,6 +223,13 @@ pub const CallingConvention = union(enum(u8)) {
223 x86_vectorcall: CommonOptions,223 x86_vectorcall: CommonOptions,
224 x86_interrupt: CommonOptions,224 x86_interrupt: CommonOptions,
225225
226 // Calling conventions for the `x86_16` architecture.
227
228 x86_16_cdecl: CommonOptions,
229 x86_16_stdcall: CommonOptions,
230 x86_16_regparmcall: CommonOptions,
231 x86_16_interrupt: CommonOptions,
232
226 // Calling conventions for the `aarch64` and `aarch64_be` architectures.233 // Calling conventions for the `aarch64` and `aarch64_be` architectures.
227 aarch64_aapcs: CommonOptions,234 aarch64_aapcs: CommonOptions,
228 aarch64_aapcs_darwin: CommonOptions,235 aarch64_aapcs_darwin: CommonOptions,
...@@ -523,6 +530,10 @@ pub const AddressSpace = enum(u5) {...@@ -523,6 +530,10 @@ pub const AddressSpace = enum(u5) {
523 fs,530 fs,
524 ss,531 ss,
525532
533 // x86_16 extra address spaces.
534 /// Allows addressing the entire address space by storing both segment and offset.
535 far,
536
526 // GPU address spaces.537 // GPU address spaces.
527 global,538 global,
528 constant,539 constant,
lib/std/builtin/assembly.zig+1-1
...@@ -1,5 +1,5 @@...@@ -1,5 +1,5 @@
1pub const Clobbers = switch (@import("builtin").cpu.arch) {1pub const Clobbers = switch (@import("builtin").cpu.arch) {
2 .x86, .x86_64 => packed struct {2 .x86_16, .x86, .x86_64 => packed struct {
3 /// Whether the inline assembly code may perform stores to memory3 /// Whether the inline assembly code may perform stores to memory
4 /// addresses other than those derived from input pointer provenance.4 /// addresses other than those derived from input pointer provenance.
5 memory: bool = false,5 memory: bool = false,
lib/std/zig/system.zig+5
...@@ -386,6 +386,11 @@ pub fn resolveTargetQuery(query: Target.Query) DetectError!Target {...@@ -386,6 +386,11 @@ pub fn resolveTargetQuery(query: Target.Query) DetectError!Target {
386 // However, the "mode" flags can be used as overrides, so if the user explicitly386 // However, the "mode" flags can be used as overrides, so if the user explicitly
387 // sets one of them, that takes precedence.387 // sets one of them, that takes precedence.
388 switch (query_cpu_arch) {388 switch (query_cpu_arch) {
389 .x86_16 => {
390 cpu.features.addFeature(
391 @intFromEnum(Target.x86.Feature.@"16bit_mode"),
392 );
393 },
389 .x86 => {394 .x86 => {
390 if (!Target.x86.featureSetHasAny(query.cpu_features_add, .{395 if (!Target.x86.featureSetHasAny(query.cpu_features_add, .{
391 .@"16bit_mode", .@"32bit_mode",396 .@"16bit_mode", .@"32bit_mode",
src/Sema.zig+1
...@@ -9034,6 +9034,7 @@ pub fn handleExternLibName(...@@ -9034,6 +9034,7 @@ pub fn handleExternLibName(
9034/// Any calling conventions not included here are either not yet verified to work with variadic9034/// Any calling conventions not included here are either not yet verified to work with variadic
9035/// functions or there are no more other calling conventions that support variadic functions.9035/// functions or there are no more other calling conventions that support variadic functions.
9036const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention.Tag{9036const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention.Tag{
9037 .x86_16_cdecl,
9037 .x86_64_sysv,9038 .x86_64_sysv,
9038 .x86_64_x32,9039 .x86_64_x32,
9039 .x86_64_win,9040 .x86_64_win,
src/Zcu.zig+4
...@@ -4406,6 +4406,10 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu...@@ -4406,6 +4406,10 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu
4406 }4406 }
4407 }4407 }
4408 break :ok switch (cc) {4408 break :ok switch (cc) {
4409 .x86_16_cdecl,
4410 .x86_16_stdcall,
4411 .x86_16_regparmcall,
4412 .x86_16_interrupt,
4409 .x86_64_sysv,4413 .x86_64_sysv,
4410 .x86_64_win,4414 .x86_64_win,
4411 .x86_64_vectorcall,4415 .x86_64_vectorcall,
src/codegen/c.zig+4-1
...@@ -8055,9 +8055,11 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8...@@ -8055,9 +8055,11 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
8055 return switch (cc) {8055 return switch (cc) {
8056 .auto, .naked => null,8056 .auto, .naked => null,
80578057
8058 .x86_16_cdecl => "cdecl",
8059 .x86_16_regparmcall => "regparmcall",
8058 .x86_64_sysv, .x86_sysv => "sysv_abi",8060 .x86_64_sysv, .x86_sysv => "sysv_abi",
8059 .x86_64_win, .x86_win => "ms_abi",8061 .x86_64_win, .x86_win => "ms_abi",
8060 .x86_stdcall => "stdcall",8062 .x86_16_stdcall, .x86_stdcall => "stdcall",
8061 .x86_fastcall => "fastcall",8063 .x86_fastcall => "fastcall",
8062 .x86_thiscall => "thiscall",8064 .x86_thiscall => "thiscall",
80638065
...@@ -8127,6 +8129,7 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8...@@ -8127,6 +8129,7 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
8127 .csky_interrupt,8129 .csky_interrupt,
8128 .m68k_interrupt,8130 .m68k_interrupt,
8129 .msp430_interrupt,8131 .msp430_interrupt,
8132 .x86_16_interrupt,
8130 .x86_interrupt,8133 .x86_interrupt,
8131 .x86_64_interrupt,8134 .x86_64_interrupt,
8132 => "interrupt",8135 => "interrupt",
src/codegen/llvm.zig+7
...@@ -117,6 +117,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8...@@ -117,6 +117,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
117 .propeller,117 .propeller,
118 .sh,118 .sh,
119 .sheb,119 .sheb,
120 .x86_16,
120 .xtensaeb,121 .xtensaeb,
121 => unreachable, // Gated by hasLlvmSupport().122 => unreachable, // Gated by hasLlvmSupport().
122 };123 };
...@@ -493,6 +494,7 @@ pub fn dataLayout(target: *const std.Target) []const u8 {...@@ -493,6 +494,7 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
493 .propeller,494 .propeller,
494 .sh,495 .sh,
495 .sheb,496 .sheb,
497 .x86_16,
496 .xtensaeb,498 .xtensaeb,
497 => unreachable, // Gated by hasLlvmSupport().499 => unreachable, // Gated by hasLlvmSupport().
498 };500 };
...@@ -11919,6 +11921,10 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s...@@ -11919,6 +11921,10 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
1191911921
11920 // All the calling conventions which LLVM does not have a general representation for.11922 // All the calling conventions which LLVM does not have a general representation for.
11921 // Note that these are often still supported through the `cCallingConvention` path above via `ccc`.11923 // Note that these are often still supported through the `cCallingConvention` path above via `ccc`.
11924 .x86_16_cdecl,
11925 .x86_16_stdcall,
11926 .x86_16_regparmcall,
11927 .x86_16_interrupt,
11922 .x86_sysv,11928 .x86_sysv,
11923 .x86_win,11929 .x86_win,
11924 .x86_thiscall_mingw,11930 .x86_thiscall_mingw,
...@@ -13148,6 +13154,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {...@@ -13148,6 +13154,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
13148 .propeller,13154 .propeller,
13149 .sh,13155 .sh,
13150 .sheb,13156 .sheb,
13157 .x86_16,
13151 .xtensaeb,13158 .xtensaeb,
13152 => unreachable,13159 => unreachable,
13153 }13160 }
src/codegen/spirv/Module.zig+1
...@@ -927,6 +927,7 @@ pub fn storageClass(module: *Module, as: std.builtin.AddressSpace) spec.StorageC...@@ -927,6 +927,7 @@ pub fn storageClass(module: *Module, as: std.builtin.AddressSpace) spec.StorageC
927 .gs,927 .gs,
928 .fs,928 .fs,
929 .ss,929 .ss,
930 .far,
930 .param,931 .param,
931 .flash,932 .flash,
932 .flash1,933 .flash1,
src/target.zig+1
...@@ -227,6 +227,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)...@@ -227,6 +227,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
227 .propeller,227 .propeller,
228 .sh,228 .sh,
229 .sheb,229 .sheb,
230 .x86_16,
230 .xtensaeb,231 .xtensaeb,
231 => false,232 => false,
232 };233 };