authorgravatar for me@gasinfinity.devGasInfinity <me@gasinfinity.dev> 2025-10-27 11:19:51+01:00
committergravatar for me@gasinfinity.devGasInfinity <me@gasinfinity.dev> 2025-10-27 11:19:51+01:00
log104c272ae5dc0ab2fc6f81da5918f1b8abf7e131
treedf07283bc81040a74df18bc4149123bd1fa85d51
parent9d3bd3c502c4a2413c1c83a581b0711eceb37838
signaturebadge-check Signed by SSH key SHA256:p3IHbr0lyK2ekfDC1Zi7dOEV/9T6lGghNawhl5sBnM4

feat: init x86_16 arch via CBE

11 files changed, 63 insertions(+), 9 deletions(-)

lib/std/Target.zig+23-7
......@@ -1101,7 +1101,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
11011101 .sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC,
11021102 .sparc64 => .SPARCV9,
11031103 .ve => .VE,
1104 .x86 => .@"386",
1104 .x86_16, .x86 => .@"386",
11051105 .x86_64 => .X86_64,
11061106 .xcore => .XCORE,
11071107 .xtensa, .xtensaeb => .XTENSA,
......@@ -1172,6 +1172,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
11721172 .ve,
11731173 .wasm32,
11741174 .wasm64,
1175 .x86_16,
11751176 .xcore,
11761177 .xtensa,
11771178 .xtensaeb,
......@@ -1394,6 +1395,7 @@ pub const Cpu = struct {
13941395 ve,
13951396 wasm32,
13961397 wasm64,
1398 x86_16,
13971399 x86,
13981400 x86_64,
13991401 xcore,
......@@ -1485,7 +1487,7 @@ pub const Cpu = struct {
14851487 .spirv32, .spirv64 => .spirv,
14861488 .ve => .ve,
14871489 .wasm32, .wasm64 => .wasm,
1488 .x86, .x86_64 => .x86,
1490 .x86_16, .x86, .x86_64 => .x86,
14891491 .xcore => .xcore,
14901492 .xtensa, .xtensaeb => .xtensa,
14911493 };
......@@ -1493,7 +1495,7 @@ pub const Cpu = struct {
14931495
14941496 pub inline fn isX86(arch: Arch) bool {
14951497 return switch (arch) {
1496 .x86, .x86_64 => true,
1498 .x86_16, .x86, .x86_64 => true,
14971499 else => false,
14981500 };
14991501 }
......@@ -1687,6 +1689,7 @@ pub const Cpu = struct {
16871689 .ve,
16881690 .wasm32,
16891691 .wasm64,
1692 .x86_16,
16901693 .x86,
16911694 .x86_64,
16921695 .xcore,
......@@ -1807,6 +1810,12 @@ pub const Cpu = struct {
18071810 .x86_interrupt,
18081811 => &.{.x86},
18091812
1813 .x86_16_cdecl,
1814 .x86_16_stdcall,
1815 .x86_16_regparmcall,
1816 .x86_16_interrupt,
1817 => &.{.x86_16},
1818
18101819 .aarch64_aapcs,
18111820 .aarch64_aapcs_darwin,
18121821 .aarch64_aapcs_win,
......@@ -1989,6 +1998,7 @@ pub const Cpu = struct {
19891998 .riscv64, .riscv64be => &riscv.cpu.generic_rv64,
19901999 .sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.
19912000 .wasm32, .wasm64 => &wasm.cpu.mvp,
2001 .x86_16 => &x86.cpu.i86,
19922002 .x86 => &x86.cpu.i386,
19932003 .x86_64 => &x86.cpu.x86_64,
19942004 inline else => |a| &@field(Target, @tagName(a.family())).cpu.generic,
......@@ -2260,7 +2270,10 @@ pub fn supportsAddressSpace(
22602270
22612271 return switch (address_space) {
22622272 .generic => true,
2263 .fs, .gs, .ss => (arch == .x86_64 or arch == .x86) and (context == null or context == .pointer),
2273 .fs, .gs, .ss => (arch == .x86_64 or arch == .x86 or arch == .x86_16) and (context == null or context == .pointer),
2274 // Technically x86 can use segmentation...
2275 .far => (arch == .x86_16),
2276
22642277 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr, // TODO this should also check how many flash banks the cpu has
22652278 .cog, .hub => arch == .propeller,
22662279 .lut => arch == .propeller and std.Target.propeller.featureSetHas(target.cpu.features, .p2),
......@@ -2833,6 +2846,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
28332846 return switch (cpu_arch) {
28342847 .avr,
28352848 .msp430,
2849 .x86_16,
28362850 => 16,
28372851
28382852 .arc,
......@@ -3046,7 +3060,7 @@ pub fn cTypeByteSize(t: *const Target, c_type: CType) u16 {
30463060pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
30473061 switch (target.os.tag) {
30483062 .freestanding, .other => switch (target.cpu.arch) {
3049 .msp430 => switch (c_type) {
3063 .msp430, .x86_16 => switch (c_type) {
30503064 .char => return 8,
30513065 .short, .ushort, .int, .uint => return 16,
30523066 .float, .long, .ulong => return 32,
......@@ -3404,6 +3418,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
34043418 std.math.ceilPowerOfTwoAssert(u16, (cTypeBitSize(target, c_type) + 7) / 8),
34053419 @as(u16, switch (target.cpu.arch) {
34063420 .msp430,
3421 .x86_16,
34073422 => 2,
34083423
34093424 .arc,
......@@ -3511,7 +3526,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
35113526 return @min(
35123527 std.math.ceilPowerOfTwoAssert(u16, (cTypeBitSize(target, c_type) + 7) / 8),
35133528 @as(u16, switch (target.cpu.arch) {
3514 .msp430 => 2,
3529 .x86_16, .msp430 => 2,
35153530
35163531 .arc,
35173532 .arceb,
......@@ -3583,7 +3598,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
35833598 return switch (target.cpu.arch) {
35843599 .avr => 1,
35853600
3586 .msp430 => 2,
3601 .msp430, .x86_16 => 2,
35873602
35883603 .arc,
35893604 .arceb,
......@@ -3660,6 +3675,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
36603675 .windows, .uefi => .{ .x86_win = .{} },
36613676 else => .{ .x86_sysv = .{} },
36623677 },
3678 .x86_16 => .{ .x86_16_cdecl = .{} },
36633679 .aarch64, .aarch64_be => if (target.os.tag.isDarwin())
36643680 .{ .aarch64_aapcs_darwin = .{} }
36653681 else switch (target.os.tag) {
lib/std/Target/x86.zig+5
......@@ -3081,6 +3081,11 @@ pub const cpu = struct {
30813081 .xsaveopt,
30823082 }),
30833083 };
3084 pub const @"i86": CpuModel = .{
3085 .name = "i86",
3086 .llvm_name = null,
3087 .features = featureSet(&[_]Feature{}),
3088 };
30843089 pub const @"i386": CpuModel = .{
30853090 .name = "i386",
30863091 .llvm_name = "i386",
lib/std/builtin.zig+11
......@@ -223,6 +223,13 @@ pub const CallingConvention = union(enum(u8)) {
223223 x86_vectorcall: CommonOptions,
224224 x86_interrupt: CommonOptions,
225225
226 // Calling conventions for the `x86_16` architecture.
227
228 x86_16_cdecl: CommonOptions,
229 x86_16_stdcall: CommonOptions,
230 x86_16_regparmcall: CommonOptions,
231 x86_16_interrupt: CommonOptions,
232
226233 // Calling conventions for the `aarch64` and `aarch64_be` architectures.
227234 aarch64_aapcs: CommonOptions,
228235 aarch64_aapcs_darwin: CommonOptions,
......@@ -523,6 +530,10 @@ pub const AddressSpace = enum(u5) {
523530 fs,
524531 ss,
525532
533 // x86_16 extra address spaces.
534 /// Allows addressing the entire address space by storing both segment and offset.
535 far,
536
526537 // GPU address spaces.
527538 global,
528539 constant,
lib/std/builtin/assembly.zig+1-1
......@@ -1,5 +1,5 @@
11pub const Clobbers = switch (@import("builtin").cpu.arch) {
2 .x86, .x86_64 => packed struct {
2 .x86_16, .x86, .x86_64 => packed struct {
33 /// Whether the inline assembly code may perform stores to memory
44 /// addresses other than those derived from input pointer provenance.
55 memory: bool = false,
lib/std/zig/system.zig+5
......@@ -386,6 +386,11 @@ pub fn resolveTargetQuery(query: Target.Query) DetectError!Target {
386386 // However, the "mode" flags can be used as overrides, so if the user explicitly
387387 // sets one of them, that takes precedence.
388388 switch (query_cpu_arch) {
389 .x86_16 => {
390 cpu.features.addFeature(
391 @intFromEnum(Target.x86.Feature.@"16bit_mode"),
392 );
393 },
389394 .x86 => {
390395 if (!Target.x86.featureSetHasAny(query.cpu_features_add, .{
391396 .@"16bit_mode", .@"32bit_mode",
src/Sema.zig+1
......@@ -9034,6 +9034,7 @@ pub fn handleExternLibName(
90349034/// Any calling conventions not included here are either not yet verified to work with variadic
90359035/// functions or there are no more other calling conventions that support variadic functions.
90369036const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention.Tag{
9037 .x86_16_cdecl,
90379038 .x86_64_sysv,
90389039 .x86_64_x32,
90399040 .x86_64_win,
src/Zcu.zig+4
......@@ -4406,6 +4406,10 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu
44064406 }
44074407 }
44084408 break :ok switch (cc) {
4409 .x86_16_cdecl,
4410 .x86_16_stdcall,
4411 .x86_16_regparmcall,
4412 .x86_16_interrupt,
44094413 .x86_64_sysv,
44104414 .x86_64_win,
44114415 .x86_64_vectorcall,
src/codegen/c.zig+4-1
......@@ -8055,9 +8055,11 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
80558055 return switch (cc) {
80568056 .auto, .naked => null,
80578057
8058 .x86_16_cdecl => "cdecl",
8059 .x86_16_regparmcall => "regparmcall",
80588060 .x86_64_sysv, .x86_sysv => "sysv_abi",
80598061 .x86_64_win, .x86_win => "ms_abi",
8060 .x86_stdcall => "stdcall",
8062 .x86_16_stdcall, .x86_stdcall => "stdcall",
80618063 .x86_fastcall => "fastcall",
80628064 .x86_thiscall => "thiscall",
80638065
......@@ -8127,6 +8129,7 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
81278129 .csky_interrupt,
81288130 .m68k_interrupt,
81298131 .msp430_interrupt,
8132 .x86_16_interrupt,
81308133 .x86_interrupt,
81318134 .x86_64_interrupt,
81328135 => "interrupt",
src/codegen/llvm.zig+7
......@@ -117,6 +117,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
117117 .propeller,
118118 .sh,
119119 .sheb,
120 .x86_16,
120121 .xtensaeb,
121122 => unreachable, // Gated by hasLlvmSupport().
122123 };
......@@ -493,6 +494,7 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
493494 .propeller,
494495 .sh,
495496 .sheb,
497 .x86_16,
496498 .xtensaeb,
497499 => unreachable, // Gated by hasLlvmSupport().
498500 };
......@@ -11919,6 +11921,10 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
1191911921
1192011922 // All the calling conventions which LLVM does not have a general representation for.
1192111923 // Note that these are often still supported through the `cCallingConvention` path above via `ccc`.
11924 .x86_16_cdecl,
11925 .x86_16_stdcall,
11926 .x86_16_regparmcall,
11927 .x86_16_interrupt,
1192211928 .x86_sysv,
1192311929 .x86_win,
1192411930 .x86_thiscall_mingw,
......@@ -13148,6 +13154,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1314813154 .propeller,
1314913155 .sh,
1315013156 .sheb,
13157 .x86_16,
1315113158 .xtensaeb,
1315213159 => unreachable,
1315313160 }
src/codegen/spirv/Module.zig+1
......@@ -927,6 +927,7 @@ pub fn storageClass(module: *Module, as: std.builtin.AddressSpace) spec.StorageC
927927 .gs,
928928 .fs,
929929 .ss,
930 .far,
930931 .param,
931932 .flash,
932933 .flash1,
src/target.zig+1
......@@ -227,6 +227,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
227227 .propeller,
228228 .sh,
229229 .sheb,
230 .x86_16,
230231 .xtensaeb,
231232 => false,
232233 };