Commit 1f50810733e087faf884c5641617369c1c8e258f | zig

author	Joachim Schmidt <joachim.schmidt557@outlook.com> 2022-09-20 21:51:02+02:00
committer	GitHub <noreply@github.com> 2022-09-20 21:51:02+02:00
log	1f50810733e087faf884c5641617369c1c8e258f
tree	f70b1453ad6e2748374cbad4695601763e844679
parent	4521456f66122c6348ef6980ae1eecdb94f4f110
parent	f014de6456f0cd56d692c2a93c441d83b01796a2
signature	Signed by PGP key 4AEE18F83AFDEB23

Merge pull request #12912 from joachimschmidt557/stage2-arm

stage2 ARM: minor fixes

3 files changed, 39 insertions(+), 72 deletions(-)

src
- arch
  - arm
    CodeGen.zig
    Emit.zig
    Mir.zig

src/arch/arm/CodeGen.zig+33-66

 @@ -169,40 +169,6 @@ const MCValue = union(enum) {
     cpsr_flags: Condition,
     /// The value is a function argument passed via the stack.
     stack_argument_offset: u32,
-    fn isMemory(mcv: MCValue) bool {
-        return switch (mcv) {
-            .memory, .stack_offset, .stack_argument_offset => true,
-            else => false,
-        };
-    }
-    fn isImmediate(mcv: MCValue) bool {
-        return switch (mcv) {
-            .immediate => true,
-            else => false,
-        };
-    }
-    fn isMutable(mcv: MCValue) bool {
-        return switch (mcv) {
-            .none => unreachable,
-            .unreach => unreachable,
-            .dead => unreachable,
-            .immediate,
-            .memory,
-            .cpsr_flags,
-            .ptr_stack_offset,
-            .undef,
-            .stack_argument_offset,
-            => false,
-            .register,
-            .stack_offset,
-            => true,
-        };
-    }
 };
 const Branch = struct {
 @@ -447,6 +413,11 @@ fn gen(self: *Self) !void {
         // sub sp, sp, #reloc
         const sub_reloc = try self.addNop();
+        // The sub_sp_scratch_r4 instruction may use r4, so we mark r4
+        // as allocated by this function.
+        const index = RegisterManager.indexOfRegIntoTracked(.r4).?;
+        self.register_manager.allocated_registers.set(index);
         if (self.ret_mcv == .stack_offset) {
             // The address of where to store the return value is in
             // r0. As this register might get overwritten along the
 @@ -457,6 +428,28 @@ fn gen(self: *Self) !void {
             self.ret_mcv = MCValue{ .stack_offset = stack_offset };
         }
+        for (self.args) |*arg, arg_index| {
+            // Copy register arguments to the stack
+            switch (arg.*) {
+                .register => |reg| {
+                    // The first AIR instructions of the main body are guaranteed
+                    // to be the functions arguments
+                    const inst = self.air.getMainBody()[arg_index];
+                    assert(self.air.instructions.items(.tag)[inst] == .arg);
+                    const ty = self.air.typeOfIndex(inst);
+                    const abi_size = @intCast(u32, ty.abiSize(self.target.*));
+                    const abi_align = ty.abiAlignment(self.target.*);
+                    const stack_offset = try self.allocMem(abi_size, abi_align, inst);
+                    try self.genSetStack(ty, stack_offset, MCValue{ .register = reg });
+                    arg.* = MCValue{ .stack_offset = stack_offset };
+                },
+                else => {},
+            }
+        }
         _ = try self.addInst(.{
             .tag = .dbg_prologue_end,
             .cond = undefined,
 @@ -477,7 +470,6 @@ fn gen(self: *Self) !void {
                 self.saved_regs_stack_space += 4;
             }
         }
         self.mir_instructions.set(push_reloc, .{
             .tag = .push,
             .data = .{ .register_list = saved_regs },
 @@ -489,7 +481,7 @@ fn gen(self: *Self) !void {
         const stack_size = aligned_total_stack_end - self.saved_regs_stack_space;
         self.max_end_stack = stack_size;
         self.mir_instructions.set(sub_reloc, .{
-            .tag = .sub_sp_scratch_r0,
+            .tag = .sub_sp_scratch_r4,
             .data = .{ .imm32 = stack_size },
         });
 @@ -3796,7 +3788,8 @@ fn genStrRegister(self: *Self, source_reg: Register, addr_reg: Register, ty: Typ
     const tag: Mir.Inst.Tag = switch (abi_size) {
         1 => .strb,
         2 => .strh,
-        3, 4 => .str,
+        4 => .str,
+        3 => return self.fail("TODO: genStrRegister for abi_size={}", .{abi_size}),
         else => unreachable,
     };
 @@ -3812,7 +3805,7 @@ fn genStrRegister(self: *Self, source_reg: Register, addr_reg: Register, ty: Typ
     } };
     const data: Mir.Inst.Data = switch (abi_size) {
-        1, 3, 4 => rr_offset,
+        1, 4 => rr_offset,
         2 => rr_extra_offset,
         else => unreachable,
     };
 @@ -4042,7 +4035,6 @@ fn genArgDbgInfo(self: *Self, inst: Air.Inst.Index, arg_index: u32) error{OutOfM
         => {
             switch (self.debug_output) {
                 .dwarf => |dw| {
-                    // const abi_size = @intCast(u32, ty.abiSize(self.target.*));
                     const adjusted_stack_offset = switch (mcv) {
                         .stack_offset => |offset| -@intCast(i32, offset),
                         .stack_argument_offset => |offset| @intCast(i32, self.saved_regs_stack_space + offset),
 @@ -4078,38 +4070,13 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {
     const arg_index = self.arg_index;
     self.arg_index += 1;
-    const ty = self.air.typeOfIndex(inst);
-    const result = self.args[arg_index];
-    const mcv = switch (result) {
-        // Copy registers to the stack
-        .register => |reg| blk: {
-            const abi_size = @intCast(u32, ty.abiSize(self.target.*));
-            const abi_align = ty.abiAlignment(self.target.*);
-            const stack_offset = try self.allocMem(abi_size, abi_align, inst);
-            try self.genSetStack(ty, stack_offset, MCValue{ .register = reg });
-            break :blk MCValue{ .stack_offset = stack_offset };
-        },
-        else => result,
-    };
     try self.dbg_arg_relocs.append(self.gpa, .{
         .inst = inst,
         .index = arg_index,
     });
-    if (self.liveness.isUnused(inst))
+    const result: MCValue = if (self.liveness.isUnused(inst)) .dead else self.args[arg_index];
-        return self.finishAirBookkeeping();
+    return self.finishAir(inst, result, .{ .none, .none, .none });
-    switch (mcv) {
-        .register => |reg| {
-            self.register_manager.getRegAssumeFree(reg, inst);
-        },
-        else => {},
-    }
-    return self.finishAir(inst, mcv, .{ .none, .none, .none });
 }
 fn airBreakpoint(self: *Self) !void {

src/arch/arm/Emit.zig+4-4

...	@@ -94,7 +94,7 @@ pub fn emitMir(	...	@@ -94,7 +94,7 @@ pub fn emitMir(
94	.sub => try emit.mirDataProcessing(inst),	94	.sub => try emit.mirDataProcessing(inst),
95	.subs => try emit.mirDataProcessing(inst),	95	.subs => try emit.mirDataProcessing(inst),
96		96
97	.sub_sp_scratch_r0 => try emit.mirSubStackPointer(inst),	97	.sub_sp_scratch_r4 => try emit.mirSubStackPointer(inst),
98		98
99	.asr => try emit.mirShift(inst),	99	.asr => try emit.mirShift(inst),
100	.lsl => try emit.mirShift(inst),	100	.lsl => try emit.mirShift(inst),
...	@@ -194,7 +194,7 @@ fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {	...	@@ -194,7 +194,7 @@ fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {
194	.dbg_prologue_end,	194	.dbg_prologue_end,
195	=> return 0,	195	=> return 0,
196		196
197	.sub_sp_scratch_r0 => {	197	.sub_sp_scratch_r4 => {
198	const imm32 = emit.mir.instructions.items(.data)[inst].imm32;	198	const imm32 = emit.mir.instructions.items(.data)[inst].imm32;
199		199
200	if (imm32 == 0) {	200	if (imm32 == 0) {
...	@@ -454,11 +454,11 @@ fn mirSubStackPointer(emit: *Emit, inst: Mir.Inst.Index) !void {	...	@@ -454,11 +454,11 @@ fn mirSubStackPointer(emit: *Emit, inst: Mir.Inst.Index) !void {
454	const imm32 = emit.mir.instructions.items(.data)[inst].imm32;	454	const imm32 = emit.mir.instructions.items(.data)[inst].imm32;
455		455
456	switch (tag) {	456	switch (tag) {
457	.sub_sp_scratch_r0 => {	457	.sub_sp_scratch_r4 => {
458	if (imm32 == 0) return;	458	if (imm32 == 0) return;
459		459
460	const operand = Instruction.Operand.fromU32(imm32) orelse blk: {	460	const operand = Instruction.Operand.fromU32(imm32) orelse blk: {
461	const scratch: Register = .r0;	461	const scratch: Register = .r4;
462		462
463	if (Target.arm.featureSetHas(emit.target.cpu.features, .has_v7)) {	463	if (Target.arm.featureSetHas(emit.target.cpu.features, .has_v7)) {
464	try emit.writeInstruction(Instruction.movw(cond, scratch, @truncate(u16, imm32)));	464	try emit.writeInstruction(Instruction.movw(cond, scratch, @truncate(u16, imm32)));

src/arch/arm/Mir.zig+2-2

...	@@ -113,9 +113,9 @@ pub const Inst = struct {	...	@@ -113,9 +113,9 @@ pub const Inst = struct {
113	sub,	113	sub,
114	/// Pseudo-instruction: Subtract 32-bit immediate from stack	114	/// Pseudo-instruction: Subtract 32-bit immediate from stack
115	///	115	///
116	/// r0 can be used by Emit as a scratch register for loading	116	/// r4 can be used by Emit as a scratch register for loading
117	/// the immediate	117	/// the immediate
118	sub_sp_scratch_r0,	118	sub_sp_scratch_r4,
119	/// Subtract, update condition flags	119	/// Subtract, update condition flags
120	subs,	120	subs,
121	/// Supervisor Call	121	/// Supervisor Call