authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-01-24 00:50:39+01:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-02-17 19:17:55+01:00
log2fe32ef847dd2f19113b86036357beeddbd08f05
tree911bf7a5f1fdef22457078eaf056cbbe2e66eafd
parent5248f0a9095bac52b5a066c0ea0a317439e6cf2f
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove Cpu.Arch.propeller2 and use a CPU feature instead.

9 files changed, 76 insertions(+), 55 deletions(-)

lib/std/Target.zig+14-35
...@@ -763,6 +763,7 @@ pub const mips = @import("Target/mips.zig");...@@ -763,6 +763,7 @@ pub const mips = @import("Target/mips.zig");
763pub const msp430 = @import("Target/msp430.zig");763pub const msp430 = @import("Target/msp430.zig");
764pub const nvptx = @import("Target/nvptx.zig");764pub const nvptx = @import("Target/nvptx.zig");
765pub const powerpc = @import("Target/powerpc.zig");765pub const powerpc = @import("Target/powerpc.zig");
766pub const propeller = @import("Target/propeller.zig");
766pub const riscv = @import("Target/riscv.zig");767pub const riscv = @import("Target/riscv.zig");
767pub const sparc = @import("Target/sparc.zig");768pub const sparc = @import("Target/sparc.zig");
768pub const spirv = @import("Target/spirv.zig");769pub const spirv = @import("Target/spirv.zig");
...@@ -772,7 +773,6 @@ pub const wasm = @import("Target/wasm.zig");...@@ -772,7 +773,6 @@ pub const wasm = @import("Target/wasm.zig");
772pub const x86 = @import("Target/x86.zig");773pub const x86 = @import("Target/x86.zig");
773pub const xcore = @import("Target/xcore.zig");774pub const xcore = @import("Target/xcore.zig");
774pub const xtensa = @import("Target/xtensa.zig");775pub const xtensa = @import("Target/xtensa.zig");
775pub const propeller = @import("Target/propeller.zig");
776776
777pub const Abi = enum {777pub const Abi = enum {
778 none,778 none,
...@@ -1081,6 +1081,7 @@ pub fn toElfMachine(target: Target) std.elf.EM {...@@ -1081,6 +1081,7 @@ pub fn toElfMachine(target: Target) std.elf.EM {
1081 .msp430 => .MSP430,1081 .msp430 => .MSP430,
1082 .powerpc, .powerpcle => .PPC,1082 .powerpc, .powerpcle => .PPC,
1083 .powerpc64, .powerpc64le => .PPC64,1083 .powerpc64, .powerpc64le => .PPC64,
1084 .propeller => .PROPELLER,
1084 .riscv32, .riscv64 => .RISCV,1085 .riscv32, .riscv64 => .RISCV,
1085 .s390x => .S390,1086 .s390x => .S390,
1086 .sparc => if (Target.sparc.featureSetHas(target.cpu.features, .v9)) .SPARC32PLUS else .SPARC,1087 .sparc => if (Target.sparc.featureSetHas(target.cpu.features, .v9)) .SPARC32PLUS else .SPARC,
...@@ -1091,9 +1092,6 @@ pub fn toElfMachine(target: Target) std.elf.EM {...@@ -1091,9 +1092,6 @@ pub fn toElfMachine(target: Target) std.elf.EM {
1091 .xcore => .XCORE,1092 .xcore => .XCORE,
1092 .xtensa => .XTENSA,1093 .xtensa => .XTENSA,
10931094
1094 .propeller1 => .PROPELLER,
1095 .propeller2 => .PROPELLER2,
1096
1097 .nvptx,1095 .nvptx,
1098 .nvptx64,1096 .nvptx64,
1099 .spirv,1097 .spirv,
...@@ -1152,8 +1150,7 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {...@@ -1152,8 +1150,7 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {
1152 .wasm64,1150 .wasm64,
1153 .xcore,1151 .xcore,
1154 .xtensa,1152 .xtensa,
1155 .propeller1,1153 .propeller,
1156 .propeller2,
1157 => .UNKNOWN,1154 => .UNKNOWN,
1158 };1155 };
1159}1156}
...@@ -1366,8 +1363,7 @@ pub const Cpu = struct {...@@ -1366,8 +1363,7 @@ pub const Cpu = struct {
1366 powerpcle,1363 powerpcle,
1367 powerpc64,1364 powerpc64,
1368 powerpc64le,1365 powerpc64le,
1369 propeller1,1366 propeller,
1370 propeller2,
1371 riscv32,1367 riscv32,
1372 riscv64,1368 riscv64,
1373 s390x,1369 s390x,
...@@ -1517,14 +1513,6 @@ pub const Cpu = struct {...@@ -1517,14 +1513,6 @@ pub const Cpu = struct {
1517 };1513 };
1518 }1514 }
15191515
1520 /// Returns if the architecture is a Parallax propeller architecture.
1521 pub inline fn isPropeller(arch: Arch) bool {
1522 return switch (arch) {
1523 .propeller1, .propeller2 => true,
1524 else => false,
1525 };
1526 }
1527
1528 pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) !*const Cpu.Model {1516 pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) !*const Cpu.Model {
1529 for (arch.allCpuModels()) |cpu| {1517 for (arch.allCpuModels()) |cpu| {
1530 if (std.mem.eql(u8, cpu_name, cpu.name)) {1518 if (std.mem.eql(u8, cpu_name, cpu.name)) {
...@@ -1568,8 +1556,7 @@ pub const Cpu = struct {...@@ -1568,8 +1556,7 @@ pub const Cpu = struct {
1568 .loongarch32,1556 .loongarch32,
1569 .loongarch64,1557 .loongarch64,
1570 .arc,1558 .arc,
1571 .propeller1,1559 .propeller,
1572 .propeller2,
1573 => .little,1560 => .little,
15741561
1575 .armeb,1562 .armeb,
...@@ -1604,8 +1591,8 @@ pub const Cpu = struct {...@@ -1604,8 +1591,8 @@ pub const Cpu = struct {
1604 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,1591 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,
16051592
1606 // Propeller address spaces:1593 // Propeller address spaces:
1607 .cog, .hub => arch.isPropeller(),1594 .cog, .hub => arch == .propeller,
1608 .lut => (arch == .propeller2),1595 .lut => arch == .propeller, // TODO: This should check for the `p2` CPU feature.
1609 };1596 };
1610 }1597 }
16111598
...@@ -1618,6 +1605,7 @@ pub const Cpu = struct {...@@ -1618,6 +1605,7 @@ pub const Cpu = struct {
1618 .loongarch32, .loongarch64 => "loongarch",1605 .loongarch32, .loongarch64 => "loongarch",
1619 .mips, .mipsel, .mips64, .mips64el => "mips",1606 .mips, .mipsel, .mips64, .mips64el => "mips",
1620 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",1607 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
1608 .propeller => "propeller",
1621 .riscv32, .riscv64 => "riscv",1609 .riscv32, .riscv64 => "riscv",
1622 .sparc, .sparc64 => "sparc",1610 .sparc, .sparc64 => "sparc",
1623 .s390x => "s390x",1611 .s390x => "s390x",
...@@ -1625,7 +1613,6 @@ pub const Cpu = struct {...@@ -1625,7 +1613,6 @@ pub const Cpu = struct {
1625 .nvptx, .nvptx64 => "nvptx",1613 .nvptx, .nvptx64 => "nvptx",
1626 .wasm32, .wasm64 => "wasm",1614 .wasm32, .wasm64 => "wasm",
1627 .spirv, .spirv32, .spirv64 => "spirv",1615 .spirv, .spirv32, .spirv64 => "spirv",
1628 .propeller1, .propeller2 => "propeller",
1629 else => @tagName(arch),1616 else => @tagName(arch),
1630 };1617 };
1631 }1618 }
...@@ -1851,10 +1838,7 @@ pub const Cpu = struct {...@@ -1851,10 +1838,7 @@ pub const Cpu = struct {
1851 => &.{.msp430},1838 => &.{.msp430},
18521839
1853 .propeller1_sysv,1840 .propeller1_sysv,
1854 => &.{.propeller1},1841 => &.{.propeller},
1855
1856 .propeller2_sysv,
1857 => &.{.propeller2},
18581842
1859 .s390x_sysv,1843 .s390x_sysv,
1860 .s390x_sysv_vx,1844 .s390x_sysv_vx,
...@@ -1933,8 +1917,7 @@ pub const Cpu = struct {...@@ -1933,8 +1917,7 @@ pub const Cpu = struct {
1933 .msp430 => &msp430.cpu.generic,1917 .msp430 => &msp430.cpu.generic,
1934 .powerpc, .powerpcle => &powerpc.cpu.ppc,1918 .powerpc, .powerpcle => &powerpc.cpu.ppc,
1935 .powerpc64, .powerpc64le => &powerpc.cpu.ppc64,1919 .powerpc64, .powerpc64le => &powerpc.cpu.ppc64,
1936 .propeller1 => &propeller.cpu.generic,1920 .propeller => &propeller.cpu.p1,
1937 .propeller2 => &propeller.cpu.generic,
1938 .riscv32 => &riscv.cpu.generic_rv32,1921 .riscv32 => &riscv.cpu.generic_rv32,
1939 .riscv64 => &riscv.cpu.generic_rv64,1922 .riscv64 => &riscv.cpu.generic_rv64,
1940 .spirv, .spirv32, .spirv64 => &spirv.cpu.generic,1923 .spirv, .spirv32, .spirv64 => &spirv.cpu.generic,
...@@ -2647,8 +2630,7 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {...@@ -2647,8 +2630,7 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
2647 .spirv32,2630 .spirv32,
2648 .loongarch32,2631 .loongarch32,
2649 .xtensa,2632 .xtensa,
2650 .propeller1,2633 .propeller,
2651 .propeller2,
2652 => 32,2634 => 32,
26532635
2654 .aarch64,2636 .aarch64,
...@@ -3159,8 +3141,7 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {...@@ -3159,8 +3141,7 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {
3159 .xcore,3141 .xcore,
3160 .kalimba,3142 .kalimba,
3161 .xtensa,3143 .xtensa,
3162 .propeller1,3144 .propeller,
3163 .propeller2,
3164 => 4,3145 => 4,
31653146
3166 .arm,3147 .arm,
...@@ -3254,8 +3235,7 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {...@@ -3254,8 +3235,7 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {
3254 .xcore,3235 .xcore,
3255 .kalimba,3236 .kalimba,
3256 .xtensa,3237 .xtensa,
3257 .propeller1,3238 .propeller,
3258 .propeller2,
3259 => 4,3239 => 4,
32603240
3261 .arc,3241 .arc,
...@@ -3360,8 +3340,7 @@ pub fn cCallingConvention(target: Target) ?std.builtin.CallingConvention {...@@ -3360,8 +3340,7 @@ pub fn cCallingConvention(target: Target) ?std.builtin.CallingConvention {
3360 else3340 else
3361 .{ .m68k_sysv = .{} },3341 .{ .m68k_sysv = .{} },
3362 .msp430 => .{ .msp430_eabi = .{} },3342 .msp430 => .{ .msp430_eabi = .{} },
3363 .propeller1 => .{ .propeller1_sysv = .{} },3343 .propeller => .{ .propeller1_sysv = .{} },
3364 .propeller2 => .{ .propeller2_sysv = .{} },
3365 .s390x => .{ .s390x_sysv = .{} },3344 .s390x => .{ .s390x_sysv = .{} },
3366 .ve => .{ .ve_sysv = .{} },3345 .ve => .{ .ve_sysv = .{} },
3367 .xcore => .{ .xcore_xs1 = .{} },3346 .xcore => .{ .xcore_xs1 = .{} },
lib/std/Target/propeller.zig+30-4
...@@ -1,20 +1,46 @@...@@ -1,20 +1,46 @@
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
1const std = @import("../std.zig");3const std = @import("../std.zig");
2const CpuFeature = std.Target.Cpu.Feature;4const CpuFeature = std.Target.Cpu.Feature;
3const CpuModel = std.Target.Cpu.Model;5const CpuModel = std.Target.Cpu.Model;
46
5pub const Feature = enum {};7pub const Feature = enum {
8 p2,
9};
610
7pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;11pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
8pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;12pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
9pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;13pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
10pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;14pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
1115
12pub const all_features: [0]CpuFeature = .{};16pub const all_features = blk: {
17 const len = @typeInfo(Feature).@"enum".fields.len;
18 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
19 var result: [len]CpuFeature = undefined;
20 result[@intFromEnum(Feature.p2)] = .{
21 .llvm_name = null,
22 .description = "Enable Propeller 2",
23 .dependencies = featureSet(&[_]Feature{}),
24 };
25 const ti = @typeInfo(Feature);
26 for (&result, 0..) |*elem, i| {
27 elem.index = i;
28 elem.name = ti.@"enum".fields[i].name;
29 }
30 break :blk result;
31};
1332
14pub const cpu = struct {33pub const cpu = struct {
15 pub const generic = CpuModel{34 pub const p1: CpuModel = .{
16 .name = "generic",35 .name = "p1",
17 .llvm_name = null,36 .llvm_name = null,
18 .features = featureSet(&[_]Feature{}),37 .features = featureSet(&[_]Feature{}),
19 };38 };
39 pub const p2: CpuModel = .{
40 .name = "p2",
41 .llvm_name = null,
42 .features = featureSet(&[_]Feature{
43 .p2,
44 }),
45 };
20};46};
lib/std/builtin.zig+1-4
...@@ -371,12 +371,9 @@ pub const CallingConvention = union(enum(u8)) {...@@ -371,12 +371,9 @@ pub const CallingConvention = union(enum(u8)) {
371 /// The standard `msp430` calling convention.371 /// The standard `msp430` calling convention.
372 msp430_eabi: CommonOptions,372 msp430_eabi: CommonOptions,
373373
374 /// The standard `propeller1` calling convention.374 /// The standard `propeller` calling convention.
375 propeller1_sysv: CommonOptions,375 propeller1_sysv: CommonOptions,
376376
377 /// The standard `propeller2` calling convention.
378 propeller2_sysv: CommonOptions,
379
380 // Calling conventions for the `s390x` architecture.377 // Calling conventions for the `s390x` architecture.
381 s390x_sysv: CommonOptions,378 s390x_sysv: CommonOptions,
382 s390x_sysv_vx: CommonOptions,379 s390x_sysv_vx: CommonOptions,
src/Sema.zig+3-2
...@@ -37271,6 +37271,7 @@ pub fn analyzeAsAddressSpace(...@@ -37271,6 +37271,7 @@ pub fn analyzeAsAddressSpace(
37271 const is_spirv = arch.isSpirV();37271 const is_spirv = arch.isSpirV();
37272 const is_gpu = is_nv or is_amd or is_spirv;37272 const is_gpu = is_nv or is_amd or is_spirv;
3727337273
37274 // TODO: Deduplicate with `std.Target.Cpu.Arch.supportsAddressSpace`.
37274 const supported = switch (address_space) {37275 const supported = switch (address_space) {
37275 // TODO: on spir-v only when os is opencl.37276 // TODO: on spir-v only when os is opencl.
37276 .generic => true,37277 .generic => true,
...@@ -37283,8 +37284,8 @@ pub fn analyzeAsAddressSpace(...@@ -37283,8 +37284,8 @@ pub fn analyzeAsAddressSpace(
37283 // TODO this should also check how many flash banks the cpu has37284 // TODO this should also check how many flash banks the cpu has
37284 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,37285 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,
3728537286
37286 .cog, .hub => arch.isPropeller(),37287 .cog, .hub => arch == .propeller,
37287 .lut => (arch == .propeller2),37288 .lut => arch == .propeller and std.Target.propeller.featureSetHas(target.cpu.features, .p2),
37288 };37289 };
3728937290
37290 if (!supported) {37291 if (!supported) {
src/Type.zig+1-1
...@@ -1647,7 +1647,7 @@ pub fn maxIntAlignment(target: std.Target) u16 {...@@ -1647,7 +1647,7 @@ pub fn maxIntAlignment(target: std.Target) u16 {
1647 .avr => 1,1647 .avr => 1,
1648 .msp430 => 2,1648 .msp430 => 2,
1649 .xcore => 4,1649 .xcore => 4,
1650 .propeller1, .propeller2 => 4,1650 .propeller => 4,
16511651
1652 .arm,1652 .arm,
1653 .armeb,1653 .armeb,
src/Zcu.zig+1-2
...@@ -3619,8 +3619,7 @@ pub fn atomicPtrAlignment(...@@ -3619,8 +3619,7 @@ pub fn atomicPtrAlignment(
3619 .spirv32,3619 .spirv32,
3620 .loongarch32,3620 .loongarch32,
3621 .xtensa,3621 .xtensa,
3622 .propeller1,3622 .propeller,
3623 .propeller2,
3624 => 32,3623 => 32,
36253624
3626 .amdgcn,3625 .amdgcn,
src/codegen/llvm.zig+2-5
...@@ -98,8 +98,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {...@@ -98,8 +98,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
98 .ve => "ve",98 .ve => "ve",
9999
100 .kalimba,100 .kalimba,
101 .propeller1,101 .propeller,
102 .propeller2,
103 => unreachable, // Gated by hasLlvmSupport().102 => unreachable, // Gated by hasLlvmSupport().
104103
105 };104 };
...@@ -11834,7 +11833,6 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: std.Targ...@@ -11834,7 +11833,6 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: std.Targ
11834 .m68k_gnu,11833 .m68k_gnu,
11835 .msp430_eabi,11834 .msp430_eabi,
11836 .propeller1_sysv,11835 .propeller1_sysv,
11837 .propeller2_sysv,
11838 .s390x_sysv,11836 .s390x_sysv,
11839 .s390x_sysv_vx,11837 .s390x_sysv_vx,
11840 .ve_sysv,11838 .ve_sysv,
...@@ -13023,8 +13021,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {...@@ -13023,8 +13021,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1302313021
13024 // LLVM does does not have a backend for these.13022 // LLVM does does not have a backend for these.
13025 .kalimba,13023 .kalimba,
13026 .propeller1,13024 .propeller,
13027 .propeller2,
13028 => unreachable,13025 => unreachable,
13029 }13026 }
13030}13027}
src/target.zig+1-2
...@@ -195,8 +195,7 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {...@@ -195,8 +195,7 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
195195
196 // No LLVM backend exists.196 // No LLVM backend exists.
197 .kalimba,197 .kalimba,
198 .propeller1,198 .propeller,
199 .propeller2,
200 => false,199 => false,
201 };200 };
202}201}
tools/update_cpu_features.zig+23
...@@ -1016,6 +1016,29 @@ const targets = [_]ArchTarget{...@@ -1016,6 +1016,29 @@ const targets = [_]ArchTarget{
1016 "ppc32",1016 "ppc32",
1017 },1017 },
1018 },1018 },
1019 .{
1020 .zig_name = "propeller",
1021 .llvm = null,
1022 .extra_features = &.{
1023 .{
1024 .zig_name = "p2",
1025 .desc = "Enable Propeller 2",
1026 .deps = &.{},
1027 },
1028 },
1029 .extra_cpus = &.{
1030 .{
1031 .llvm_name = null,
1032 .zig_name = "p1",
1033 .features = &.{},
1034 },
1035 .{
1036 .llvm_name = null,
1037 .zig_name = "p2",
1038 .features = &.{"p2"},
1039 },
1040 },
1041 },
1019 .{1042 .{
1020 .zig_name = "riscv",1043 .zig_name = "riscv",
1021 .llvm = .{1044 .llvm = .{