authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-01-24 00:50:39+01:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-02-17 19:17:55+01:00
log2fe32ef847dd2f19113b86036357beeddbd08f05
tree911bf7a5f1fdef22457078eaf056cbbe2e66eafd
parent5248f0a9095bac52b5a066c0ea0a317439e6cf2f
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: Remove Cpu.Arch.propeller2 and use a CPU feature instead.

9 files changed, 76 insertions(+), 55 deletions(-)

lib/std/Target.zig+14-35
......@@ -763,6 +763,7 @@ pub const mips = @import("Target/mips.zig");
763763pub const msp430 = @import("Target/msp430.zig");
764764pub const nvptx = @import("Target/nvptx.zig");
765765pub const powerpc = @import("Target/powerpc.zig");
766pub const propeller = @import("Target/propeller.zig");
766767pub const riscv = @import("Target/riscv.zig");
767768pub const sparc = @import("Target/sparc.zig");
768769pub const spirv = @import("Target/spirv.zig");
......@@ -772,7 +773,6 @@ pub const wasm = @import("Target/wasm.zig");
772773pub const x86 = @import("Target/x86.zig");
773774pub const xcore = @import("Target/xcore.zig");
774775pub const xtensa = @import("Target/xtensa.zig");
775pub const propeller = @import("Target/propeller.zig");
776776
777777pub const Abi = enum {
778778 none,
......@@ -1081,6 +1081,7 @@ pub fn toElfMachine(target: Target) std.elf.EM {
10811081 .msp430 => .MSP430,
10821082 .powerpc, .powerpcle => .PPC,
10831083 .powerpc64, .powerpc64le => .PPC64,
1084 .propeller => .PROPELLER,
10841085 .riscv32, .riscv64 => .RISCV,
10851086 .s390x => .S390,
10861087 .sparc => if (Target.sparc.featureSetHas(target.cpu.features, .v9)) .SPARC32PLUS else .SPARC,
......@@ -1091,9 +1092,6 @@ pub fn toElfMachine(target: Target) std.elf.EM {
10911092 .xcore => .XCORE,
10921093 .xtensa => .XTENSA,
10931094
1094 .propeller1 => .PROPELLER,
1095 .propeller2 => .PROPELLER2,
1096
10971095 .nvptx,
10981096 .nvptx64,
10991097 .spirv,
......@@ -1152,8 +1150,7 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {
11521150 .wasm64,
11531151 .xcore,
11541152 .xtensa,
1155 .propeller1,
1156 .propeller2,
1153 .propeller,
11571154 => .UNKNOWN,
11581155 };
11591156}
......@@ -1366,8 +1363,7 @@ pub const Cpu = struct {
13661363 powerpcle,
13671364 powerpc64,
13681365 powerpc64le,
1369 propeller1,
1370 propeller2,
1366 propeller,
13711367 riscv32,
13721368 riscv64,
13731369 s390x,
......@@ -1517,14 +1513,6 @@ pub const Cpu = struct {
15171513 };
15181514 }
15191515
1520 /// Returns if the architecture is a Parallax propeller architecture.
1521 pub inline fn isPropeller(arch: Arch) bool {
1522 return switch (arch) {
1523 .propeller1, .propeller2 => true,
1524 else => false,
1525 };
1526 }
1527
15281516 pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) !*const Cpu.Model {
15291517 for (arch.allCpuModels()) |cpu| {
15301518 if (std.mem.eql(u8, cpu_name, cpu.name)) {
......@@ -1568,8 +1556,7 @@ pub const Cpu = struct {
15681556 .loongarch32,
15691557 .loongarch64,
15701558 .arc,
1571 .propeller1,
1572 .propeller2,
1559 .propeller,
15731560 => .little,
15741561
15751562 .armeb,
......@@ -1604,8 +1591,8 @@ pub const Cpu = struct {
16041591 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,
16051592
16061593 // Propeller address spaces:
1607 .cog, .hub => arch.isPropeller(),
1608 .lut => (arch == .propeller2),
1594 .cog, .hub => arch == .propeller,
1595 .lut => arch == .propeller, // TODO: This should check for the `p2` CPU feature.
16091596 };
16101597 }
16111598
......@@ -1618,6 +1605,7 @@ pub const Cpu = struct {
16181605 .loongarch32, .loongarch64 => "loongarch",
16191606 .mips, .mipsel, .mips64, .mips64el => "mips",
16201607 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
1608 .propeller => "propeller",
16211609 .riscv32, .riscv64 => "riscv",
16221610 .sparc, .sparc64 => "sparc",
16231611 .s390x => "s390x",
......@@ -1625,7 +1613,6 @@ pub const Cpu = struct {
16251613 .nvptx, .nvptx64 => "nvptx",
16261614 .wasm32, .wasm64 => "wasm",
16271615 .spirv, .spirv32, .spirv64 => "spirv",
1628 .propeller1, .propeller2 => "propeller",
16291616 else => @tagName(arch),
16301617 };
16311618 }
......@@ -1851,10 +1838,7 @@ pub const Cpu = struct {
18511838 => &.{.msp430},
18521839
18531840 .propeller1_sysv,
1854 => &.{.propeller1},
1855
1856 .propeller2_sysv,
1857 => &.{.propeller2},
1841 => &.{.propeller},
18581842
18591843 .s390x_sysv,
18601844 .s390x_sysv_vx,
......@@ -1933,8 +1917,7 @@ pub const Cpu = struct {
19331917 .msp430 => &msp430.cpu.generic,
19341918 .powerpc, .powerpcle => &powerpc.cpu.ppc,
19351919 .powerpc64, .powerpc64le => &powerpc.cpu.ppc64,
1936 .propeller1 => &propeller.cpu.generic,
1937 .propeller2 => &propeller.cpu.generic,
1920 .propeller => &propeller.cpu.p1,
19381921 .riscv32 => &riscv.cpu.generic_rv32,
19391922 .riscv64 => &riscv.cpu.generic_rv64,
19401923 .spirv, .spirv32, .spirv64 => &spirv.cpu.generic,
......@@ -2647,8 +2630,7 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
26472630 .spirv32,
26482631 .loongarch32,
26492632 .xtensa,
2650 .propeller1,
2651 .propeller2,
2633 .propeller,
26522634 => 32,
26532635
26542636 .aarch64,
......@@ -3159,8 +3141,7 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {
31593141 .xcore,
31603142 .kalimba,
31613143 .xtensa,
3162 .propeller1,
3163 .propeller2,
3144 .propeller,
31643145 => 4,
31653146
31663147 .arm,
......@@ -3254,8 +3235,7 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {
32543235 .xcore,
32553236 .kalimba,
32563237 .xtensa,
3257 .propeller1,
3258 .propeller2,
3238 .propeller,
32593239 => 4,
32603240
32613241 .arc,
......@@ -3360,8 +3340,7 @@ pub fn cCallingConvention(target: Target) ?std.builtin.CallingConvention {
33603340 else
33613341 .{ .m68k_sysv = .{} },
33623342 .msp430 => .{ .msp430_eabi = .{} },
3363 .propeller1 => .{ .propeller1_sysv = .{} },
3364 .propeller2 => .{ .propeller2_sysv = .{} },
3343 .propeller => .{ .propeller1_sysv = .{} },
33653344 .s390x => .{ .s390x_sysv = .{} },
33663345 .ve => .{ .ve_sysv = .{} },
33673346 .xcore => .{ .xcore_xs1 = .{} },
lib/std/Target/propeller.zig+30-4
......@@ -1,20 +1,46 @@
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
13const std = @import("../std.zig");
24const CpuFeature = std.Target.Cpu.Feature;
35const CpuModel = std.Target.Cpu.Model;
46
5pub const Feature = enum {};
7pub const Feature = enum {
8 p2,
9};
610
711pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
812pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
913pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
1014pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
1115
12pub const all_features: [0]CpuFeature = .{};
16pub const all_features = blk: {
17 const len = @typeInfo(Feature).@"enum".fields.len;
18 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
19 var result: [len]CpuFeature = undefined;
20 result[@intFromEnum(Feature.p2)] = .{
21 .llvm_name = null,
22 .description = "Enable Propeller 2",
23 .dependencies = featureSet(&[_]Feature{}),
24 };
25 const ti = @typeInfo(Feature);
26 for (&result, 0..) |*elem, i| {
27 elem.index = i;
28 elem.name = ti.@"enum".fields[i].name;
29 }
30 break :blk result;
31};
1332
1433pub const cpu = struct {
15 pub const generic = CpuModel{
16 .name = "generic",
34 pub const p1: CpuModel = .{
35 .name = "p1",
1736 .llvm_name = null,
1837 .features = featureSet(&[_]Feature{}),
1938 };
39 pub const p2: CpuModel = .{
40 .name = "p2",
41 .llvm_name = null,
42 .features = featureSet(&[_]Feature{
43 .p2,
44 }),
45 };
2046};
lib/std/builtin.zig+1-4
......@@ -371,12 +371,9 @@ pub const CallingConvention = union(enum(u8)) {
371371 /// The standard `msp430` calling convention.
372372 msp430_eabi: CommonOptions,
373373
374 /// The standard `propeller1` calling convention.
374 /// The standard `propeller` calling convention.
375375 propeller1_sysv: CommonOptions,
376376
377 /// The standard `propeller2` calling convention.
378 propeller2_sysv: CommonOptions,
379
380377 // Calling conventions for the `s390x` architecture.
381378 s390x_sysv: CommonOptions,
382379 s390x_sysv_vx: CommonOptions,
src/Sema.zig+3-2
......@@ -37271,6 +37271,7 @@ pub fn analyzeAsAddressSpace(
3727137271 const is_spirv = arch.isSpirV();
3727237272 const is_gpu = is_nv or is_amd or is_spirv;
3727337273
37274 // TODO: Deduplicate with `std.Target.Cpu.Arch.supportsAddressSpace`.
3727437275 const supported = switch (address_space) {
3727537276 // TODO: on spir-v only when os is opencl.
3727637277 .generic => true,
......@@ -37283,8 +37284,8 @@ pub fn analyzeAsAddressSpace(
3728337284 // TODO this should also check how many flash banks the cpu has
3728437285 .flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,
3728537286
37286 .cog, .hub => arch.isPropeller(),
37287 .lut => (arch == .propeller2),
37287 .cog, .hub => arch == .propeller,
37288 .lut => arch == .propeller and std.Target.propeller.featureSetHas(target.cpu.features, .p2),
3728837289 };
3728937290
3729037291 if (!supported) {
src/Type.zig+1-1
......@@ -1647,7 +1647,7 @@ pub fn maxIntAlignment(target: std.Target) u16 {
16471647 .avr => 1,
16481648 .msp430 => 2,
16491649 .xcore => 4,
1650 .propeller1, .propeller2 => 4,
1650 .propeller => 4,
16511651
16521652 .arm,
16531653 .armeb,
src/Zcu.zig+1-2
......@@ -3619,8 +3619,7 @@ pub fn atomicPtrAlignment(
36193619 .spirv32,
36203620 .loongarch32,
36213621 .xtensa,
3622 .propeller1,
3623 .propeller2,
3622 .propeller,
36243623 => 32,
36253624
36263625 .amdgcn,
src/codegen/llvm.zig+2-5
......@@ -98,8 +98,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
9898 .ve => "ve",
9999
100100 .kalimba,
101 .propeller1,
102 .propeller2,
101 .propeller,
103102 => unreachable, // Gated by hasLlvmSupport().
104103
105104 };
......@@ -11834,7 +11833,6 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: std.Targ
1183411833 .m68k_gnu,
1183511834 .msp430_eabi,
1183611835 .propeller1_sysv,
11837 .propeller2_sysv,
1183811836 .s390x_sysv,
1183911837 .s390x_sysv_vx,
1184011838 .ve_sysv,
......@@ -13023,8 +13021,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1302313021
1302413022 // LLVM does does not have a backend for these.
1302513023 .kalimba,
13026 .propeller1,
13027 .propeller2,
13024 .propeller,
1302813025 => unreachable,
1302913026 }
1303013027}
src/target.zig+1-2
......@@ -195,8 +195,7 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
195195
196196 // No LLVM backend exists.
197197 .kalimba,
198 .propeller1,
199 .propeller2,
198 .propeller,
200199 => false,
201200 };
202201}
tools/update_cpu_features.zig+23
......@@ -1016,6 +1016,29 @@ const targets = [_]ArchTarget{
10161016 "ppc32",
10171017 },
10181018 },
1019 .{
1020 .zig_name = "propeller",
1021 .llvm = null,
1022 .extra_features = &.{
1023 .{
1024 .zig_name = "p2",
1025 .desc = "Enable Propeller 2",
1026 .deps = &.{},
1027 },
1028 },
1029 .extra_cpus = &.{
1030 .{
1031 .llvm_name = null,
1032 .zig_name = "p1",
1033 .features = &.{},
1034 },
1035 .{
1036 .llvm_name = null,
1037 .zig_name = "p2",
1038 .features = &.{"p2"},
1039 },
1040 },
1041 },
10191042 .{
10201043 .zig_name = "riscv",
10211044 .llvm = .{