Commit 3ed40b114020ff774279a5af993851d74da64b52 | zig

author	Andrew Kelley <andrew@ziglang.org> 2023-08-11 16:15:19-07:00
committer	Andrew Kelley <andrew@ziglang.org> 2023-09-19 09:37:31-07:00
log	3ed40b114020ff774279a5af993851d74da64b52
tree	733076dbb0b66df6fd51a6bcadbc0091b4eab99f
parent	1c7adf5064386fe668fe580d701db07d226245ed

update CPU features to LLVM 17

release/17.x branch, commit 8f4dd44097c9ae25dd203d5ac87f3b48f854bba8

12 files changed, 1142 insertions(+), 295 deletions(-)

lib
- std
  - target
    aarch64.zig
    amdgpu.zig
    arm.zig
    avr.zig
    bpf.zig
    csky.zig
    loongarch.zig
    m68k.zig
    nvptx.zig
    riscv.zig
    x86.zig
tools
- update_cpu_features.zig

lib/std/target/aarch64.zig+53

...	...	@@ -37,6 +37,7 @@ pub const Feature = enum {
37	37	ccdp,
38	38	ccidx,
39	39	ccpp,
	40	chk,
40	41	clrbhb,
41	42	cmp_bcc_fusion,
42	43	complxnum,
...	...	@@ -68,12 +69,14 @@ pub const Feature = enum {
68	69	fptoint,
69	70	fullfp16,
70	71	fuse_address,
	72	fuse_addsub_2reg_const1,
71	73	fuse_adrp_add,
72	74	fuse_aes,
73	75	fuse_arith_logic,
74	76	fuse_crypto_eor,
75	77	fuse_csel,
76	78	fuse_literals,
	79	gcs,
77	80	harden_sls_blr,
78	81	harden_sls_nocomdat,
79	82	harden_sls_retbr,
...	...	@@ -96,6 +99,7 @@ pub const Feature = enum {
96	99	nmi,
97	100	no_bti_at_return_twice,
98	101	no_neg_immediates,
	102	no_sve_fp_ld1r,
99	103	no_zcz_fp,
100	104	nv,
101	105	outline_atomics,
...	...	@@ -173,6 +177,7 @@ pub const Feature = enum {
173	177	tpidr_el1,
174	178	tpidr_el2,
175	179	tpidr_el3,
	180	tpidrro_el0,
176	181	tracev8_4,
177	182	trbe,
178	183	uaops,
...	...	@@ -233,6 +238,7 @@ pub const all_features = blk: {
233	238	.fuse_adrp_add,
234	239	.fuse_aes,
235	240	.fuse_literals,
	241	.predictable_select_expensive,
236	242	}),
237	243	};
238	244	result[@intFromEnum(Feature.a710)] = .{
...	...	@@ -244,6 +250,7 @@ pub const all_features = blk: {
244	250	.fuse_adrp_add,
245	251	.fuse_aes,
246	252	.lsl_fast,
	253	.predictable_select_expensive,
247	254	.use_postra_scheduler,
248	255	}),
249	256	};
...	...	@@ -255,6 +262,7 @@ pub const all_features = blk: {
255	262	.fuse_adrp_add,
256	263	.fuse_aes,
257	264	.lsl_fast,
	265	.predictable_select_expensive,
258	266	}),
259	267	};
260	268	result[@intFromEnum(Feature.a78)] = .{
...	...	@@ -266,6 +274,7 @@ pub const all_features = blk: {
266	274	.fuse_adrp_add,
267	275	.fuse_aes,
268	276	.lsl_fast,
	277	.predictable_select_expensive,
269	278	.use_postra_scheduler,
270	279	}),
271	280	};
...	...	@@ -278,6 +287,7 @@ pub const all_features = blk: {
278	287	.fuse_adrp_add,
279	288	.fuse_aes,
280	289	.lsl_fast,
	290	.predictable_select_expensive,
281	291	.use_postra_scheduler,
282	292	}),
283	293	};
...	...	@@ -415,6 +425,11 @@ pub const all_features = blk: {
415	425	.description = "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)",
416	426	.dependencies = featureSet(&[_]Feature{}),
417	427	};
	428	result[@intFromEnum(Feature.chk)] = .{
	429	.llvm_name = "chk",
	430	.description = "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)",
	431	.dependencies = featureSet(&[_]Feature{}),
	432	};
418	433	result[@intFromEnum(Feature.clrbhb)] = .{
419	434	.llvm_name = "clrbhb",
420	435	.description = "Enable Clear BHB instruction (FEAT_CLRBHB)",
...	...	@@ -591,6 +606,11 @@ pub const all_features = blk: {
591	606	.description = "CPU fuses address generation and memory operations",
592	607	.dependencies = featureSet(&[_]Feature{}),
593	608	};
	609	result[@intFromEnum(Feature.fuse_addsub_2reg_const1)] = .{
	610	.llvm_name = "fuse-addsub-2reg-const1",
	611	.description = "CPU fuses (a + b + 1) and (a - b - 1)",
	612	.dependencies = featureSet(&[_]Feature{}),
	613	};
594	614	result[@intFromEnum(Feature.fuse_adrp_add)] = .{
595	615	.llvm_name = "fuse-adrp-add",
596	616	.description = "CPU fuses adrp+add operations",
...	...	@@ -621,6 +641,13 @@ pub const all_features = blk: {
621	641	.description = "CPU fuses literal generation operations",
622	642	.dependencies = featureSet(&[_]Feature{}),
623	643	};
	644	result[@intFromEnum(Feature.gcs)] = .{
	645	.llvm_name = "gcs",
	646	.description = "Enable Armv9.4-A Guarded Call Stack Extension",
	647	.dependencies = featureSet(&[_]Feature{
	648	.chk,
	649	}),
	650	};
624	651	result[@intFromEnum(Feature.harden_sls_blr)] = .{
625	652	.llvm_name = "harden-sls-blr",
626	653	.description = "Harden against straight line speculation across BLR instructions",
...	...	@@ -741,6 +768,11 @@ pub const all_features = blk: {
741	768	.description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
742	769	.dependencies = featureSet(&[_]Feature{}),
743	770	};
	771	result[@intFromEnum(Feature.no_sve_fp_ld1r)] = .{
	772	.llvm_name = "no-sve-fp-ld1r",
	773	.description = "Avoid using LD1RX instructions for FP",
	774	.dependencies = featureSet(&[_]Feature{}),
	775	};
744	776	result[@intFromEnum(Feature.no_zcz_fp)] = .{
745	777	.llvm_name = "no-zcz-fp",
746	778	.description = "Has no zero-cycle zeroing instructions for FP registers",
...	...	@@ -1171,6 +1203,11 @@ pub const all_features = blk: {
1171	1203	.description = "Permit use of TPIDR_EL3 for the TLS base",
1172	1204	.dependencies = featureSet(&[_]Feature{}),
1173	1205	};
	1206	result[@intFromEnum(Feature.tpidrro_el0)] = .{
	1207	.llvm_name = "tpidrro-el0",
	1208	.description = "Permit use of TPIDRRO_EL0 for the TLS base",
	1209	.dependencies = featureSet(&[_]Feature{}),
	1210	};
1174	1211	result[@intFromEnum(Feature.tracev8_4)] = .{
1175	1212	.llvm_name = "tracev8.4",
1176	1213	.description = "Enable v8.4-A Trace extension (FEAT_TRF)",
...	...	@@ -1311,6 +1348,7 @@ pub const all_features = blk: {
1311	1348	.llvm_name = "v8.9a",
1312	1349	.description = "Support ARM v8.9a instructions",
1313	1350	.dependencies = featureSet(&[_]Feature{
	1351	.chk,
1314	1352	.clrbhb,
1315	1353	.cssc,
1316	1354	.prfm_slc_target,
...	...	@@ -1974,6 +2012,7 @@ pub const cpu = struct {
1974	2012	.lsl_fast,
1975	2013	.mte,
1976	2014	.perfmon,
	2015	.predictable_select_expensive,
1977	2016	.spe,
1978	2017	.sve2_bitperm,
1979	2018	.use_postra_scheduler,
...	...	@@ -1991,6 +2030,7 @@ pub const cpu = struct {
1991	2030	.fuse_aes,
1992	2031	.fuse_literals,
1993	2032	.perfmon,
	2033	.predictable_select_expensive,
1994	2034	.v8a,
1995	2035	}),
1996	2036	};
...	...	@@ -2004,6 +2044,7 @@ pub const cpu = struct {
2004	2044	.fuse_adrp_add,
2005	2045	.fuse_aes,
2006	2046	.perfmon,
	2047	.predictable_select_expensive,
2007	2048	.v8a,
2008	2049	}),
2009	2050	};
...	...	@@ -2018,6 +2059,7 @@ pub const cpu = struct {
2018	2059	.fuse_adrp_add,
2019	2060	.fuse_aes,
2020	2061	.perfmon,
	2062	.predictable_select_expensive,
2021	2063	.rcpc,
2022	2064	.v8_2a,
2023	2065	}),
...	...	@@ -2063,6 +2105,7 @@ pub const cpu = struct {
2063	2105	.fuse_aes,
2064	2106	.lsl_fast,
2065	2107	.perfmon,
	2108	.predictable_select_expensive,
2066	2109	.rcpc,
2067	2110	.ssbs,
2068	2111	.v8_2a,
...	...	@@ -2126,6 +2169,7 @@ pub const cpu = struct {
2126	2169	.fuse_aes,
2127	2170	.lsl_fast,
2128	2171	.perfmon,
	2172	.predictable_select_expensive,
2129	2173	.rcpc,
2130	2174	.spe,
2131	2175	.ssbs,
...	...	@@ -2149,6 +2193,7 @@ pub const cpu = struct {
2149	2193	.lsl_fast,
2150	2194	.pauth,
2151	2195	.perfmon,
	2196	.predictable_select_expensive,
2152	2197	.rcpc_immo,
2153	2198	.spe,
2154	2199	.ssbs,
...	...	@@ -2171,6 +2216,7 @@ pub const cpu = struct {
2171	2216	.lsl_fast,
2172	2217	.mte,
2173	2218	.perfmon,
	2219	.predictable_select_expensive,
2174	2220	.sve2_bitperm,
2175	2221	.use_postra_scheduler,
2176	2222	.v9a,
...	...	@@ -2190,6 +2236,7 @@ pub const cpu = struct {
2190	2236	.lsl_fast,
2191	2237	.mte,
2192	2238	.perfmon,
	2239	.predictable_select_expensive,
2193	2240	.spe,
2194	2241	.sve2_bitperm,
2195	2242	.use_postra_scheduler,
...	...	@@ -2383,6 +2430,7 @@ pub const cpu = struct {
2383	2430	.i8mm,
2384	2431	.lsl_fast,
2385	2432	.perfmon,
	2433	.predictable_select_expensive,
2386	2434	.rand,
2387	2435	.spe,
2388	2436	.ssbs,
...	...	@@ -2419,6 +2467,7 @@ pub const cpu = struct {
2419	2467	.fuse_aes,
2420	2468	.lsl_fast,
2421	2469	.perfmon,
	2470	.predictable_select_expensive,
2422	2471	.rcpc,
2423	2472	.spe,
2424	2473	.ssbs,
...	...	@@ -2440,6 +2489,7 @@ pub const cpu = struct {
2440	2489	.lsl_fast,
2441	2490	.mte,
2442	2491	.perfmon,
	2492	.predictable_select_expensive,
2443	2493	.sve2_bitperm,
2444	2494	.use_postra_scheduler,
2445	2495	.v8_5a,
...	...	@@ -2458,7 +2508,9 @@ pub const cpu = struct {
2458	2508	.fuse_aes,
2459	2509	.i8mm,
2460	2510	.lsl_fast,
	2511	.no_sve_fp_ld1r,
2461	2512	.perfmon,
	2513	.predictable_select_expensive,
2462	2514	.rand,
2463	2515	.spe,
2464	2516	.ssbs,
...	...	@@ -2480,6 +2532,7 @@ pub const cpu = struct {
2480	2532	.lsl_fast,
2481	2533	.mte,
2482	2534	.perfmon,
	2535	.predictable_select_expensive,
2483	2536	.rand,
2484	2537	.spe,
2485	2538	.sve2_bitperm,

lib/std/target/amdgpu.zig+215-35

...	...	@@ -10,14 +10,20 @@ pub const Feature = enum {
10	10	add_no_carry_insts,
11	11	aperture_regs,
12	12	architected_flat_scratch,
	13	architected_sgprs,
	14	atomic_buffer_global_pk_add_f16_insts,
	15	atomic_buffer_global_pk_add_f16_no_rtn_insts,
	16	atomic_ds_pk_add_16_insts,
13	17	atomic_fadd_no_rtn_insts,
14	18	atomic_fadd_rtn_insts,
15		atomic_pk_fadd_no_rtn_insts,
	19	atomic_flat_pk_add_16_insts,
	20	atomic_global_pk_add_bf16_inst,
16	21	auto_waitcnt_before_barrier,
17	22	back_off_barrier,
18	23	ci_insts,
19	24	cumode,
20	25	dl_insts,
	26	dot10_insts,
21	27	dot1_insts,
22	28	dot2_insts,
23	29	dot3_insts,
...	...	@@ -46,6 +52,7 @@ pub const Feature = enum {
46	52	fma_mix_insts,
47	53	fmacf64_inst,
48	54	fmaf,
	55	force_store_sc0_sc1,
49	56	fp64,
50	57	fp8_insts,
51	58	full_rate_64_ops,
...	...	@@ -96,12 +103,11 @@ pub const Feature = enum {
96	103	no_sdst_cmpx,
97	104	nsa_clause_bug,
98	105	nsa_encoding,
99		nsa_max_size_13,
100		nsa_max_size_5,
101	106	nsa_to_vmem_bug,
102	107	offset_3f_bug,
103	108	packed_fp32_ops,
104	109	packed_tid,
	110	partial_nsa_encoding,
105	111	pk_fmac_f16_inst,
106	112	promote_alloca,
107	113	prt_strict_null,
...	...	@@ -187,6 +193,30 @@ pub const all_features = blk: {
187	193	.description = "Flat Scratch register is a readonly SPI initialized architected register",
188	194	.dependencies = featureSet(&[_]Feature{}),
189	195	};
	196	result[@intFromEnum(Feature.architected_sgprs)] = .{
	197	.llvm_name = "architected-sgprs",
	198	.description = "Enable the architected SGPRs",
	199	.dependencies = featureSet(&[_]Feature{}),
	200	};
	201	result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_insts)] = .{
	202	.llvm_name = "atomic-buffer-global-pk-add-f16-insts",
	203	.description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that can return original value",
	204	.dependencies = featureSet(&[_]Feature{
	205	.flat_global_insts,
	206	}),
	207	};
	208	result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_no_rtn_insts)] = .{
	209	.llvm_name = "atomic-buffer-global-pk-add-f16-no-rtn-insts",
	210	.description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that don't return original value",
	211	.dependencies = featureSet(&[_]Feature{
	212	.flat_global_insts,
	213	}),
	214	};
	215	result[@intFromEnum(Feature.atomic_ds_pk_add_16_insts)] = .{
	216	.llvm_name = "atomic-ds-pk-add-16-insts",
	217	.description = "Has ds_pk_add_bf16, ds_pk_add_f16, ds_pk_add_rtn_bf16, ds_pk_add_rtn_f16 instructions",
	218	.dependencies = featureSet(&[_]Feature{}),
	219	};
190	220	result[@intFromEnum(Feature.atomic_fadd_no_rtn_insts)] = .{
191	221	.llvm_name = "atomic-fadd-no-rtn-insts",
192	222	.description = "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that don't return original value",
...	...	@@ -201,9 +231,14 @@ pub const all_features = blk: {
201	231	.flat_global_insts,
202	232	}),
203	233	};
204		result[@intFromEnum(Feature.atomic_pk_fadd_no_rtn_insts)] = .{
205		.llvm_name = "atomic-pk-fadd-no-rtn-insts",
206		.description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that don't return original value",
	234	result[@intFromEnum(Feature.atomic_flat_pk_add_16_insts)] = .{
	235	.llvm_name = "atomic-flat-pk-add-16-insts",
	236	.description = "Has flat_atomic_pk_add_f16 and flat_atomic_pk_add_bf16 instructions",
	237	.dependencies = featureSet(&[_]Feature{}),
	238	};
	239	result[@intFromEnum(Feature.atomic_global_pk_add_bf16_inst)] = .{
	240	.llvm_name = "atomic-global-pk-add-bf16-inst",
	241	.description = "Has global_atomic_pk_add_bf16 instruction",
207	242	.dependencies = featureSet(&[_]Feature{
208	243	.flat_global_insts,
209	244	}),
...	...	@@ -233,6 +268,11 @@ pub const all_features = blk: {
233	268	.description = "Has v_fmac_f32 and v_xnor_b32 instructions",
234	269	.dependencies = featureSet(&[_]Feature{}),
235	270	};
	271	result[@intFromEnum(Feature.dot10_insts)] = .{
	272	.llvm_name = "dot10-insts",
	273	.description = "Has v_dot2_f32_f16 instruction",
	274	.dependencies = featureSet(&[_]Feature{}),
	275	};
236	276	result[@intFromEnum(Feature.dot1_insts)] = .{
237	277	.llvm_name = "dot1-insts",
238	278	.description = "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions",
...	...	@@ -265,7 +305,7 @@ pub const all_features = blk: {
265	305	};
266	306	result[@intFromEnum(Feature.dot7_insts)] = .{
267	307	.llvm_name = "dot7-insts",
268		.description = "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions",
	308	.description = "Has v_dot4_u32_u8, v_dot8_u32_u4 instructions",
269	309	.dependencies = featureSet(&[_]Feature{}),
270	310	};
271	311	result[@intFromEnum(Feature.dot8_insts)] = .{
...	...	@@ -373,6 +413,11 @@ pub const all_features = blk: {
373	413	.description = "Enable single precision FMA (not as fast as mul+add, but fused)",
374	414	.dependencies = featureSet(&[_]Feature{}),
375	415	};
	416	result[@intFromEnum(Feature.force_store_sc0_sc1)] = .{
	417	.llvm_name = "force-store-sc0-sc1",
	418	.description = "Has SC0 and SC1 on stores",
	419	.dependencies = featureSet(&[_]Feature{}),
	420	};
376	421	result[@intFromEnum(Feature.fp64)] = .{
377	422	.llvm_name = "fp64",
378	423	.description = "Enable double precision operations",
...	...	@@ -742,16 +787,6 @@ pub const all_features = blk: {
742	787	.description = "Support NSA encoding for image instructions",
743	788	.dependencies = featureSet(&[_]Feature{}),
744	789	};
745		result[@intFromEnum(Feature.nsa_max_size_13)] = .{
746		.llvm_name = "nsa-max-size-13",
747		.description = "The maximum non-sequential address size in VGPRs.",
748		.dependencies = featureSet(&[_]Feature{}),
749		};
750		result[@intFromEnum(Feature.nsa_max_size_5)] = .{
751		.llvm_name = "nsa-max-size-5",
752		.description = "The maximum non-sequential address size in VGPRs.",
753		.dependencies = featureSet(&[_]Feature{}),
754		};
755	790	result[@intFromEnum(Feature.nsa_to_vmem_bug)] = .{
756	791	.llvm_name = "nsa-to-vmem-bug",
757	792	.description = "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero",
...	...	@@ -772,6 +807,11 @@ pub const all_features = blk: {
772	807	.description = "Workitem IDs are packed into v0 at kernel launch",
773	808	.dependencies = featureSet(&[_]Feature{}),
774	809	};
	810	result[@intFromEnum(Feature.partial_nsa_encoding)] = .{
	811	.llvm_name = "partial-nsa-encoding",
	812	.description = "Support partial NSA encoding for image instructions",
	813	.dependencies = featureSet(&[_]Feature{}),
	814	};
775	815	result[@intFromEnum(Feature.pk_fmac_f16_inst)] = .{
776	816	.llvm_name = "pk-fmac-f16-inst",
777	817	.description = "Has v_pk_fmac_f16 instruction",
...	...	@@ -1146,7 +1186,6 @@ pub const cpu = struct {
1146	1186	.negative_unaligned_scratch_offset_bug,
1147	1187	.nsa_clause_bug,
1148	1188	.nsa_encoding,
1149		.nsa_max_size_5,
1150	1189	.nsa_to_vmem_bug,
1151	1190	.offset_3f_bug,
1152	1191	.scalar_atomics,
...	...	@@ -1166,6 +1205,7 @@ pub const cpu = struct {
1166	1205	.features = featureSet(&[_]Feature{
1167	1206	.back_off_barrier,
1168	1207	.dl_insts,
	1208	.dot10_insts,
1169	1209	.dot1_insts,
1170	1210	.dot2_insts,
1171	1211	.dot5_insts,
...	...	@@ -1183,7 +1223,6 @@ pub const cpu = struct {
1183	1223	.negative_unaligned_scratch_offset_bug,
1184	1224	.nsa_clause_bug,
1185	1225	.nsa_encoding,
1186		.nsa_max_size_5,
1187	1226	.nsa_to_vmem_bug,
1188	1227	.offset_3f_bug,
1189	1228	.scalar_atomics,
...	...	@@ -1203,6 +1242,7 @@ pub const cpu = struct {
1203	1242	.features = featureSet(&[_]Feature{
1204	1243	.back_off_barrier,
1205	1244	.dl_insts,
	1245	.dot10_insts,
1206	1246	.dot1_insts,
1207	1247	.dot2_insts,
1208	1248	.dot5_insts,
...	...	@@ -1220,7 +1260,6 @@ pub const cpu = struct {
1220	1260	.negative_unaligned_scratch_offset_bug,
1221	1261	.nsa_clause_bug,
1222	1262	.nsa_encoding,
1223		.nsa_max_size_5,
1224	1263	.nsa_to_vmem_bug,
1225	1264	.offset_3f_bug,
1226	1265	.scalar_atomics,
...	...	@@ -1253,7 +1292,6 @@ pub const cpu = struct {
1253	1292	.negative_unaligned_scratch_offset_bug,
1254	1293	.nsa_clause_bug,
1255	1294	.nsa_encoding,
1256		.nsa_max_size_5,
1257	1295	.nsa_to_vmem_bug,
1258	1296	.offset_3f_bug,
1259	1297	.scalar_atomics,
...	...	@@ -1273,6 +1311,7 @@ pub const cpu = struct {
1273	1311	.features = featureSet(&[_]Feature{
1274	1312	.back_off_barrier,
1275	1313	.dl_insts,
	1314	.dot10_insts,
1276	1315	.dot1_insts,
1277	1316	.dot2_insts,
1278	1317	.dot5_insts,
...	...	@@ -1284,7 +1323,6 @@ pub const cpu = struct {
1284	1323	.gfx10_b_encoding,
1285	1324	.ldsbankcount32,
1286	1325	.nsa_encoding,
1287		.nsa_max_size_13,
1288	1326	.shader_cycles_register,
1289	1327	.wavefrontsize32,
1290	1328	}),
...	...	@@ -1295,6 +1333,7 @@ pub const cpu = struct {
1295	1333	.features = featureSet(&[_]Feature{
1296	1334	.back_off_barrier,
1297	1335	.dl_insts,
	1336	.dot10_insts,
1298	1337	.dot1_insts,
1299	1338	.dot2_insts,
1300	1339	.dot5_insts,
...	...	@@ -1306,7 +1345,6 @@ pub const cpu = struct {
1306	1345	.gfx10_b_encoding,
1307	1346	.ldsbankcount32,
1308	1347	.nsa_encoding,
1309		.nsa_max_size_13,
1310	1348	.shader_cycles_register,
1311	1349	.wavefrontsize32,
1312	1350	}),
...	...	@@ -1317,6 +1355,7 @@ pub const cpu = struct {
1317	1355	.features = featureSet(&[_]Feature{
1318	1356	.back_off_barrier,
1319	1357	.dl_insts,
	1358	.dot10_insts,
1320	1359	.dot1_insts,
1321	1360	.dot2_insts,
1322	1361	.dot5_insts,
...	...	@@ -1328,7 +1367,6 @@ pub const cpu = struct {
1328	1367	.gfx10_b_encoding,
1329	1368	.ldsbankcount32,
1330	1369	.nsa_encoding,
1331		.nsa_max_size_13,
1332	1370	.shader_cycles_register,
1333	1371	.wavefrontsize32,
1334	1372	}),
...	...	@@ -1339,6 +1377,7 @@ pub const cpu = struct {
1339	1377	.features = featureSet(&[_]Feature{
1340	1378	.back_off_barrier,
1341	1379	.dl_insts,
	1380	.dot10_insts,
1342	1381	.dot1_insts,
1343	1382	.dot2_insts,
1344	1383	.dot5_insts,
...	...	@@ -1350,7 +1389,6 @@ pub const cpu = struct {
1350	1389	.gfx10_b_encoding,
1351	1390	.ldsbankcount32,
1352	1391	.nsa_encoding,
1353		.nsa_max_size_13,
1354	1392	.shader_cycles_register,
1355	1393	.wavefrontsize32,
1356	1394	}),
...	...	@@ -1361,6 +1399,7 @@ pub const cpu = struct {
1361	1399	.features = featureSet(&[_]Feature{
1362	1400	.back_off_barrier,
1363	1401	.dl_insts,
	1402	.dot10_insts,
1364	1403	.dot1_insts,
1365	1404	.dot2_insts,
1366	1405	.dot5_insts,
...	...	@@ -1372,7 +1411,6 @@ pub const cpu = struct {
1372	1411	.gfx10_b_encoding,
1373	1412	.ldsbankcount32,
1374	1413	.nsa_encoding,
1375		.nsa_max_size_13,
1376	1414	.shader_cycles_register,
1377	1415	.wavefrontsize32,
1378	1416	}),
...	...	@@ -1383,6 +1421,7 @@ pub const cpu = struct {
1383	1421	.features = featureSet(&[_]Feature{
1384	1422	.back_off_barrier,
1385	1423	.dl_insts,
	1424	.dot10_insts,
1386	1425	.dot1_insts,
1387	1426	.dot2_insts,
1388	1427	.dot5_insts,
...	...	@@ -1394,7 +1433,6 @@ pub const cpu = struct {
1394	1433	.gfx10_b_encoding,
1395	1434	.ldsbankcount32,
1396	1435	.nsa_encoding,
1397		.nsa_max_size_13,
1398	1436	.shader_cycles_register,
1399	1437	.wavefrontsize32,
1400	1438	}),
...	...	@@ -1405,6 +1443,7 @@ pub const cpu = struct {
1405	1443	.features = featureSet(&[_]Feature{
1406	1444	.back_off_barrier,
1407	1445	.dl_insts,
	1446	.dot10_insts,
1408	1447	.dot1_insts,
1409	1448	.dot2_insts,
1410	1449	.dot5_insts,
...	...	@@ -1416,7 +1455,6 @@ pub const cpu = struct {
1416	1455	.gfx10_b_encoding,
1417	1456	.ldsbankcount32,
1418	1457	.nsa_encoding,
1419		.nsa_max_size_13,
1420	1458	.shader_cycles_register,
1421	1459	.wavefrontsize32,
1422	1460	}),
...	...	@@ -1429,6 +1467,7 @@ pub const cpu = struct {
1429	1467	.atomic_fadd_no_rtn_insts,
1430	1468	.atomic_fadd_rtn_insts,
1431	1469	.dl_insts,
	1470	.dot10_insts,
1432	1471	.dot5_insts,
1433	1472	.dot7_insts,
1434	1473	.dot8_insts,
...	...	@@ -1440,8 +1479,8 @@ pub const cpu = struct {
1440	1479	.ldsbankcount32,
1441	1480	.mad_intra_fwd_bug,
1442	1481	.nsa_encoding,
1443		.nsa_max_size_5,
1444	1482	.packed_tid,
	1483	.partial_nsa_encoding,
1445	1484	.shader_cycles_register,
1446	1485	.user_sgpr_init16_bug,
1447	1486	.valu_trans_use_hazard,
...	...	@@ -1457,6 +1496,7 @@ pub const cpu = struct {
1457	1496	.atomic_fadd_no_rtn_insts,
1458	1497	.atomic_fadd_rtn_insts,
1459	1498	.dl_insts,
	1499	.dot10_insts,
1460	1500	.dot5_insts,
1461	1501	.dot7_insts,
1462	1502	.dot8_insts,
...	...	@@ -1468,8 +1508,8 @@ pub const cpu = struct {
1468	1508	.ldsbankcount32,
1469	1509	.mad_intra_fwd_bug,
1470	1510	.nsa_encoding,
1471		.nsa_max_size_5,
1472	1511	.packed_tid,
	1512	.partial_nsa_encoding,
1473	1513	.shader_cycles_register,
1474	1514	.valu_trans_use_hazard,
1475	1515	.vcmpx_permlane_hazard,
...	...	@@ -1484,6 +1524,7 @@ pub const cpu = struct {
1484	1524	.atomic_fadd_no_rtn_insts,
1485	1525	.atomic_fadd_rtn_insts,
1486	1526	.dl_insts,
	1527	.dot10_insts,
1487	1528	.dot5_insts,
1488	1529	.dot7_insts,
1489	1530	.dot8_insts,
...	...	@@ -1494,8 +1535,8 @@ pub const cpu = struct {
1494	1535	.ldsbankcount32,
1495	1536	.mad_intra_fwd_bug,
1496	1537	.nsa_encoding,
1497		.nsa_max_size_5,
1498	1538	.packed_tid,
	1539	.partial_nsa_encoding,
1499	1540	.shader_cycles_register,
1500	1541	.user_sgpr_init16_bug,
1501	1542	.valu_trans_use_hazard,
...	...	@@ -1511,6 +1552,7 @@ pub const cpu = struct {
1511	1552	.atomic_fadd_no_rtn_insts,
1512	1553	.atomic_fadd_rtn_insts,
1513	1554	.dl_insts,
	1555	.dot10_insts,
1514	1556	.dot5_insts,
1515	1557	.dot7_insts,
1516	1558	.dot8_insts,
...	...	@@ -1521,14 +1563,67 @@ pub const cpu = struct {
1521	1563	.ldsbankcount32,
1522	1564	.mad_intra_fwd_bug,
1523	1565	.nsa_encoding,
1524		.nsa_max_size_5,
1525	1566	.packed_tid,
	1567	.partial_nsa_encoding,
1526	1568	.shader_cycles_register,
1527	1569	.valu_trans_use_hazard,
1528	1570	.vcmpx_permlane_hazard,
1529	1571	.wavefrontsize32,
1530	1572	}),
1531	1573	};
	1574	pub const gfx1150 = CpuModel{
	1575	.name = "gfx1150",
	1576	.llvm_name = "gfx1150",
	1577	.features = featureSet(&[_]Feature{
	1578	.architected_flat_scratch,
	1579	.atomic_fadd_no_rtn_insts,
	1580	.atomic_fadd_rtn_insts,
	1581	.dl_insts,
	1582	.dot10_insts,
	1583	.dot5_insts,
	1584	.dot7_insts,
	1585	.dot8_insts,
	1586	.dot9_insts,
	1587	.flat_atomic_fadd_f32_inst,
	1588	.gfx11,
	1589	.image_insts,
	1590	.ldsbankcount32,
	1591	.mad_intra_fwd_bug,
	1592	.nsa_encoding,
	1593	.packed_tid,
	1594	.partial_nsa_encoding,
	1595	.shader_cycles_register,
	1596	.vcmpx_permlane_hazard,
	1597	.wavefrontsize32,
	1598	}),
	1599	};
	1600	pub const gfx1151 = CpuModel{
	1601	.name = "gfx1151",
	1602	.llvm_name = "gfx1151",
	1603	.features = featureSet(&[_]Feature{
	1604	.architected_flat_scratch,
	1605	.atomic_fadd_no_rtn_insts,
	1606	.atomic_fadd_rtn_insts,
	1607	.dl_insts,
	1608	.dot10_insts,
	1609	.dot5_insts,
	1610	.dot7_insts,
	1611	.dot8_insts,
	1612	.dot9_insts,
	1613	.flat_atomic_fadd_f32_inst,
	1614	.gfx11,
	1615	.gfx11_full_vgprs,
	1616	.image_insts,
	1617	.ldsbankcount32,
	1618	.mad_intra_fwd_bug,
	1619	.nsa_encoding,
	1620	.packed_tid,
	1621	.partial_nsa_encoding,
	1622	.shader_cycles_register,
	1623	.vcmpx_permlane_hazard,
	1624	.wavefrontsize32,
	1625	}),
	1626	};
1532	1627	pub const gfx600 = CpuModel{
1533	1628	.name = "gfx600",
1534	1629	.llvm_name = "gfx600",
...	...	@@ -1702,6 +1797,7 @@ pub const cpu = struct {
1702	1797	.llvm_name = "gfx906",
1703	1798	.features = featureSet(&[_]Feature{
1704	1799	.dl_insts,
	1800	.dot10_insts,
1705	1801	.dot1_insts,
1706	1802	.dot2_insts,
1707	1803	.dot7_insts,
...	...	@@ -1721,9 +1817,10 @@ pub const cpu = struct {
1721	1817	.name = "gfx908",
1722	1818	.llvm_name = "gfx908",
1723	1819	.features = featureSet(&[_]Feature{
	1820	.atomic_buffer_global_pk_add_f16_no_rtn_insts,
1724	1821	.atomic_fadd_no_rtn_insts,
1725		.atomic_pk_fadd_no_rtn_insts,
1726	1822	.dl_insts,
	1823	.dot10_insts,
1727	1824	.dot1_insts,
1728	1825	.dot2_insts,
1729	1826	.dot3_insts,
...	...	@@ -1764,11 +1861,12 @@ pub const cpu = struct {
1764	1861	.name = "gfx90a",
1765	1862	.llvm_name = "gfx90a",
1766	1863	.features = featureSet(&[_]Feature{
	1864	.atomic_buffer_global_pk_add_f16_insts,
1767	1865	.atomic_fadd_no_rtn_insts,
1768	1866	.atomic_fadd_rtn_insts,
1769		.atomic_pk_fadd_no_rtn_insts,
1770	1867	.back_off_barrier,
1771	1868	.dl_insts,
	1869	.dot10_insts,
1772	1870	.dot1_insts,
1773	1871	.dot2_insts,
1774	1872	.dot3_insts,
...	...	@@ -1811,11 +1909,93 @@ pub const cpu = struct {
1811	1909	.llvm_name = "gfx940",
1812	1910	.features = featureSet(&[_]Feature{
1813	1911	.architected_flat_scratch,
	1912	.atomic_buffer_global_pk_add_f16_insts,
	1913	.atomic_ds_pk_add_16_insts,
	1914	.atomic_fadd_no_rtn_insts,
	1915	.atomic_fadd_rtn_insts,
	1916	.atomic_flat_pk_add_16_insts,
	1917	.atomic_global_pk_add_bf16_inst,
	1918	.back_off_barrier,
	1919	.dl_insts,
	1920	.dot10_insts,
	1921	.dot1_insts,
	1922	.dot2_insts,
	1923	.dot3_insts,
	1924	.dot4_insts,
	1925	.dot5_insts,
	1926	.dot6_insts,
	1927	.dot7_insts,
	1928	.dpp_64bit,
	1929	.flat_atomic_fadd_f32_inst,
	1930	.fma_mix_insts,
	1931	.fmacf64_inst,
	1932	.force_store_sc0_sc1,
	1933	.fp8_insts,
	1934	.full_rate_64_ops,
	1935	.gfx9,
	1936	.gfx90a_insts,
	1937	.gfx940_insts,
	1938	.ldsbankcount32,
	1939	.mai_insts,
	1940	.packed_fp32_ops,
	1941	.packed_tid,
	1942	.pk_fmac_f16_inst,
	1943	.sramecc_support,
	1944	}),
	1945	};
	1946	pub const gfx941 = CpuModel{
	1947	.name = "gfx941",
	1948	.llvm_name = "gfx941",
	1949	.features = featureSet(&[_]Feature{
	1950	.architected_flat_scratch,
	1951	.atomic_buffer_global_pk_add_f16_insts,
	1952	.atomic_ds_pk_add_16_insts,
	1953	.atomic_fadd_no_rtn_insts,
	1954	.atomic_fadd_rtn_insts,
	1955	.atomic_flat_pk_add_16_insts,
	1956	.atomic_global_pk_add_bf16_inst,
	1957	.back_off_barrier,
	1958	.dl_insts,
	1959	.dot10_insts,
	1960	.dot1_insts,
	1961	.dot2_insts,
	1962	.dot3_insts,
	1963	.dot4_insts,
	1964	.dot5_insts,
	1965	.dot6_insts,
	1966	.dot7_insts,
	1967	.dpp_64bit,
	1968	.flat_atomic_fadd_f32_inst,
	1969	.fma_mix_insts,
	1970	.fmacf64_inst,
	1971	.force_store_sc0_sc1,
	1972	.fp8_insts,
	1973	.full_rate_64_ops,
	1974	.gfx9,
	1975	.gfx90a_insts,
	1976	.gfx940_insts,
	1977	.ldsbankcount32,
	1978	.mai_insts,
	1979	.packed_fp32_ops,
	1980	.packed_tid,
	1981	.pk_fmac_f16_inst,
	1982	.sramecc_support,
	1983	}),
	1984	};
	1985	pub const gfx942 = CpuModel{
	1986	.name = "gfx942",
	1987	.llvm_name = "gfx942",
	1988	.features = featureSet(&[_]Feature{
	1989	.architected_flat_scratch,
	1990	.atomic_buffer_global_pk_add_f16_insts,
	1991	.atomic_ds_pk_add_16_insts,
1814	1992	.atomic_fadd_no_rtn_insts,
1815	1993	.atomic_fadd_rtn_insts,
1816		.atomic_pk_fadd_no_rtn_insts,
	1994	.atomic_flat_pk_add_16_insts,
	1995	.atomic_global_pk_add_bf16_inst,
1817	1996	.back_off_barrier,
1818	1997	.dl_insts,
	1998	.dot10_insts,
1819	1999	.dot1_insts,
1820	2000	.dot2_insts,
1821	2001	.dot3_insts,

lib/std/target/arm.zig+16-4

...	...	@@ -122,7 +122,9 @@ pub const Feature = enum {
122	122	r4,
123	123	ras,
124	124	rclass,
125		read_tp_hard,
	125	read_tp_tpidrprw,
	126	read_tp_tpidruro,
	127	read_tp_tpidrurw,
126	128	reserve_r9,
127	129	ret_addr_stack,
128	130	sb,
...	...	@@ -949,9 +951,19 @@ pub const all_features = blk: {
949	951	.description = "Is realtime profile ('R' series)",
950	952	.dependencies = featureSet(&[_]Feature{}),
951	953	};
952		result[@intFromEnum(Feature.read_tp_hard)] = .{
953		.llvm_name = "read-tp-hard",
954		.description = "Reading thread pointer from register",
	954	result[@intFromEnum(Feature.read_tp_tpidrprw)] = .{
	955	.llvm_name = "read-tp-tpidrprw",
	956	.description = "Reading thread pointer from TPIDRPRW register",
	957	.dependencies = featureSet(&[_]Feature{}),
	958	};
	959	result[@intFromEnum(Feature.read_tp_tpidruro)] = .{
	960	.llvm_name = "read-tp-tpidruro",
	961	.description = "Reading thread pointer from TPIDRURO register",
	962	.dependencies = featureSet(&[_]Feature{}),
	963	};
	964	result[@intFromEnum(Feature.read_tp_tpidrurw)] = .{
	965	.llvm_name = "read-tp-tpidrurw",
	966	.description = "Reading thread pointer from TPIDRURW register",
955	967	.dependencies = featureSet(&[_]Feature{}),
956	968	};
957	969	result[@intFromEnum(Feature.reserve_r9)] = .{

lib/std/target/avr.zig+8-9

...	...	@@ -25,12 +25,12 @@ pub const Feature = enum {
25	25	elpmx,
26	26	ijmpcall,
27	27	jmpcall,
	28	lowbytefirst,
28	29	lpm,
29	30	lpmx,
30	31	memmappedregs,
31	32	movw,
32	33	mul,
33		progmem,
34	34	rmw,
35	35	smallstack,
36	36	special,
...	...	@@ -69,7 +69,6 @@ pub const all_features = blk: {
69	69	.avr0,
70	70	.lpm,
71	71	.memmappedregs,
72		.progmem,
73	72	}),
74	73	};
75	74	result[@intFromEnum(Feature.avr2)] = .{
...	...	@@ -207,6 +206,11 @@ pub const all_features = blk: {
207	206	.description = "The device supports the `JMP` and `CALL` instructions",
208	207	.dependencies = featureSet(&[_]Feature{}),
209	208	};
	209	result[@intFromEnum(Feature.lowbytefirst)] = .{
	210	.llvm_name = "lowbytefirst",
	211	.description = "Do the low byte first when writing a 16-bit port or storing a 16-bit word",
	212	.dependencies = featureSet(&[_]Feature{}),
	213	};
210	214	result[@intFromEnum(Feature.lpm)] = .{
211	215	.llvm_name = "lpm",
212	216	.description = "The device supports the `LPM` instruction",
...	...	@@ -232,11 +236,6 @@ pub const all_features = blk: {
232	236	.description = "The device supports the multiplication instructions",
233	237	.dependencies = featureSet(&[_]Feature{}),
234	238	};
235		result[@intFromEnum(Feature.progmem)] = .{
236		.llvm_name = "progmem",
237		.description = "The device has a separate flash namespace",
238		.dependencies = featureSet(&[_]Feature{}),
239		};
240	239	result[@intFromEnum(Feature.rmw)] = .{
241	240	.llvm_name = "rmw",
242	241	.description = "The device supports the read-write-modify instructions: XCH, LAS, LAC, LAT",
...	...	@@ -303,11 +302,11 @@ pub const all_features = blk: {
303	302	.elpmx,
304	303	.ijmpcall,
305	304	.jmpcall,
	305	.lowbytefirst,
306	306	.lpm,
307	307	.lpmx,
308	308	.movw,
309	309	.mul,
310		.progmem,
311	310	.spm,
312	311	.spmx,
313	312	.sram,
...	...	@@ -322,11 +321,11 @@ pub const all_features = blk: {
322	321	.@"break",
323	322	.ijmpcall,
324	323	.jmpcall,
	324	.lowbytefirst,
325	325	.lpm,
326	326	.lpmx,
327	327	.movw,
328	328	.mul,
329		.progmem,
330	329	.sram,
331	330	}),
332	331	};

lib/std/target/bpf.zig+3-1

...	...	@@ -66,6 +66,8 @@ pub const cpu = struct {
66	66	pub const v3 = CpuModel{
67	67	.name = "v3",
68	68	.llvm_name = "v3",
69		.features = featureSet(&[_]Feature{}),
	69	.features = featureSet(&[_]Feature{
	70	.alu32,
	71	}),
70	72	};
71	73	};

lib/std/target/csky.zig+10-10

...	...	@@ -214,7 +214,7 @@ pub const all_features = blk: {
214	214	};
215	215	result[@intFromEnum(Feature.dsp_silan)] = .{
216	216	.llvm_name = "dsp_silan",
217		.description = "Enable DSP Silan instructions",
	217	.description = "Enable DSP Silan instrutions",
218	218	.dependencies = featureSet(&[_]Feature{}),
219	219	};
220	220	result[@intFromEnum(Feature.dspe60)] = .{
...	...	@@ -224,7 +224,7 @@ pub const all_features = blk: {
224	224	};
225	225	result[@intFromEnum(Feature.dspv2)] = .{
226	226	.llvm_name = "dspv2",
227		.description = "Enable DSP V2.0 instructions",
	227	.description = "Enable DSP V2.0 instrutions",
228	228	.dependencies = featureSet(&[_]Feature{}),
229	229	};
230	230	result[@intFromEnum(Feature.e1)] = .{
...	...	@@ -243,7 +243,7 @@ pub const all_features = blk: {
243	243	};
244	244	result[@intFromEnum(Feature.edsp)] = .{
245	245	.llvm_name = "edsp",
246		.description = "Enable DSP instructions",
	246	.description = "Enable DSP instrutions",
247	247	.dependencies = featureSet(&[_]Feature{}),
248	248	};
249	249	result[@intFromEnum(Feature.elrw)] = .{
...	...	@@ -298,12 +298,12 @@ pub const all_features = blk: {
298	298	};
299	299	result[@intFromEnum(Feature.fpuv3_hf)] = .{
300	300	.llvm_name = "fpuv3_hf",
301		.description = "Enable FPUv3 harf precision operate instructions",
	301	.description = "Enable FPUv3 half precision operate instructions",
302	302	.dependencies = featureSet(&[_]Feature{}),
303	303	};
304	304	result[@intFromEnum(Feature.fpuv3_hi)] = .{
305	305	.llvm_name = "fpuv3_hi",
306		.description = "Enable FPUv3 harf word converting instructions",
	306	.description = "Enable FPUv3 half word converting instructions",
307	307	.dependencies = featureSet(&[_]Feature{}),
308	308	};
309	309	result[@intFromEnum(Feature.fpuv3_sf)] = .{
...	...	@@ -333,12 +333,12 @@ pub const all_features = blk: {
333	333	};
334	334	result[@intFromEnum(Feature.hwdiv)] = .{
335	335	.llvm_name = "hwdiv",
336		.description = "Enable divide instructions",
	336	.description = "Enable divide instrutions",
337	337	.dependencies = featureSet(&[_]Feature{}),
338	338	};
339	339	result[@intFromEnum(Feature.istack)] = .{
340	340	.llvm_name = "istack",
341		.description = "Enable interrupt attribute",
	341	.description = "Enable interrput attribute",
342	342	.dependencies = featureSet(&[_]Feature{}),
343	343	};
344	344	result[@intFromEnum(Feature.java)] = .{
...	...	@@ -362,7 +362,7 @@ pub const all_features = blk: {
362	362	};
363	363	result[@intFromEnum(Feature.multiple_stld)] = .{
364	364	.llvm_name = "multiple_stld",
365		.description = "Enable multiple load/store instructions",
	365	.description = "Enable multiple load/store instrutions",
366	366	.dependencies = featureSet(&[_]Feature{}),
367	367	};
368	368	result[@intFromEnum(Feature.nvic)] = .{
...	...	@@ -372,7 +372,7 @@ pub const all_features = blk: {
372	372	};
373	373	result[@intFromEnum(Feature.pushpop)] = .{
374	374	.llvm_name = "pushpop",
375		.description = "Enable push/pop instructions",
	375	.description = "Enable push/pop instrutions",
376	376	.dependencies = featureSet(&[_]Feature{}),
377	377	};
378	378	result[@intFromEnum(Feature.smart)] = .{
...	...	@@ -3079,7 +3079,7 @@ pub const cpu = struct {
3079	3079	.btst16,
3080	3080	}),
3081	3081	};
3082		pub const @"i805" = CpuModel{
	3082	pub const i805 = CpuModel{
3083	3083	.name = "i805",
3084	3084	.llvm_name = "i805",
3085	3085	.features = featureSet(&[_]Feature{

lib/std/target/loongarch.zig+17

...	...	@@ -16,6 +16,7 @@ pub const Feature = enum {
16	16	lbt,
17	17	lsx,
18	18	lvz,
	19	ual,
19	20	};
20	21
21	22	pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
...	...	@@ -88,6 +89,11 @@ pub const all_features = blk: {
88	89	.description = "'LVZ' (Loongson Virtualization Extension)",
89	90	.dependencies = featureSet(&[_]Feature{}),
90	91	};
	92	result[@intFromEnum(Feature.ual)] = .{
	93	.llvm_name = "ual",
	94	.description = "Allow memory accesses to be unaligned",
	95	.dependencies = featureSet(&[_]Feature{}),
	96	};
91	97	const ti = @typeInfo(Feature);
92	98	for (&result, 0..) \|*elem, i\| {
93	99	elem.index = i;
...	...	@@ -114,6 +120,7 @@ pub const cpu = struct {
114	120	.llvm_name = "generic-la64",
115	121	.features = featureSet(&[_]Feature{
116	122	.@"64bit",
	123	.ual,
117	124	}),
118	125	};
119	126	pub const la464 = CpuModel{
...	...	@@ -124,6 +131,16 @@ pub const cpu = struct {
124	131	.lasx,
125	132	.lbt,
126	133	.lvz,
	134	.ual,
	135	}),
	136	};
	137	pub const loongarch64 = CpuModel{
	138	.name = "loongarch64",
	139	.llvm_name = "loongarch64",
	140	.features = featureSet(&[_]Feature{
	141	.@"64bit",
	142	.d,
	143	.ual,
127	144	}),
128	145	};
129	146	};

lib/std/target/m68k.zig+15

...	...	@@ -11,6 +11,8 @@ pub const Feature = enum {
11	11	isa_68030,
12	12	isa_68040,
13	13	isa_68060,
	14	isa_68881,
	15	isa_68882,
14	16	reserve_a0,
15	17	reserve_a1,
16	18	reserve_a2,
...	...	@@ -68,6 +70,7 @@ pub const all_features = blk: {
68	70	.description = "Is M68040 ISA supported",
69	71	.dependencies = featureSet(&[_]Feature{
70	72	.isa_68030,
	73	.isa_68882,
71	74	}),
72	75	};
73	76	result[@intFromEnum(Feature.isa_68060)] = .{
...	...	@@ -77,6 +80,18 @@ pub const all_features = blk: {
77	80	.isa_68040,
78	81	}),
79	82	};
	83	result[@intFromEnum(Feature.isa_68881)] = .{
	84	.llvm_name = "isa-68881",
	85	.description = "Is M68881 (FPU) ISA supported",
	86	.dependencies = featureSet(&[_]Feature{}),
	87	};
	88	result[@intFromEnum(Feature.isa_68882)] = .{
	89	.llvm_name = "isa-68882",
	90	.description = "Is M68882 (FPU) ISA supported",
	91	.dependencies = featureSet(&[_]Feature{
	92	.isa_68881,
	93	}),
	94	};
80	95	result[@intFromEnum(Feature.reserve_a0)] = .{
81	96	.llvm_name = "reserve-a0",
82	97	.description = "Reserve A0 register",

lib/std/target/nvptx.zig+66-40

...	...	@@ -25,6 +25,8 @@ pub const Feature = enum {
25	25	ptx76,
26	26	ptx77,
27	27	ptx78,
	28	ptx80,
	29	ptx81,
28	30	sm_20,
29	31	sm_21,
30	32	sm_30,
...	...	@@ -45,6 +47,7 @@ pub const Feature = enum {
45	47	sm_87,
46	48	sm_89,
47	49	sm_90,
	50	sm_90,
48	51	};
49	52
50	53	pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
...	...	@@ -58,202 +61,217 @@ pub const all_features = blk: {
58	61	var result: [len]CpuFeature = undefined;
59	62	result[@intFromEnum(Feature.ptx32)] = .{
60	63	.llvm_name = "ptx32",
61		.description = "Use PTX version 3.2",
	64	.description = "Use PTX version 32",
62	65	.dependencies = featureSet(&[_]Feature{}),
63	66	};
64	67	result[@intFromEnum(Feature.ptx40)] = .{
65	68	.llvm_name = "ptx40",
66		.description = "Use PTX version 4.0",
	69	.description = "Use PTX version 40",
67	70	.dependencies = featureSet(&[_]Feature{}),
68	71	};
69	72	result[@intFromEnum(Feature.ptx41)] = .{
70	73	.llvm_name = "ptx41",
71		.description = "Use PTX version 4.1",
	74	.description = "Use PTX version 41",
72	75	.dependencies = featureSet(&[_]Feature{}),
73	76	};
74	77	result[@intFromEnum(Feature.ptx42)] = .{
75	78	.llvm_name = "ptx42",
76		.description = "Use PTX version 4.2",
	79	.description = "Use PTX version 42",
77	80	.dependencies = featureSet(&[_]Feature{}),
78	81	};
79	82	result[@intFromEnum(Feature.ptx43)] = .{
80	83	.llvm_name = "ptx43",
81		.description = "Use PTX version 4.3",
	84	.description = "Use PTX version 43",
82	85	.dependencies = featureSet(&[_]Feature{}),
83	86	};
84	87	result[@intFromEnum(Feature.ptx50)] = .{
85	88	.llvm_name = "ptx50",
86		.description = "Use PTX version 5.0",
	89	.description = "Use PTX version 50",
87	90	.dependencies = featureSet(&[_]Feature{}),
88	91	};
89	92	result[@intFromEnum(Feature.ptx60)] = .{
90	93	.llvm_name = "ptx60",
91		.description = "Use PTX version 6.0",
	94	.description = "Use PTX version 60",
92	95	.dependencies = featureSet(&[_]Feature{}),
93	96	};
94	97	result[@intFromEnum(Feature.ptx61)] = .{
95	98	.llvm_name = "ptx61",
96		.description = "Use PTX version 6.1",
	99	.description = "Use PTX version 61",
97	100	.dependencies = featureSet(&[_]Feature{}),
98	101	};
99	102	result[@intFromEnum(Feature.ptx63)] = .{
100	103	.llvm_name = "ptx63",
101		.description = "Use PTX version 6.3",
	104	.description = "Use PTX version 63",
102	105	.dependencies = featureSet(&[_]Feature{}),
103	106	};
104	107	result[@intFromEnum(Feature.ptx64)] = .{
105	108	.llvm_name = "ptx64",
106		.description = "Use PTX version 6.4",
	109	.description = "Use PTX version 64",
107	110	.dependencies = featureSet(&[_]Feature{}),
108	111	};
109	112	result[@intFromEnum(Feature.ptx65)] = .{
110	113	.llvm_name = "ptx65",
111		.description = "Use PTX version 6.5",
	114	.description = "Use PTX version 65",
112	115	.dependencies = featureSet(&[_]Feature{}),
113	116	};
114	117	result[@intFromEnum(Feature.ptx70)] = .{
115	118	.llvm_name = "ptx70",
116		.description = "Use PTX version 7.0",
	119	.description = "Use PTX version 70",
117	120	.dependencies = featureSet(&[_]Feature{}),
118	121	};
119	122	result[@intFromEnum(Feature.ptx71)] = .{
120	123	.llvm_name = "ptx71",
121		.description = "Use PTX version 7.1",
	124	.description = "Use PTX version 71",
122	125	.dependencies = featureSet(&[_]Feature{}),
123	126	};
124	127	result[@intFromEnum(Feature.ptx72)] = .{
125	128	.llvm_name = "ptx72",
126		.description = "Use PTX version 7.2",
	129	.description = "Use PTX version 72",
127	130	.dependencies = featureSet(&[_]Feature{}),
128	131	};
129	132	result[@intFromEnum(Feature.ptx73)] = .{
130	133	.llvm_name = "ptx73",
131		.description = "Use PTX version 7.3",
	134	.description = "Use PTX version 73",
132	135	.dependencies = featureSet(&[_]Feature{}),
133	136	};
134	137	result[@intFromEnum(Feature.ptx74)] = .{
135	138	.llvm_name = "ptx74",
136		.description = "Use PTX version 7.4",
	139	.description = "Use PTX version 74",
137	140	.dependencies = featureSet(&[_]Feature{}),
138	141	};
139	142	result[@intFromEnum(Feature.ptx75)] = .{
140	143	.llvm_name = "ptx75",
141		.description = "Use PTX version 7.5",
	144	.description = "Use PTX version 75",
142	145	.dependencies = featureSet(&[_]Feature{}),
143	146	};
144	147	result[@intFromEnum(Feature.ptx76)] = .{
145	148	.llvm_name = "ptx76",
146		.description = "Use PTX version 7.6",
	149	.description = "Use PTX version 76",
147	150	.dependencies = featureSet(&[_]Feature{}),
148	151	};
149	152	result[@intFromEnum(Feature.ptx77)] = .{
150	153	.llvm_name = "ptx77",
151		.description = "Use PTX version 7.7",
	154	.description = "Use PTX version 77",
152	155	.dependencies = featureSet(&[_]Feature{}),
153	156	};
154	157	result[@intFromEnum(Feature.ptx78)] = .{
155	158	.llvm_name = "ptx78",
156		.description = "Use PTX version 7.8",
	159	.description = "Use PTX version 78",
	160	.dependencies = featureSet(&[_]Feature{}),
	161	};
	162	result[@intFromEnum(Feature.ptx80)] = .{
	163	.llvm_name = "ptx80",
	164	.description = "Use PTX version 80",
	165	.dependencies = featureSet(&[_]Feature{}),
	166	};
	167	result[@intFromEnum(Feature.ptx81)] = .{
	168	.llvm_name = "ptx81",
	169	.description = "Use PTX version 81",
157	170	.dependencies = featureSet(&[_]Feature{}),
158	171	};
159	172	result[@intFromEnum(Feature.sm_20)] = .{
160	173	.llvm_name = "sm_20",
161		.description = "Target SM 2.0",
	174	.description = "Target SM 20",
162	175	.dependencies = featureSet(&[_]Feature{}),
163	176	};
164	177	result[@intFromEnum(Feature.sm_21)] = .{
165	178	.llvm_name = "sm_21",
166		.description = "Target SM 2.1",
	179	.description = "Target SM 21",
167	180	.dependencies = featureSet(&[_]Feature{}),
168	181	};
169	182	result[@intFromEnum(Feature.sm_30)] = .{
170	183	.llvm_name = "sm_30",
171		.description = "Target SM 3.0",
	184	.description = "Target SM 30",
172	185	.dependencies = featureSet(&[_]Feature{}),
173	186	};
174	187	result[@intFromEnum(Feature.sm_32)] = .{
175	188	.llvm_name = "sm_32",
176		.description = "Target SM 3.2",
	189	.description = "Target SM 32",
177	190	.dependencies = featureSet(&[_]Feature{}),
178	191	};
179	192	result[@intFromEnum(Feature.sm_35)] = .{
180	193	.llvm_name = "sm_35",
181		.description = "Target SM 3.5",
	194	.description = "Target SM 35",
182	195	.dependencies = featureSet(&[_]Feature{}),
183	196	};
184	197	result[@intFromEnum(Feature.sm_37)] = .{
185	198	.llvm_name = "sm_37",
186		.description = "Target SM 3.7",
	199	.description = "Target SM 37",
187	200	.dependencies = featureSet(&[_]Feature{}),
188	201	};
189	202	result[@intFromEnum(Feature.sm_50)] = .{
190	203	.llvm_name = "sm_50",
191		.description = "Target SM 5.0",
	204	.description = "Target SM 50",
192	205	.dependencies = featureSet(&[_]Feature{}),
193	206	};
194	207	result[@intFromEnum(Feature.sm_52)] = .{
195	208	.llvm_name = "sm_52",
196		.description = "Target SM 5.2",
	209	.description = "Target SM 52",
197	210	.dependencies = featureSet(&[_]Feature{}),
198	211	};
199	212	result[@intFromEnum(Feature.sm_53)] = .{
200	213	.llvm_name = "sm_53",
201		.description = "Target SM 5.3",
	214	.description = "Target SM 53",
202	215	.dependencies = featureSet(&[_]Feature{}),
203	216	};
204	217	result[@intFromEnum(Feature.sm_60)] = .{
205	218	.llvm_name = "sm_60",
206		.description = "Target SM 6.0",
	219	.description = "Target SM 60",
207	220	.dependencies = featureSet(&[_]Feature{}),
208	221	};
209	222	result[@intFromEnum(Feature.sm_61)] = .{
210	223	.llvm_name = "sm_61",
211		.description = "Target SM 6.1",
	224	.description = "Target SM 61",
212	225	.dependencies = featureSet(&[_]Feature{}),
213	226	};
214	227	result[@intFromEnum(Feature.sm_62)] = .{
215	228	.llvm_name = "sm_62",
216		.description = "Target SM 6.2",
	229	.description = "Target SM 62",
217	230	.dependencies = featureSet(&[_]Feature{}),
218	231	};
219	232	result[@intFromEnum(Feature.sm_70)] = .{
220	233	.llvm_name = "sm_70",
221		.description = "Target SM 7.0",
	234	.description = "Target SM 70",
222	235	.dependencies = featureSet(&[_]Feature{}),
223	236	};
224	237	result[@intFromEnum(Feature.sm_72)] = .{
225	238	.llvm_name = "sm_72",
226		.description = "Target SM 7.2",
	239	.description = "Target SM 72",
227	240	.dependencies = featureSet(&[_]Feature{}),
228	241	};
229	242	result[@intFromEnum(Feature.sm_75)] = .{
230	243	.llvm_name = "sm_75",
231		.description = "Target SM 7.5",
	244	.description = "Target SM 75",
232	245	.dependencies = featureSet(&[_]Feature{}),
233	246	};
234	247	result[@intFromEnum(Feature.sm_80)] = .{
235	248	.llvm_name = "sm_80",
236		.description = "Target SM 8.0",
	249	.description = "Target SM 80",
237	250	.dependencies = featureSet(&[_]Feature{}),
238	251	};
239	252	result[@intFromEnum(Feature.sm_86)] = .{
240	253	.llvm_name = "sm_86",
241		.description = "Target SM 8.6",
	254	.description = "Target SM 86",
242	255	.dependencies = featureSet(&[_]Feature{}),
243	256	};
244	257	result[@intFromEnum(Feature.sm_87)] = .{
245	258	.llvm_name = "sm_87",
246		.description = "Target SM 8.7",
	259	.description = "Target SM 87",
247	260	.dependencies = featureSet(&[_]Feature{}),
248	261	};
249	262	result[@intFromEnum(Feature.sm_89)] = .{
250	263	.llvm_name = "sm_89",
251		.description = "Target SM 8.9",
	264	.description = "Target SM 89",
252	265	.dependencies = featureSet(&[_]Feature{}),
253	266	};
254	267	result[@intFromEnum(Feature.sm_90)] = .{
255	268	.llvm_name = "sm_90",
256		.description = "Target SM 9.0",
	269	.description = "Target SM 90",
	270	.dependencies = featureSet(&[_]Feature{}),
	271	};
	272	result[@intFromEnum(Feature.sm_90)] = .{
	273	.llvm_name = "sm_90",
	274	.description = "Target SM 90",
257	275	.dependencies = featureSet(&[_]Feature{}),
258	276	};
259	277	const ti = @typeInfo(Feature);
...	...	@@ -424,4 +442,12 @@ pub const cpu = struct {
424	442	.sm_90,
425	443	}),
426	444	};
	445	pub const sm_90a = CpuModel{
	446	.name = "sm_90a",
	447	.llvm_name = "sm_90a",
	448	.features = featureSet(&[_]Feature{
	449	.ptx80,
	450	.sm_90,
	451	}),
	452	};
427	453	};

lib/std/target/riscv.zig+401-26

...	...	@@ -10,14 +10,33 @@ pub const Feature = enum {
10	10	a,
11	11	c,
12	12	d,
	13	dlen_factor_2,
13	14	e,
14		experimental_zawrs,
15		experimental_zca,
16		experimental_zcd,
17		experimental_zcf,
	15	experimental_smaia,
	16	experimental_ssaia,
	17	experimental_zacas,
	18	experimental_zfa,
	19	experimental_zfbfmin,
	20	experimental_zicond,
18	21	experimental_zihintntl,
19	22	experimental_ztso,
20		experimental_zvfh,
	23	experimental_zvbb,
	24	experimental_zvbc,
	25	experimental_zvfbfmin,
	26	experimental_zvfbfwma,
	27	experimental_zvkg,
	28	experimental_zvkn,
	29	experimental_zvknc,
	30	experimental_zvkned,
	31	experimental_zvkng,
	32	experimental_zvknha,
	33	experimental_zvknhb,
	34	experimental_zvks,
	35	experimental_zvksc,
	36	experimental_zvksed,
	37	experimental_zvksg,
	38	experimental_zvksh,
	39	experimental_zvkt,
21	40	f,
22	41	forced_atomics,
23	42	h,
...	...	@@ -59,15 +78,32 @@ pub const Feature = enum {
59	78	reserve_x8,
60	79	reserve_x9,
61	80	save_restore,
	81	seq_cst_trailing_fence,
62	82	short_forward_branch_opt,
63	83	svinval,
64	84	svnapot,
65	85	svpbmt,
66	86	tagged_globals,
67	87	unaligned_scalar_mem,
	88	unaligned_vector_mem,
68	89	v,
	90	xcvbitmanip,
	91	xcvmac,
	92	xsfcie,
	93	xsfvcp,
	94	xtheadba,
	95	xtheadbb,
	96	xtheadbs,
	97	xtheadcmo,
	98	xtheadcondmov,
	99	xtheadfmemidx,
	100	xtheadmac,
	101	xtheadmemidx,
	102	xtheadmempair,
	103	xtheadsync,
69	104	xtheadvdot,
70	105	xventanacondops,
	106	zawrs,
71	107	zba,
72	108	zbb,
73	109	zbc,
...	...	@@ -75,6 +111,13 @@ pub const Feature = enum {
75	111	zbkc,
76	112	zbkx,
77	113	zbs,
	114	zca,
	115	zcb,
	116	zcd,
	117	zce,
	118	zcf,
	119	zcmp,
	120	zcmt,
78	121	zdinx,
79	122	zfh,
80	123	zfhmin,
...	...	@@ -84,7 +127,11 @@ pub const Feature = enum {
84	127	zicbom,
85	128	zicbop,
86	129	zicboz,
	130	zicntr,
	131	zicsr,
	132	zifencei,
87	133	zihintpause,
	134	zihpm,
88	135	zk,
89	136	zkn,
90	137	zknd,
...	...	@@ -101,6 +148,7 @@ pub const Feature = enum {
101	148	zve64d,
102	149	zve64f,
103	150	zve64x,
	151	zvfh,
104	152	zvl1024b,
105	153	zvl128b,
106	154	zvl16384b,
...	...	@@ -151,34 +199,53 @@ pub const all_features = blk: {
151	199	.f,
152	200	}),
153	201	};
	202	result[@intFromEnum(Feature.dlen_factor_2)] = .{
	203	.llvm_name = "dlen-factor-2",
	204	.description = "Vector unit DLEN(data path width) is half of VLEN",
	205	.dependencies = featureSet(&[_]Feature{}),
	206	};
154	207	result[@intFromEnum(Feature.e)] = .{
155	208	.llvm_name = "e",
156		.description = "Implements RV32E (provides 16 rather than 32 GPRs)",
	209	.description = "Implements RV{32,64}E (provides 16 rather than 32 GPRs)",
157	210	.dependencies = featureSet(&[_]Feature{}),
158	211	};
159		result[@intFromEnum(Feature.experimental_zawrs)] = .{
160		.llvm_name = "experimental-zawrs",
161		.description = "'Zawrs' (Wait on Reservation Set)",
	212	result[@intFromEnum(Feature.experimental_smaia)] = .{
	213	.llvm_name = "experimental-smaia",
	214	.description = "'Smaia' (Smaia encompasses all added CSRs and all modifications to interrupt response behavior that the AIA specifies for a hart, over all privilege levels.)",
162	215	.dependencies = featureSet(&[_]Feature{}),
163	216	};
164		result[@intFromEnum(Feature.experimental_zca)] = .{
165		.llvm_name = "experimental-zca",
166		.description = "'Zca' (part of the C extension, excluding compressed floating point loads/stores)",
	217	result[@intFromEnum(Feature.experimental_ssaia)] = .{
	218	.llvm_name = "experimental-ssaia",
	219	.description = "'Ssaia' (Ssaia is essentially the same as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level.)",
167	220	.dependencies = featureSet(&[_]Feature{}),
168	221	};
169		result[@intFromEnum(Feature.experimental_zcd)] = .{
170		.llvm_name = "experimental-zcd",
171		.description = "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
	222	result[@intFromEnum(Feature.experimental_zacas)] = .{
	223	.llvm_name = "experimental-zacas",
	224	.description = "'Zacas' (Atomic Compare-And-Swap Instructions)",
172	225	.dependencies = featureSet(&[_]Feature{}),
173	226	};
174		result[@intFromEnum(Feature.experimental_zcf)] = .{
175		.llvm_name = "experimental-zcf",
176		.description = "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
	227	result[@intFromEnum(Feature.experimental_zfa)] = .{
	228	.llvm_name = "experimental-zfa",
	229	.description = "'Zfa' (Additional Floating-Point)",
	230	.dependencies = featureSet(&[_]Feature{
	231	.f,
	232	}),
	233	};
	234	result[@intFromEnum(Feature.experimental_zfbfmin)] = .{
	235	.llvm_name = "experimental-zfbfmin",
	236	.description = "'Zfbfmin' (Scalar BF16 Converts)",
	237	.dependencies = featureSet(&[_]Feature{
	238	.f,
	239	}),
	240	};
	241	result[@intFromEnum(Feature.experimental_zicond)] = .{
	242	.llvm_name = "experimental-zicond",
	243	.description = "'Zicond' (Integer Conditional Operations)",
177	244	.dependencies = featureSet(&[_]Feature{}),
178	245	};
179	246	result[@intFromEnum(Feature.experimental_zihintntl)] = .{
180	247	.llvm_name = "experimental-zihintntl",
181		.description = "'zihintntl' (Non-Temporal Locality Hints)",
	248	.description = "'Zihintntl' (Non-Temporal Locality Hints)",
182	249	.dependencies = featureSet(&[_]Feature{}),
183	250	};
184	251	result[@intFromEnum(Feature.experimental_ztso)] = .{
...	...	@@ -186,17 +253,103 @@ pub const all_features = blk: {
186	253	.description = "'Ztso' (Memory Model - Total Store Order)",
187	254	.dependencies = featureSet(&[_]Feature{}),
188	255	};
189		result[@intFromEnum(Feature.experimental_zvfh)] = .{
190		.llvm_name = "experimental-zvfh",
191		.description = "'Zvfh' (Vector Half-Precision Floating-Point)",
	256	result[@intFromEnum(Feature.experimental_zvbb)] = .{
	257	.llvm_name = "experimental-zvbb",
	258	.description = "'Zvbb' (Vector Bit-manipulation used in Cryptography)",
	259	.dependencies = featureSet(&[_]Feature{}),
	260	};
	261	result[@intFromEnum(Feature.experimental_zvbc)] = .{
	262	.llvm_name = "experimental-zvbc",
	263	.description = "'Zvbc' (Vector Carryless Multiplication)",
	264	.dependencies = featureSet(&[_]Feature{}),
	265	};
	266	result[@intFromEnum(Feature.experimental_zvfbfmin)] = .{
	267	.llvm_name = "experimental-zvfbfmin",
	268	.description = "'Zvbfmin' (Vector BF16 Converts)",
192	269	.dependencies = featureSet(&[_]Feature{
193	270	.zve32f,
194	271	}),
195	272	};
	273	result[@intFromEnum(Feature.experimental_zvfbfwma)] = .{
	274	.llvm_name = "experimental-zvfbfwma",
	275	.description = "'Zvfbfwma' (Vector BF16 widening mul-add)",
	276	.dependencies = featureSet(&[_]Feature{
	277	.zve32f,
	278	}),
	279	};
	280	result[@intFromEnum(Feature.experimental_zvkg)] = .{
	281	.llvm_name = "experimental-zvkg",
	282	.description = "'Zvkg' (Vector GCM instructions for Cryptography)",
	283	.dependencies = featureSet(&[_]Feature{}),
	284	};
	285	result[@intFromEnum(Feature.experimental_zvkn)] = .{
	286	.llvm_name = "experimental-zvkn",
	287	.description = "This extension is shorthand for the following set of other extensions: Zvkned, Zvknhb, Zvbb, Zvbc, and Zvkt.",
	288	.dependencies = featureSet(&[_]Feature{}),
	289	};
	290	result[@intFromEnum(Feature.experimental_zvknc)] = .{
	291	.llvm_name = "experimental-zvknc",
	292	.description = "This extension is shorthand for the following set of other extensions: Zvkn and Zvbc.",
	293	.dependencies = featureSet(&[_]Feature{}),
	294	};
	295	result[@intFromEnum(Feature.experimental_zvkned)] = .{
	296	.llvm_name = "experimental-zvkned",
	297	.description = "'Zvkned' (Vector AES Encryption & Decryption (Single Round))",
	298	.dependencies = featureSet(&[_]Feature{}),
	299	};
	300	result[@intFromEnum(Feature.experimental_zvkng)] = .{
	301	.llvm_name = "experimental-zvkng",
	302	.description = "This extension is shorthand for the following set of other extensions: Zvkn and Zvkg.",
	303	.dependencies = featureSet(&[_]Feature{}),
	304	};
	305	result[@intFromEnum(Feature.experimental_zvknha)] = .{
	306	.llvm_name = "experimental-zvknha",
	307	.description = "'Zvknha' (Vector SHA-2 (SHA-256 only))",
	308	.dependencies = featureSet(&[_]Feature{}),
	309	};
	310	result[@intFromEnum(Feature.experimental_zvknhb)] = .{
	311	.llvm_name = "experimental-zvknhb",
	312	.description = "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
	313	.dependencies = featureSet(&[_]Feature{
	314	.experimental_zvknha,
	315	}),
	316	};
	317	result[@intFromEnum(Feature.experimental_zvks)] = .{
	318	.llvm_name = "experimental-zvks",
	319	.description = "This extension is shorthand for the following set of other extensions: Zvksed, Zvksh, Zvbb, Zvbc, and Zvkt.",
	320	.dependencies = featureSet(&[_]Feature{}),
	321	};
	322	result[@intFromEnum(Feature.experimental_zvksc)] = .{
	323	.llvm_name = "experimental-zvksc",
	324	.description = "This extension is shorthand for the following set of other extensions: Zvks and Zvbc.",
	325	.dependencies = featureSet(&[_]Feature{}),
	326	};
	327	result[@intFromEnum(Feature.experimental_zvksed)] = .{
	328	.llvm_name = "experimental-zvksed",
	329	.description = "'Zvksed' (SM4 Block Cipher Instructions)",
	330	.dependencies = featureSet(&[_]Feature{}),
	331	};
	332	result[@intFromEnum(Feature.experimental_zvksg)] = .{
	333	.llvm_name = "experimental-zvksg",
	334	.description = "This extension is shorthand for the following set of other extensions: Zvks and Zvkg.",
	335	.dependencies = featureSet(&[_]Feature{}),
	336	};
	337	result[@intFromEnum(Feature.experimental_zvksh)] = .{
	338	.llvm_name = "experimental-zvksh",
	339	.description = "'Zvksh' (SM3 Hash Function Instructions)",
	340	.dependencies = featureSet(&[_]Feature{}),
	341	};
	342	result[@intFromEnum(Feature.experimental_zvkt)] = .{
	343	.llvm_name = "experimental-zvkt",
	344	.description = "'Zvkt' (Vector Data-Independent Execution Latency)",
	345	.dependencies = featureSet(&[_]Feature{}),
	346	};
196	347	result[@intFromEnum(Feature.f)] = .{
197	348	.llvm_name = "f",
198	349	.description = "'F' (Single-Precision Floating-Point)",
199		.dependencies = featureSet(&[_]Feature{}),
	350	.dependencies = featureSet(&[_]Feature{
	351	.zicsr,
	352	}),
200	353	};
201	354	result[@intFromEnum(Feature.forced_atomics)] = .{
202	355	.llvm_name = "forced-atomics",
...	...	@@ -398,6 +551,11 @@ pub const all_features = blk: {
398	551	.description = "Enable save/restore.",
399	552	.dependencies = featureSet(&[_]Feature{}),
400	553	};
	554	result[@intFromEnum(Feature.seq_cst_trailing_fence)] = .{
	555	.llvm_name = "seq-cst-trailing-fence",
	556	.description = "Enable trailing fence for seq-cst store.",
	557	.dependencies = featureSet(&[_]Feature{}),
	558	};
401	559	result[@intFromEnum(Feature.short_forward_branch_opt)] = .{
402	560	.llvm_name = "short-forward-branch-opt",
403	561	.description = "Enable short forward branch optimization",
...	...	@@ -428,15 +586,93 @@ pub const all_features = blk: {
428	586	.description = "Has reasonably performant unaligned scalar loads and stores",
429	587	.dependencies = featureSet(&[_]Feature{}),
430	588	};
	589	result[@intFromEnum(Feature.unaligned_vector_mem)] = .{
	590	.llvm_name = "unaligned-vector-mem",
	591	.description = "Has reasonably performant unaligned vector loads and stores",
	592	.dependencies = featureSet(&[_]Feature{}),
	593	};
431	594	result[@intFromEnum(Feature.v)] = .{
432	595	.llvm_name = "v",
433	596	.description = "'V' (Vector Extension for Application Processors)",
434	597	.dependencies = featureSet(&[_]Feature{
435		.d,
436	598	.zve64d,
437	599	.zvl128b,
438	600	}),
439	601	};
	602	result[@intFromEnum(Feature.xcvbitmanip)] = .{
	603	.llvm_name = "xcvbitmanip",
	604	.description = "'XCVbitmanip' (CORE-V Bit Manipulation)",
	605	.dependencies = featureSet(&[_]Feature{}),
	606	};
	607	result[@intFromEnum(Feature.xcvmac)] = .{
	608	.llvm_name = "xcvmac",
	609	.description = "'XCVmac' (CORE-V Multiply-Accumulate)",
	610	.dependencies = featureSet(&[_]Feature{}),
	611	};
	612	result[@intFromEnum(Feature.xsfcie)] = .{
	613	.llvm_name = "xsfcie",
	614	.description = "'XSfcie' (SiFive Custom Instruction Extension SCIE.)",
	615	.dependencies = featureSet(&[_]Feature{}),
	616	};
	617	result[@intFromEnum(Feature.xsfvcp)] = .{
	618	.llvm_name = "xsfvcp",
	619	.description = "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
	620	.dependencies = featureSet(&[_]Feature{
	621	.zve32x,
	622	}),
	623	};
	624	result[@intFromEnum(Feature.xtheadba)] = .{
	625	.llvm_name = "xtheadba",
	626	.description = "'xtheadba' (T-Head address calculation instructions)",
	627	.dependencies = featureSet(&[_]Feature{}),
	628	};
	629	result[@intFromEnum(Feature.xtheadbb)] = .{
	630	.llvm_name = "xtheadbb",
	631	.description = "'xtheadbb' (T-Head basic bit-manipulation instructions)",
	632	.dependencies = featureSet(&[_]Feature{}),
	633	};
	634	result[@intFromEnum(Feature.xtheadbs)] = .{
	635	.llvm_name = "xtheadbs",
	636	.description = "'xtheadbs' (T-Head single-bit instructions)",
	637	.dependencies = featureSet(&[_]Feature{}),
	638	};
	639	result[@intFromEnum(Feature.xtheadcmo)] = .{
	640	.llvm_name = "xtheadcmo",
	641	.description = "'xtheadcmo' (T-Head cache management instructions)",
	642	.dependencies = featureSet(&[_]Feature{}),
	643	};
	644	result[@intFromEnum(Feature.xtheadcondmov)] = .{
	645	.llvm_name = "xtheadcondmov",
	646	.description = "'xtheadcondmov' (T-Head conditional move instructions)",
	647	.dependencies = featureSet(&[_]Feature{}),
	648	};
	649	result[@intFromEnum(Feature.xtheadfmemidx)] = .{
	650	.llvm_name = "xtheadfmemidx",
	651	.description = "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)",
	652	.dependencies = featureSet(&[_]Feature{
	653	.f,
	654	}),
	655	};
	656	result[@intFromEnum(Feature.xtheadmac)] = .{
	657	.llvm_name = "xtheadmac",
	658	.description = "'xtheadmac' (T-Head Multiply-Accumulate Instructions)",
	659	.dependencies = featureSet(&[_]Feature{}),
	660	};
	661	result[@intFromEnum(Feature.xtheadmemidx)] = .{
	662	.llvm_name = "xtheadmemidx",
	663	.description = "'xtheadmemidx' (T-Head Indexed Memory Operations)",
	664	.dependencies = featureSet(&[_]Feature{}),
	665	};
	666	result[@intFromEnum(Feature.xtheadmempair)] = .{
	667	.llvm_name = "xtheadmempair",
	668	.description = "'xtheadmempair' (T-Head two-GPR Memory Operations)",
	669	.dependencies = featureSet(&[_]Feature{}),
	670	};
	671	result[@intFromEnum(Feature.xtheadsync)] = .{
	672	.llvm_name = "xtheadsync",
	673	.description = "'xtheadsync' (T-Head multicore synchronization instructions)",
	674	.dependencies = featureSet(&[_]Feature{}),
	675	};
440	676	result[@intFromEnum(Feature.xtheadvdot)] = .{
441	677	.llvm_name = "xtheadvdot",
442	678	.description = "'xtheadvdot' (T-Head Vector Extensions for Dot)",
...	...	@@ -449,6 +685,11 @@ pub const all_features = blk: {
449	685	.description = "'XVentanaCondOps' (Ventana Conditional Ops)",
450	686	.dependencies = featureSet(&[_]Feature{}),
451	687	};
	688	result[@intFromEnum(Feature.zawrs)] = .{
	689	.llvm_name = "zawrs",
	690	.description = "'Zawrs' (Wait on Reservation Set)",
	691	.dependencies = featureSet(&[_]Feature{}),
	692	};
452	693	result[@intFromEnum(Feature.zba)] = .{
453	694	.llvm_name = "zba",
454	695	.description = "'Zba' (Address Generation Instructions)",
...	...	@@ -484,6 +725,56 @@ pub const all_features = blk: {
484	725	.description = "'Zbs' (Single-Bit Instructions)",
485	726	.dependencies = featureSet(&[_]Feature{}),
486	727	};
	728	result[@intFromEnum(Feature.zca)] = .{
	729	.llvm_name = "zca",
	730	.description = "'Zca' (part of the C extension, excluding compressed floating point loads/stores)",
	731	.dependencies = featureSet(&[_]Feature{}),
	732	};
	733	result[@intFromEnum(Feature.zcb)] = .{
	734	.llvm_name = "zcb",
	735	.description = "'Zcb' (Compressed basic bit manipulation instructions)",
	736	.dependencies = featureSet(&[_]Feature{
	737	.zca,
	738	}),
	739	};
	740	result[@intFromEnum(Feature.zcd)] = .{
	741	.llvm_name = "zcd",
	742	.description = "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
	743	.dependencies = featureSet(&[_]Feature{
	744	.zca,
	745	}),
	746	};
	747	result[@intFromEnum(Feature.zce)] = .{
	748	.llvm_name = "zce",
	749	.description = "'Zce' (Compressed extensions for microcontrollers)",
	750	.dependencies = featureSet(&[_]Feature{
	751	.zcb,
	752	.zcmp,
	753	.zcmt,
	754	}),
	755	};
	756	result[@intFromEnum(Feature.zcf)] = .{
	757	.llvm_name = "zcf",
	758	.description = "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
	759	.dependencies = featureSet(&[_]Feature{
	760	.zca,
	761	}),
	762	};
	763	result[@intFromEnum(Feature.zcmp)] = .{
	764	.llvm_name = "zcmp",
	765	.description = "'Zcmp' (sequenced instuctions for code-size reduction)",
	766	.dependencies = featureSet(&[_]Feature{
	767	.zca,
	768	}),
	769	};
	770	result[@intFromEnum(Feature.zcmt)] = .{
	771	.llvm_name = "zcmt",
	772	.description = "'Zcmt' (table jump instuctions for code-size reduction)",
	773	.dependencies = featureSet(&[_]Feature{
	774	.zca,
	775	.zicsr,
	776	}),
	777	};
487	778	result[@intFromEnum(Feature.zdinx)] = .{
488	779	.llvm_name = "zdinx",
489	780	.description = "'Zdinx' (Double in Integer)",
...	...	@@ -508,7 +799,9 @@ pub const all_features = blk: {
508	799	result[@intFromEnum(Feature.zfinx)] = .{
509	800	.llvm_name = "zfinx",
510	801	.description = "'Zfinx' (Float in Integer)",
511		.dependencies = featureSet(&[_]Feature{}),
	802	.dependencies = featureSet(&[_]Feature{
	803	.zicsr,
	804	}),
512	805	};
513	806	result[@intFromEnum(Feature.zhinx)] = .{
514	807	.llvm_name = "zhinx",
...	...	@@ -539,11 +832,35 @@ pub const all_features = blk: {
539	832	.description = "'Zicboz' (Cache-Block Zero Instructions)",
540	833	.dependencies = featureSet(&[_]Feature{}),
541	834	};
	835	result[@intFromEnum(Feature.zicntr)] = .{
	836	.llvm_name = "zicntr",
	837	.description = "'Zicntr' (Base Counters and Timers)",
	838	.dependencies = featureSet(&[_]Feature{
	839	.zicsr,
	840	}),
	841	};
	842	result[@intFromEnum(Feature.zicsr)] = .{
	843	.llvm_name = "zicsr",
	844	.description = "'zicsr' (CSRs)",
	845	.dependencies = featureSet(&[_]Feature{}),
	846	};
	847	result[@intFromEnum(Feature.zifencei)] = .{
	848	.llvm_name = "zifencei",
	849	.description = "'Zifencei' (fence.i)",
	850	.dependencies = featureSet(&[_]Feature{}),
	851	};
542	852	result[@intFromEnum(Feature.zihintpause)] = .{
543	853	.llvm_name = "zihintpause",
544		.description = "'zihintpause' (Pause Hint)",
	854	.description = "'Zihintpause' (Pause Hint)",
545	855	.dependencies = featureSet(&[_]Feature{}),
546	856	};
	857	result[@intFromEnum(Feature.zihpm)] = .{
	858	.llvm_name = "zihpm",
	859	.description = "'Zihpm' (Hardware Performance Counters)",
	860	.dependencies = featureSet(&[_]Feature{
	861	.zicsr,
	862	}),
	863	};
547	864	result[@intFromEnum(Feature.zk)] = .{
548	865	.llvm_name = "zk",
549	866	.description = "'Zk' (Standard scalar cryptography extension)",
...	...	@@ -620,6 +937,7 @@ pub const all_features = blk: {
620	937	.llvm_name = "zve32f",
621	938	.description = "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)",
622	939	.dependencies = featureSet(&[_]Feature{
	940	.f,
623	941	.zve32x,
624	942	}),
625	943	};
...	...	@@ -627,6 +945,7 @@ pub const all_features = blk: {
627	945	.llvm_name = "zve32x",
628	946	.description = "'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)",
629	947	.dependencies = featureSet(&[_]Feature{
	948	.zicsr,
630	949	.zvl32b,
631	950	}),
632	951	};
...	...	@@ -634,6 +953,7 @@ pub const all_features = blk: {
634	953	.llvm_name = "zve64d",
635	954	.description = "'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)",
636	955	.dependencies = featureSet(&[_]Feature{
	956	.d,
637	957	.zve64f,
638	958	}),
639	959	};
...	...	@@ -653,6 +973,14 @@ pub const all_features = blk: {
653	973	.zvl64b,
654	974	}),
655	975	};
	976	result[@intFromEnum(Feature.zvfh)] = .{
	977	.llvm_name = "zvfh",
	978	.description = "'Zvfh' (Vector Half-Precision Floating-Point)",
	979	.dependencies = featureSet(&[_]Feature{
	980	.zfhmin,
	981	.zve32f,
	982	}),
	983	};
656	984	result[@intFromEnum(Feature.zvl1024b)] = .{
657	985	.llvm_name = "zvl1024b",
658	986	.description = "'Zvl' (Minimum Vector Length) 1024",
...	...	@@ -795,6 +1123,8 @@ pub const cpu = struct {
795	1123	.llvm_name = "rocket-rv32",
796	1124	.features = featureSet(&[_]Feature{
797	1125	.@"32bit",
	1126	.zicsr,
	1127	.zifencei,
798	1128	}),
799	1129	};
800	1130	pub const rocket_rv64 = CpuModel{
...	...	@@ -802,6 +1132,8 @@ pub const cpu = struct {
802	1132	.llvm_name = "rocket-rv64",
803	1133	.features = featureSet(&[_]Feature{
804	1134	.@"64bit",
	1135	.zicsr,
	1136	.zifencei,
805	1137	}),
806	1138	};
807	1139	pub const sifive_7_series = CpuModel{
...	...	@@ -819,6 +1151,8 @@ pub const cpu = struct {
819	1151	.@"32bit",
820	1152	.c,
821	1153	.m,
	1154	.zicsr,
	1155	.zifencei,
822	1156	}),
823	1157	};
824	1158	pub const sifive_e21 = CpuModel{
...	...	@@ -829,6 +1163,8 @@ pub const cpu = struct {
829	1163	.a,
830	1164	.c,
831	1165	.m,
	1166	.zicsr,
	1167	.zifencei,
832	1168	}),
833	1169	};
834	1170	pub const sifive_e24 = CpuModel{
...	...	@@ -840,6 +1176,7 @@ pub const cpu = struct {
840	1176	.c,
841	1177	.f,
842	1178	.m,
	1179	.zifencei,
843	1180	}),
844	1181	};
845	1182	pub const sifive_e31 = CpuModel{
...	...	@@ -850,6 +1187,8 @@ pub const cpu = struct {
850	1187	.a,
851	1188	.c,
852	1189	.m,
	1190	.zicsr,
	1191	.zifencei,
853	1192	}),
854	1193	};
855	1194	pub const sifive_e34 = CpuModel{
...	...	@@ -861,6 +1200,7 @@ pub const cpu = struct {
861	1200	.c,
862	1201	.f,
863	1202	.m,
	1203	.zifencei,
864	1204	}),
865	1205	};
866	1206	pub const sifive_e76 = CpuModel{
...	...	@@ -874,6 +1214,7 @@ pub const cpu = struct {
874	1214	.m,
875	1215	.no_default_unroll,
876	1216	.short_forward_branch_opt,
	1217	.zifencei,
877	1218	}),
878	1219	};
879	1220	pub const sifive_s21 = CpuModel{
...	...	@@ -884,6 +1225,8 @@ pub const cpu = struct {
884	1225	.a,
885	1226	.c,
886	1227	.m,
	1228	.zicsr,
	1229	.zifencei,
887	1230	}),
888	1231	};
889	1232	pub const sifive_s51 = CpuModel{
...	...	@@ -894,6 +1237,8 @@ pub const cpu = struct {
894	1237	.a,
895	1238	.c,
896	1239	.m,
	1240	.zicsr,
	1241	.zifencei,
897	1242	}),
898	1243	};
899	1244	pub const sifive_s54 = CpuModel{
...	...	@@ -905,6 +1250,7 @@ pub const cpu = struct {
905	1250	.c,
906	1251	.d,
907	1252	.m,
	1253	.zifencei,
908	1254	}),
909	1255	};
910	1256	pub const sifive_s76 = CpuModel{
...	...	@@ -918,6 +1264,9 @@ pub const cpu = struct {
918	1264	.m,
919	1265	.no_default_unroll,
920	1266	.short_forward_branch_opt,
	1267	.xsfcie,
	1268	.zifencei,
	1269	.zihintpause,
921	1270	}),
922	1271	};
923	1272	pub const sifive_u54 = CpuModel{
...	...	@@ -929,6 +1278,7 @@ pub const cpu = struct {
929	1278	.c,
930	1279	.d,
931	1280	.m,
	1281	.zifencei,
932	1282	}),
933	1283	};
934	1284	pub const sifive_u74 = CpuModel{
...	...	@@ -942,6 +1292,27 @@ pub const cpu = struct {
942	1292	.m,
943	1293	.no_default_unroll,
944	1294	.short_forward_branch_opt,
	1295	.zifencei,
	1296	}),
	1297	};
	1298	pub const sifive_x280 = CpuModel{
	1299	.name = "sifive_x280",
	1300	.llvm_name = "sifive-x280",
	1301	.features = featureSet(&[_]Feature{
	1302	.@"64bit",
	1303	.a,
	1304	.c,
	1305	.dlen_factor_2,
	1306	.m,
	1307	.no_default_unroll,
	1308	.short_forward_branch_opt,
	1309	.v,
	1310	.zba,
	1311	.zbb,
	1312	.zfh,
	1313	.zifencei,
	1314	.zvfh,
	1315	.zvl512b,
945	1316	}),
946	1317	};
947	1318	pub const syntacore_scr1_base = CpuModel{
...	...	@@ -951,6 +1322,8 @@ pub const cpu = struct {
951	1322	.@"32bit",
952	1323	.c,
953	1324	.no_default_unroll,
	1325	.zicsr,
	1326	.zifencei,
954	1327	}),
955	1328	};
956	1329	pub const syntacore_scr1_max = CpuModel{
...	...	@@ -961,6 +1334,8 @@ pub const cpu = struct {
961	1334	.c,
962	1335	.m,
963	1336	.no_default_unroll,
	1337	.zicsr,
	1338	.zifencei,
964	1339	}),
965	1340	};
966	1341	};

lib/std/target/x86.zig+299-170

...	...	@@ -14,6 +14,7 @@ pub const Feature = enum {
14	14	aes,
15	15	allow_light_256_bit,
16	16	amx_bf16,
	17	amx_complex,
17	18	amx_fp16,
18	19	amx_int8,
19	20	amx_tile,
...	...	@@ -38,6 +39,7 @@ pub const Feature = enum {
38	39	avxifma,
39	40	avxneconvert,
40	41	avxvnni,
	42	avxvnniint16,
41	43	avxvnniint8,
42	44	bmi,
43	45	bmi2,
...	...	@@ -76,6 +78,7 @@ pub const Feature = enum {
76	78	fast_variable_perlane_shuffle,
77	79	fast_vector_fsqrt,
78	80	fast_vector_shift_masks,
	81	faster_shift_than_shuffle,
79	82	fma,
80	83	fma4,
81	84	fsgsbase,
...	...	@@ -101,6 +104,10 @@ pub const Feature = enum {
101	104	movdir64b,
102	105	movdiri,
103	106	mwaitx,
	107	no_bypass_delay,
	108	no_bypass_delay_blend,
	109	no_bypass_delay_mov,
	110	no_bypass_delay_shuffle,
104	111	nopl,
105	112	pad_short_functions,
106	113	pclmul,
...	...	@@ -110,6 +117,7 @@ pub const Feature = enum {
110	117	prefer_128_bit,
111	118	prefer_256_bit,
112	119	prefer_mask_registers,
	120	prefer_movmsk_over_vtest,
113	121	prefetchi,
114	122	prefetchwt1,
115	123	prfchw,
...	...	@@ -130,6 +138,7 @@ pub const Feature = enum {
130	138	seses,
131	139	sgx,
132	140	sha,
	141	sha512,
133	142	shstk,
134	143	slow_3ops_lea,
135	144	slow_incdec,
...	...	@@ -140,6 +149,8 @@ pub const Feature = enum {
140	149	slow_two_mem_ops,
141	150	slow_unaligned_mem_16,
142	151	slow_unaligned_mem_32,
	152	sm3,
	153	sm4,
143	154	soft_float,
144	155	sse,
145	156	sse2,
...	...	@@ -152,6 +163,7 @@ pub const Feature = enum {
152	163	tagged_globals,
153	164	tbm,
154	165	tsxldtrk,
	166	tuning_fast_imm_vector_shift,
155	167	uintr,
156	168	use_glm_div_sqrt_costs,
157	169	use_slm_arith_costs,
...	...	@@ -231,6 +243,13 @@ pub const all_features = blk: {
231	243	.amx_tile,
232	244	}),
233	245	};
	246	result[@intFromEnum(Feature.amx_complex)] = .{
	247	.llvm_name = "amx-complex",
	248	.description = "Support AMX-COMPLEX instructions",
	249	.dependencies = featureSet(&[_]Feature{
	250	.amx_tile,
	251	}),
	252	};
234	253	result[@intFromEnum(Feature.amx_fp16)] = .{
235	254	.llvm_name = "amx-fp16",
236	255	.description = "Support AMX amx-fp16 instructions",
...	...	@@ -326,7 +345,7 @@ pub const all_features = blk: {
326	345	};
327	346	result[@intFromEnum(Feature.avx512ifma)] = .{
328	347	.llvm_name = "avx512ifma",
329		.description = "Enable AVX-512 Integer Fused Multiply-Add",
	348	.description = "Enable AVX-512 Integer Fused Multiple-Add",
330	349	.dependencies = featureSet(&[_]Feature{
331	350	.avx512f,
332	351	}),
...	...	@@ -401,6 +420,13 @@ pub const all_features = blk: {
401	420	.avx2,
402	421	}),
403	422	};
	423	result[@intFromEnum(Feature.avxvnniint16)] = .{
	424	.llvm_name = "avxvnniint16",
	425	.description = "Enable AVX-VNNI-INT16",
	426	.dependencies = featureSet(&[_]Feature{
	427	.avx2,
	428	}),
	429	};
404	430	result[@intFromEnum(Feature.avxvnniint8)] = .{
405	431	.llvm_name = "avxvnniint8",
406	432	.description = "Enable AVX-VNNI-INT8",
...	...	@@ -597,16 +623,21 @@ pub const all_features = blk: {
597	623	.description = "Prefer a left/right vector logical shift pair over a shift+and pair",
598	624	.dependencies = featureSet(&[_]Feature{}),
599	625	};
	626	result[@intFromEnum(Feature.faster_shift_than_shuffle)] = .{
	627	.llvm_name = "faster-shift-than-shuffle",
	628	.description = "Shifts are faster (or as fast) as shuffle",
	629	.dependencies = featureSet(&[_]Feature{}),
	630	};
600	631	result[@intFromEnum(Feature.fma)] = .{
601	632	.llvm_name = "fma",
602		.description = "Enable three-operand fused multiply-add",
	633	.description = "Enable three-operand fused multiple-add",
603	634	.dependencies = featureSet(&[_]Feature{
604	635	.avx,
605	636	}),
606	637	};
607	638	result[@intFromEnum(Feature.fma4)] = .{
608	639	.llvm_name = "fma4",
609		.description = "Enable four-operand fused multiply-add",
	640	.description = "Enable four-operand fused multiple-add",
610	641	.dependencies = featureSet(&[_]Feature{
611	642	.avx,
612	643	.sse4a,
...	...	@@ -731,6 +762,26 @@ pub const all_features = blk: {
731	762	.description = "Enable MONITORX/MWAITX timer functionality",
732	763	.dependencies = featureSet(&[_]Feature{}),
733	764	};
	765	result[@intFromEnum(Feature.no_bypass_delay)] = .{
	766	.llvm_name = "no-bypass-delay",
	767	.description = "Has no bypass delay when using the 'wrong' domain",
	768	.dependencies = featureSet(&[_]Feature{}),
	769	};
	770	result[@intFromEnum(Feature.no_bypass_delay_blend)] = .{
	771	.llvm_name = "no-bypass-delay-blend",
	772	.description = "Has no bypass delay when using the 'wrong' blend type",
	773	.dependencies = featureSet(&[_]Feature{}),
	774	};
	775	result[@intFromEnum(Feature.no_bypass_delay_mov)] = .{
	776	.llvm_name = "no-bypass-delay-mov",
	777	.description = "Has no bypass delay when using the 'wrong' mov type",
	778	.dependencies = featureSet(&[_]Feature{}),
	779	};
	780	result[@intFromEnum(Feature.no_bypass_delay_shuffle)] = .{
	781	.llvm_name = "no-bypass-delay-shuffle",
	782	.description = "Has no bypass delay when using the 'wrong' shuffle type",
	783	.dependencies = featureSet(&[_]Feature{}),
	784	};
734	785	result[@intFromEnum(Feature.nopl)] = .{
735	786	.llvm_name = "nopl",
736	787	.description = "Enable NOPL instruction (generally pentium pro+)",
...	...	@@ -778,6 +829,11 @@ pub const all_features = blk: {
778	829	.description = "Prefer AVX512 mask registers over PTEST/MOVMSK",
779	830	.dependencies = featureSet(&[_]Feature{}),
780	831	};
	832	result[@intFromEnum(Feature.prefer_movmsk_over_vtest)] = .{
	833	.llvm_name = "prefer-movmsk-over-vtest",
	834	.description = "Prefer movmsk over vtest instruction",
	835	.dependencies = featureSet(&[_]Feature{}),
	836	};
781	837	result[@intFromEnum(Feature.prefetchi)] = .{
782	838	.llvm_name = "prefetchi",
783	839	.description = "Prefetch instruction with T0 or T1 Hint",
...	...	@@ -887,6 +943,13 @@ pub const all_features = blk: {
887	943	.sse2,
888	944	}),
889	945	};
	946	result[@intFromEnum(Feature.sha512)] = .{
	947	.llvm_name = "sha512",
	948	.description = "Support SHA512 instructions",
	949	.dependencies = featureSet(&[_]Feature{
	950	.avx,
	951	}),
	952	};
890	953	result[@intFromEnum(Feature.shstk)] = .{
891	954	.llvm_name = "shstk",
892	955	.description = "Support CET Shadow-Stack instructions",
...	...	@@ -937,6 +1000,20 @@ pub const all_features = blk: {
937	1000	.description = "Slow unaligned 32-byte memory access",
938	1001	.dependencies = featureSet(&[_]Feature{}),
939	1002	};
	1003	result[@intFromEnum(Feature.sm3)] = .{
	1004	.llvm_name = "sm3",
	1005	.description = "Support SM3 instructions",
	1006	.dependencies = featureSet(&[_]Feature{
	1007	.avx,
	1008	}),
	1009	};
	1010	result[@intFromEnum(Feature.sm4)] = .{
	1011	.llvm_name = "sm4",
	1012	.description = "Support SM4 instructions",
	1013	.dependencies = featureSet(&[_]Feature{
	1014	.avx,
	1015	}),
	1016	};
940	1017	result[@intFromEnum(Feature.soft_float)] = .{
941	1018	.llvm_name = "soft-float",
942	1019	.description = "Use software floating point features",
...	...	@@ -1009,6 +1086,11 @@ pub const all_features = blk: {
1009	1086	.description = "Support TSXLDTRK instructions",
1010	1087	.dependencies = featureSet(&[_]Feature{}),
1011	1088	};
	1089	result[@intFromEnum(Feature.tuning_fast_imm_vector_shift)] = .{
	1090	.llvm_name = "tuning-fast-imm-vector-shift",
	1091	.description = "Vector shifts are fast (2/cycle) as opposed to slow (1/cycle)",
	1092	.dependencies = featureSet(&[_]Feature{}),
	1093	};
1012	1094	result[@intFromEnum(Feature.uintr)] = .{
1013	1095	.llvm_name = "uintr",
1014	1096	.description = "Has UINTR Instructions",
...	...	@@ -1148,10 +1230,14 @@ pub const cpu = struct {
1148	1230	.movbe,
1149	1231	.movdir64b,
1150	1232	.movdiri,
	1233	.no_bypass_delay_blend,
	1234	.no_bypass_delay_mov,
	1235	.no_bypass_delay_shuffle,
1151	1236	.nopl,
1152	1237	.pconfig,
1153	1238	.pku,
1154	1239	.popcnt,
	1240	.prefer_movmsk_over_vtest,
1155	1241	.prfchw,
1156	1242	.ptwrite,
1157	1243	.rdpid,
...	...	@@ -1162,6 +1248,7 @@ pub const cpu = struct {
1162	1248	.sha,
1163	1249	.shstk,
1164	1250	.slow_3ops_lea,
	1251	.tuning_fast_imm_vector_shift,
1165	1252	.vaes,
1166	1253	.vpclmulqdq,
1167	1254	.vzeroupper,
...	...	@@ -1342,6 +1429,7 @@ pub const cpu = struct {
1342	1429	.lea_uses_ag,
1343	1430	.mmx,
1344	1431	.movbe,
	1432	.no_bypass_delay,
1345	1433	.nopl,
1346	1434	.pad_short_functions,
1347	1435	.sahf,
...	...	@@ -1352,6 +1440,46 @@ pub const cpu = struct {
1352	1440	.x87,
1353	1441	}),
1354	1442	};
	1443	pub const atom_sse4_2_movbe = CpuModel{
	1444	.name = "atom_sse4_2_movbe",
	1445	.llvm_name = "atom_sse4_2_movbe",
	1446	.features = featureSet(&[_]Feature{
	1447	.@"64bit",
	1448	.aes,
	1449	.clflushopt,
	1450	.cmov,
	1451	.crc32,
	1452	.cx16,
	1453	.false_deps_popcnt,
	1454	.fast_7bytenop,
	1455	.fast_movbe,
	1456	.fsgsbase,
	1457	.fxsr,
	1458	.idivq_to_divl,
	1459	.mmx,
	1460	.movbe,
	1461	.no_bypass_delay,
	1462	.nopl,
	1463	.pclmul,
	1464	.popcnt,
	1465	.prfchw,
	1466	.rdrnd,
	1467	.rdseed,
	1468	.sahf,
	1469	.sha,
	1470	.slow_incdec,
	1471	.slow_lea,
	1472	.slow_pmulld,
	1473	.slow_two_mem_ops,
	1474	.sse4_2,
	1475	.use_slm_arith_costs,
	1476	.vzeroupper,
	1477	.x87,
	1478	.xsavec,
	1479	.xsaveopt,
	1480	.xsaves,
	1481	}),
	1482	};
1355	1483	pub const barcelona = CpuModel{
1356	1484	.name = "barcelona",
1357	1485	.llvm_name = "barcelona",
...	...	@@ -1529,6 +1657,7 @@ pub const cpu = struct {
1529	1657	.lea_uses_ag,
1530	1658	.mmx,
1531	1659	.movbe,
	1660	.no_bypass_delay,
1532	1661	.nopl,
1533	1662	.pad_short_functions,
1534	1663	.sahf,
...	...	@@ -1570,6 +1699,8 @@ pub const cpu = struct {
1570	1699	.macrofusion,
1571	1700	.mmx,
1572	1701	.movbe,
	1702	.no_bypass_delay_mov,
	1703	.no_bypass_delay_shuffle,
1573	1704	.nopl,
1574	1705	.pclmul,
1575	1706	.popcnt,
...	...	@@ -1701,6 +1832,9 @@ pub const cpu = struct {
1701	1832	.macrofusion,
1702	1833	.mmx,
1703	1834	.movbe,
	1835	.no_bypass_delay_blend,
	1836	.no_bypass_delay_mov,
	1837	.no_bypass_delay_shuffle,
1704	1838	.nopl,
1705	1839	.pclmul,
1706	1840	.pku,
...	...	@@ -1712,6 +1846,7 @@ pub const cpu = struct {
1712	1846	.sahf,
1713	1847	.sha,
1714	1848	.slow_3ops_lea,
	1849	.tuning_fast_imm_vector_shift,
1715	1850	.vzeroupper,
1716	1851	.x87,
1717	1852	.xsavec,
...	...	@@ -1748,6 +1883,7 @@ pub const cpu = struct {
1748	1883	.fast_variable_crosslane_shuffle,
1749	1884	.fast_variable_perlane_shuffle,
1750	1885	.fast_vector_fsqrt,
	1886	.faster_shift_than_shuffle,
1751	1887	.fsgsbase,
1752	1888	.fxsr,
1753	1889	.idivq_to_divl,
...	...	@@ -1756,6 +1892,9 @@ pub const cpu = struct {
1756	1892	.macrofusion,
1757	1893	.mmx,
1758	1894	.movbe,
	1895	.no_bypass_delay_blend,
	1896	.no_bypass_delay_mov,
	1897	.no_bypass_delay_shuffle,
1759	1898	.nopl,
1760	1899	.pclmul,
1761	1900	.pku,
...	...	@@ -1766,6 +1905,7 @@ pub const cpu = struct {
1766	1905	.rdseed,
1767	1906	.sahf,
1768	1907	.slow_3ops_lea,
	1908	.tuning_fast_imm_vector_shift,
1769	1909	.vzeroupper,
1770	1910	.x87,
1771	1911	.xsavec,
...	...	@@ -1802,6 +1942,7 @@ pub const cpu = struct {
1802	1942	.fast_variable_crosslane_shuffle,
1803	1943	.fast_variable_perlane_shuffle,
1804	1944	.fast_vector_fsqrt,
	1945	.faster_shift_than_shuffle,
1805	1946	.fsgsbase,
1806	1947	.fxsr,
1807	1948	.idivq_to_divl,
...	...	@@ -1810,6 +1951,9 @@ pub const cpu = struct {
1810	1951	.macrofusion,
1811	1952	.mmx,
1812	1953	.movbe,
	1954	.no_bypass_delay_blend,
	1955	.no_bypass_delay_mov,
	1956	.no_bypass_delay_shuffle,
1813	1957	.nopl,
1814	1958	.pclmul,
1815	1959	.pku,
...	...	@@ -1820,6 +1964,7 @@ pub const cpu = struct {
1820	1964	.rdseed,
1821	1965	.sahf,
1822	1966	.slow_3ops_lea,
	1967	.tuning_fast_imm_vector_shift,
1823	1968	.vzeroupper,
1824	1969	.x87,
1825	1970	.xsavec,
...	...	@@ -1845,77 +1990,6 @@ pub const cpu = struct {
1845	1990	.x87,
1846	1991	}),
1847	1992	};
1848		pub const core_avx2 = CpuModel{
1849		.name = "core_avx2",
1850		.llvm_name = "core-avx2",
1851		.features = featureSet(&[_]Feature{
1852		.@"64bit",
1853		.allow_light_256_bit,
1854		.avx2,
1855		.bmi,
1856		.bmi2,
1857		.cmov,
1858		.crc32,
1859		.cx16,
1860		.ermsb,
1861		.f16c,
1862		.false_deps_lzcnt_tzcnt,
1863		.false_deps_popcnt,
1864		.fast_15bytenop,
1865		.fast_scalar_fsqrt,
1866		.fast_shld_rotate,
1867		.fast_variable_crosslane_shuffle,
1868		.fast_variable_perlane_shuffle,
1869		.fma,
1870		.fsgsbase,
1871		.fxsr,
1872		.idivq_to_divl,
1873		.invpcid,
1874		.lzcnt,
1875		.macrofusion,
1876		.mmx,
1877		.movbe,
1878		.nopl,
1879		.pclmul,
1880		.popcnt,
1881		.rdrnd,
1882		.sahf,
1883		.slow_3ops_lea,
1884		.vzeroupper,
1885		.x87,
1886		.xsaveopt,
1887		}),
1888		};
1889		pub const core_avx_i = CpuModel{
1890		.name = "core_avx_i",
1891		.llvm_name = "core-avx-i",
1892		.features = featureSet(&[_]Feature{
1893		.@"64bit",
1894		.cmov,
1895		.crc32,
1896		.cx16,
1897		.f16c,
1898		.false_deps_popcnt,
1899		.fast_15bytenop,
1900		.fast_scalar_fsqrt,
1901		.fast_shld_rotate,
1902		.fsgsbase,
1903		.fxsr,
1904		.idivq_to_divl,
1905		.macrofusion,
1906		.mmx,
1907		.nopl,
1908		.pclmul,
1909		.popcnt,
1910		.rdrnd,
1911		.sahf,
1912		.slow_3ops_lea,
1913		.slow_unaligned_mem_32,
1914		.vzeroupper,
1915		.x87,
1916		.xsaveopt,
1917		}),
1918		};
1919	1993	pub const corei7 = CpuModel{
1920	1994	.name = "corei7",
1921	1995	.llvm_name = "corei7",
...	...	@@ -1927,6 +2001,7 @@ pub const cpu = struct {
1927	2001	.fxsr,
1928	2002	.macrofusion,
1929	2003	.mmx,
	2004	.no_bypass_delay_mov,
1930	2005	.nopl,
1931	2006	.popcnt,
1932	2007	.sahf,
...	...	@@ -1935,34 +2010,6 @@ pub const cpu = struct {
1935	2010	.x87,
1936	2011	}),
1937	2012	};
1938		pub const corei7_avx = CpuModel{
1939		.name = "corei7_avx",
1940		.llvm_name = "corei7-avx",
1941		.features = featureSet(&[_]Feature{
1942		.@"64bit",
1943		.avx,
1944		.cmov,
1945		.crc32,
1946		.cx16,
1947		.false_deps_popcnt,
1948		.fast_15bytenop,
1949		.fast_scalar_fsqrt,
1950		.fast_shld_rotate,
1951		.fxsr,
1952		.idivq_to_divl,
1953		.macrofusion,
1954		.mmx,
1955		.nopl,
1956		.pclmul,
1957		.popcnt,
1958		.sahf,
1959		.slow_3ops_lea,
1960		.slow_unaligned_mem_32,
1961		.vzeroupper,
1962		.x87,
1963		.xsaveopt,
1964		}),
1965		};
1966	2013	pub const emeraldrapids = CpuModel{
1967	2014	.name = "emeraldrapids",
1968	2015	.llvm_name = "emeraldrapids",
...	...	@@ -2016,6 +2063,9 @@ pub const cpu = struct {
2016	2063	.movbe,
2017	2064	.movdir64b,
2018	2065	.movdiri,
	2066	.no_bypass_delay_blend,
	2067	.no_bypass_delay_mov,
	2068	.no_bypass_delay_shuffle,
2019	2069	.nopl,
2020	2070	.pconfig,
2021	2071	.pku,
...	...	@@ -2031,6 +2081,7 @@ pub const cpu = struct {
2031	2081	.sha,
2032	2082	.shstk,
2033	2083	.tsxldtrk,
	2084	.tuning_fast_imm_vector_shift,
2034	2085	.uintr,
2035	2086	.vaes,
2036	2087	.vpclmulqdq,
...	...	@@ -2085,6 +2136,7 @@ pub const cpu = struct {
2085	2136	.fxsr,
2086	2137	.mmx,
2087	2138	.movbe,
	2139	.no_bypass_delay,
2088	2140	.nopl,
2089	2141	.pclmul,
2090	2142	.popcnt,
...	...	@@ -2120,6 +2172,7 @@ pub const cpu = struct {
2120	2172	.fxsr,
2121	2173	.mmx,
2122	2174	.movbe,
	2175	.no_bypass_delay,
2123	2176	.nopl,
2124	2177	.pclmul,
2125	2178	.popcnt,
...	...	@@ -2161,6 +2214,7 @@ pub const cpu = struct {
2161	2214	.cmpccxadd,
2162	2215	.crc32,
2163	2216	.cx16,
	2217	.enqcmd,
2164	2218	.f16c,
2165	2219	.fast_movbe,
2166	2220	.fma,
...	...	@@ -2174,6 +2228,7 @@ pub const cpu = struct {
2174	2228	.movbe,
2175	2229	.movdir64b,
2176	2230	.movdiri,
	2231	.no_bypass_delay,
2177	2232	.nopl,
2178	2233	.pconfig,
2179	2234	.pku,
...	...	@@ -2191,6 +2246,7 @@ pub const cpu = struct {
2191	2246	.slow_incdec,
2192	2247	.slow_lea,
2193	2248	.slow_two_mem_ops,
	2249	.uintr,
2194	2250	.use_glm_div_sqrt_costs,
2195	2251	.vaes,
2196	2252	.vpclmulqdq,
...	...	@@ -2257,6 +2313,96 @@ pub const cpu = struct {
2257	2313	.movbe,
2258	2314	.movdir64b,
2259	2315	.movdiri,
	2316	.no_bypass_delay_blend,
	2317	.no_bypass_delay_mov,
	2318	.no_bypass_delay_shuffle,
	2319	.nopl,
	2320	.pconfig,
	2321	.pku,
	2322	.popcnt,
	2323	.prefer_256_bit,
	2324	.prefetchi,
	2325	.prfchw,
	2326	.ptwrite,
	2327	.rdpid,
	2328	.rdrnd,
	2329	.rdseed,
	2330	.sahf,
	2331	.serialize,
	2332	.sha,
	2333	.shstk,
	2334	.tsxldtrk,
	2335	.tuning_fast_imm_vector_shift,
	2336	.uintr,
	2337	.vaes,
	2338	.vpclmulqdq,
	2339	.vzeroupper,
	2340	.waitpkg,
	2341	.wbnoinvd,
	2342	.x87,
	2343	.xsavec,
	2344	.xsaveopt,
	2345	.xsaves,
	2346	}),
	2347	};
	2348	pub const graniterapids_d = CpuModel{
	2349	.name = "graniterapids_d",
	2350	.llvm_name = "graniterapids-d",
	2351	.features = featureSet(&[_]Feature{
	2352	.@"64bit",
	2353	.adx,
	2354	.allow_light_256_bit,
	2355	.amx_bf16,
	2356	.amx_complex,
	2357	.amx_fp16,
	2358	.amx_int8,
	2359	.avx512bf16,
	2360	.avx512bitalg,
	2361	.avx512cd,
	2362	.avx512fp16,
	2363	.avx512ifma,
	2364	.avx512vbmi,
	2365	.avx512vbmi2,
	2366	.avx512vnni,
	2367	.avx512vpopcntdq,
	2368	.avxvnni,
	2369	.bmi,
	2370	.bmi2,
	2371	.cldemote,
	2372	.clflushopt,
	2373	.clwb,
	2374	.cmov,
	2375	.crc32,
	2376	.cx16,
	2377	.enqcmd,
	2378	.ermsb,
	2379	.false_deps_getmant,
	2380	.false_deps_mulc,
	2381	.false_deps_mullq,
	2382	.false_deps_perm,
	2383	.false_deps_range,
	2384	.fast_15bytenop,
	2385	.fast_gather,
	2386	.fast_scalar_fsqrt,
	2387	.fast_shld_rotate,
	2388	.fast_variable_crosslane_shuffle,
	2389	.fast_variable_perlane_shuffle,
	2390	.fast_vector_fsqrt,
	2391	.fsgsbase,
	2392	.fsrm,
	2393	.fxsr,
	2394	.gfni,
	2395	.idivq_to_divl,
	2396	.invpcid,
	2397	.lzcnt,
	2398	.macrofusion,
	2399	.mmx,
	2400	.movbe,
	2401	.movdir64b,
	2402	.movdiri,
	2403	.no_bypass_delay_blend,
	2404	.no_bypass_delay_mov,
	2405	.no_bypass_delay_shuffle,
2260	2406	.nopl,
2261	2407	.pconfig,
2262	2408	.pku,
...	...	@@ -2273,6 +2419,7 @@ pub const cpu = struct {
2273	2419	.sha,
2274	2420	.shstk,
2275	2421	.tsxldtrk,
	2422	.tuning_fast_imm_vector_shift,
2276	2423	.uintr,
2277	2424	.vaes,
2278	2425	.vpclmulqdq,
...	...	@@ -2315,6 +2462,8 @@ pub const cpu = struct {
2315	2462	.macrofusion,
2316	2463	.mmx,
2317	2464	.movbe,
	2465	.no_bypass_delay_mov,
	2466	.no_bypass_delay_shuffle,
2318	2467	.nopl,
2319	2468	.pclmul,
2320	2469	.popcnt,
...	...	@@ -2405,6 +2554,9 @@ pub const cpu = struct {
2405	2554	.macrofusion,
2406	2555	.mmx,
2407	2556	.movbe,
	2557	.no_bypass_delay_blend,
	2558	.no_bypass_delay_mov,
	2559	.no_bypass_delay_shuffle,
2408	2560	.nopl,
2409	2561	.pku,
2410	2562	.popcnt,
...	...	@@ -2415,6 +2567,7 @@ pub const cpu = struct {
2415	2567	.rdseed,
2416	2568	.sahf,
2417	2569	.sha,
	2570	.tuning_fast_imm_vector_shift,
2418	2571	.vaes,
2419	2572	.vpclmulqdq,
2420	2573	.vzeroupper,
...	...	@@ -2465,6 +2618,9 @@ pub const cpu = struct {
2465	2618	.macrofusion,
2466	2619	.mmx,
2467	2620	.movbe,
	2621	.no_bypass_delay_blend,
	2622	.no_bypass_delay_mov,
	2623	.no_bypass_delay_shuffle,
2468	2624	.nopl,
2469	2625	.pconfig,
2470	2626	.pku,
...	...	@@ -2476,6 +2632,7 @@ pub const cpu = struct {
2476	2632	.rdseed,
2477	2633	.sahf,
2478	2634	.sha,
	2635	.tuning_fast_imm_vector_shift,
2479	2636	.vaes,
2480	2637	.vpclmulqdq,
2481	2638	.vzeroupper,
...	...	@@ -2504,6 +2661,7 @@ pub const cpu = struct {
2504	2661	.idivq_to_divl,
2505	2662	.macrofusion,
2506	2663	.mmx,
	2664	.no_bypass_delay_mov,
2507	2665	.nopl,
2508	2666	.pclmul,
2509	2667	.popcnt,
...	...	@@ -2717,10 +2875,14 @@ pub const cpu = struct {
2717	2875	.movbe,
2718	2876	.movdir64b,
2719	2877	.movdiri,
	2878	.no_bypass_delay_blend,
	2879	.no_bypass_delay_mov,
	2880	.no_bypass_delay_shuffle,
2720	2881	.nopl,
2721	2882	.pconfig,
2722	2883	.pku,
2723	2884	.popcnt,
	2885	.prefer_movmsk_over_vtest,
2724	2886	.prfchw,
2725	2887	.ptwrite,
2726	2888	.rdpid,
...	...	@@ -2731,6 +2893,7 @@ pub const cpu = struct {
2731	2893	.sha,
2732	2894	.shstk,
2733	2895	.slow_3ops_lea,
	2896	.tuning_fast_imm_vector_shift,
2734	2897	.vaes,
2735	2898	.vpclmulqdq,
2736	2899	.vzeroupper,
...	...	@@ -2753,6 +2916,7 @@ pub const cpu = struct {
2753	2916	.fxsr,
2754	2917	.macrofusion,
2755	2918	.mmx,
	2919	.no_bypass_delay_mov,
2756	2920	.nopl,
2757	2921	.popcnt,
2758	2922	.sahf,
...	...	@@ -2902,21 +3066,6 @@ pub const cpu = struct {
2902	3066	.x87,
2903	3067	}),
2904	3068	};
2905		pub const pentium4m = CpuModel{
2906		.name = "pentium4m",
2907		.llvm_name = "pentium4m",
2908		.features = featureSet(&[_]Feature{
2909		.cmov,
2910		.cx8,
2911		.fxsr,
2912		.mmx,
2913		.nopl,
2914		.slow_unaligned_mem_16,
2915		.sse2,
2916		.vzeroupper,
2917		.x87,
2918		}),
2919		};
2920	3069	pub const pentium_m = CpuModel{
2921	3070	.name = "pentium_m",
2922	3071	.llvm_name = "pentium-m",
...	...	@@ -3009,10 +3158,14 @@ pub const cpu = struct {
3009	3158	.movbe,
3010	3159	.movdir64b,
3011	3160	.movdiri,
	3161	.no_bypass_delay_blend,
	3162	.no_bypass_delay_mov,
	3163	.no_bypass_delay_shuffle,
3012	3164	.nopl,
3013	3165	.pconfig,
3014	3166	.pku,
3015	3167	.popcnt,
	3168	.prefer_movmsk_over_vtest,
3016	3169	.prfchw,
3017	3170	.ptwrite,
3018	3171	.rdpid,
...	...	@@ -3023,6 +3176,7 @@ pub const cpu = struct {
3023	3176	.sha,
3024	3177	.shstk,
3025	3178	.slow_3ops_lea,
	3179	.tuning_fast_imm_vector_shift,
3026	3180	.vaes,
3027	3181	.vpclmulqdq,
3028	3182	.vzeroupper,
...	...	@@ -3074,6 +3228,9 @@ pub const cpu = struct {
3074	3228	.macrofusion,
3075	3229	.mmx,
3076	3230	.movbe,
	3231	.no_bypass_delay_blend,
	3232	.no_bypass_delay_mov,
	3233	.no_bypass_delay_shuffle,
3077	3234	.nopl,
3078	3235	.pku,
3079	3236	.popcnt,
...	...	@@ -3084,6 +3241,7 @@ pub const cpu = struct {
3084	3241	.rdseed,
3085	3242	.sahf,
3086	3243	.sha,
	3244	.tuning_fast_imm_vector_shift,
3087	3245	.vaes,
3088	3246	.vpclmulqdq,
3089	3247	.vzeroupper,
...	...	@@ -3110,6 +3268,7 @@ pub const cpu = struct {
3110	3268	.idivq_to_divl,
3111	3269	.macrofusion,
3112	3270	.mmx,
	3271	.no_bypass_delay_mov,
3113	3272	.nopl,
3114	3273	.pclmul,
3115	3274	.popcnt,
...	...	@@ -3174,6 +3333,9 @@ pub const cpu = struct {
3174	3333	.movbe,
3175	3334	.movdir64b,
3176	3335	.movdiri,
	3336	.no_bypass_delay_blend,
	3337	.no_bypass_delay_mov,
	3338	.no_bypass_delay_shuffle,
3177	3339	.nopl,
3178	3340	.pconfig,
3179	3341	.pku,
...	...	@@ -3189,6 +3351,7 @@ pub const cpu = struct {
3189	3351	.sha,
3190	3352	.shstk,
3191	3353	.tsxldtrk,
	3354	.tuning_fast_imm_vector_shift,
3192	3355	.uintr,
3193	3356	.vaes,
3194	3357	.vpclmulqdq,
...	...	@@ -3220,6 +3383,7 @@ pub const cpu = struct {
3220	3383	.cmpccxadd,
3221	3384	.crc32,
3222	3385	.cx16,
	3386	.enqcmd,
3223	3387	.f16c,
3224	3388	.fast_movbe,
3225	3389	.fma,
...	...	@@ -3233,6 +3397,7 @@ pub const cpu = struct {
3233	3397	.movbe,
3234	3398	.movdir64b,
3235	3399	.movdiri,
	3400	.no_bypass_delay,
3236	3401	.nopl,
3237	3402	.pconfig,
3238	3403	.pku,
...	...	@@ -3249,6 +3414,7 @@ pub const cpu = struct {
3249	3414	.slow_incdec,
3250	3415	.slow_lea,
3251	3416	.slow_two_mem_ops,
	3417	.uintr,
3252	3418	.use_glm_div_sqrt_costs,
3253	3419	.vaes,
3254	3420	.vpclmulqdq,
...	...	@@ -3276,6 +3442,7 @@ pub const cpu = struct {
3276	3442	.idivq_to_divl,
3277	3443	.mmx,
3278	3444	.movbe,
	3445	.no_bypass_delay,
3279	3446	.nopl,
3280	3447	.pclmul,
3281	3448	.popcnt,
...	...	@@ -3320,6 +3487,7 @@ pub const cpu = struct {
3320	3487	.fast_variable_crosslane_shuffle,
3321	3488	.fast_variable_perlane_shuffle,
3322	3489	.fast_vector_fsqrt,
	3490	.faster_shift_than_shuffle,
3323	3491	.fsgsbase,
3324	3492	.fxsr,
3325	3493	.idivq_to_divl,
...	...	@@ -3328,6 +3496,9 @@ pub const cpu = struct {
3328	3496	.macrofusion,
3329	3497	.mmx,
3330	3498	.movbe,
	3499	.no_bypass_delay_blend,
	3500	.no_bypass_delay_mov,
	3501	.no_bypass_delay_shuffle,
3331	3502	.nopl,
3332	3503	.pclmul,
3333	3504	.pku,
...	...	@@ -3338,6 +3509,7 @@ pub const cpu = struct {
3338	3509	.rdseed,
3339	3510	.sahf,
3340	3511	.slow_3ops_lea,
	3512	.tuning_fast_imm_vector_shift,
3341	3513	.vzeroupper,
3342	3514	.x87,
3343	3515	.xsavec,
...	...	@@ -3379,6 +3551,9 @@ pub const cpu = struct {
3379	3551	.macrofusion,
3380	3552	.mmx,
3381	3553	.movbe,
	3554	.no_bypass_delay_blend,
	3555	.no_bypass_delay_mov,
	3556	.no_bypass_delay_shuffle,
3382	3557	.nopl,
3383	3558	.pclmul,
3384	3559	.popcnt,
...	...	@@ -3394,59 +3569,6 @@ pub const cpu = struct {
3394	3569	.xsaves,
3395	3570	}),
3396	3571	};
3397		pub const skylake_avx512 = CpuModel{
3398		.name = "skylake_avx512",
3399		.llvm_name = "skylake-avx512",
3400		.features = featureSet(&[_]Feature{
3401		.@"64bit",
3402		.adx,
3403		.aes,
3404		.allow_light_256_bit,
3405		.avx512bw,
3406		.avx512cd,
3407		.avx512dq,
3408		.avx512vl,
3409		.bmi,
3410		.bmi2,
3411		.clflushopt,
3412		.clwb,
3413		.cmov,
3414		.crc32,
3415		.cx16,
3416		.ermsb,
3417		.false_deps_popcnt,
3418		.fast_15bytenop,
3419		.fast_gather,
3420		.fast_scalar_fsqrt,
3421		.fast_shld_rotate,
3422		.fast_variable_crosslane_shuffle,
3423		.fast_variable_perlane_shuffle,
3424		.fast_vector_fsqrt,
3425		.fsgsbase,
3426		.fxsr,
3427		.idivq_to_divl,
3428		.invpcid,
3429		.lzcnt,
3430		.macrofusion,
3431		.mmx,
3432		.movbe,
3433		.nopl,
3434		.pclmul,
3435		.pku,
3436		.popcnt,
3437		.prefer_256_bit,
3438		.prfchw,
3439		.rdrnd,
3440		.rdseed,
3441		.sahf,
3442		.slow_3ops_lea,
3443		.vzeroupper,
3444		.x87,
3445		.xsavec,
3446		.xsaveopt,
3447		.xsaves,
3448		}),
3449		};
3450	3572	pub const slm = CpuModel{
3451	3573	.name = "slm",
3452	3574	.llvm_name = "slm",
...	...	@@ -3462,6 +3584,7 @@ pub const cpu = struct {
3462	3584	.idivq_to_divl,
3463	3585	.mmx,
3464	3586	.movbe,
	3587	.no_bypass_delay,
3465	3588	.nopl,
3466	3589	.pclmul,
3467	3590	.popcnt,
...	...	@@ -3522,6 +3645,9 @@ pub const cpu = struct {
3522	3645	.movbe,
3523	3646	.movdir64b,
3524	3647	.movdiri,
	3648	.no_bypass_delay_blend,
	3649	.no_bypass_delay_mov,
	3650	.no_bypass_delay_shuffle,
3525	3651	.nopl,
3526	3652	.pku,
3527	3653	.popcnt,
...	...	@@ -3533,6 +3659,7 @@ pub const cpu = struct {
3533	3659	.sahf,
3534	3660	.sha,
3535	3661	.shstk,
	3662	.tuning_fast_imm_vector_shift,
3536	3663	.vaes,
3537	3664	.vpclmulqdq,
3538	3665	.vzeroupper,
...	...	@@ -3559,6 +3686,7 @@ pub const cpu = struct {
3559	3686	.gfni,
3560	3687	.mmx,
3561	3688	.movbe,
	3689	.no_bypass_delay,
3562	3690	.nopl,
3563	3691	.pclmul,
3564	3692	.popcnt,
...	...	@@ -3592,6 +3720,7 @@ pub const cpu = struct {
3592	3720	.fxsr,
3593	3721	.macrofusion,
3594	3722	.mmx,
	3723	.no_bypass_delay_mov,
3595	3724	.nopl,
3596	3725	.pclmul,
3597	3726	.popcnt,

tools/update_cpu_features.zig+39

...	...	@@ -40,6 +40,7 @@ const LlvmTarget = struct {
40	40	feature_overrides: []const FeatureOverride = &.{},
41	41	extra_cpus: []const Cpu = &.{},
42	42	extra_features: []const Feature = &.{},
	43	omit_cpus: []const []const u8 = &.{},
43	44	branch_quota: ?usize = null,
44	45	};
45	46
...	...	@@ -915,6 +916,40 @@ const llvm_targets = [_]LlvmTarget{
915	916	.extra_deps = &.{"soft_float"},
916	917	},
917	918	},
	919	.omit_cpus = &.{
	920	// LLVM defines a bunch of dumb aliases with foreach loops in X86.td.
	921	"pentium_mmx",
	922	"pentium_pro",
	923	"pentium_ii",
	924	"pentium_3m",
	925	"pentium_iii_no_xmm_regs",
	926	"pentium_iii",
	927	"pentium_m",
	928	"pentium4m",
	929	"pentium_4",
	930	"pentium_4_sse3",
	931	"core_2_duo_ssse3",
	932	"core_2_duo_sse4_1",
	933	"atom_sse4_2",
	934	"goldmont_plus",
	935	"core_i7_sse4_2",
	936	"core_aes_pclmulqdq",
	937	"corei7-avx",
	938	"core_2nd_gen_avx",
	939	"core-avx-i",
	940	"core_3rd_gen_avx",
	941	"core-avx2",
	942	"core_4th_gen_avx",
	943	"core_4th_gen_avx_tsx",
	944	"core_5th_gen_avx",
	945	"core_5th_gen_avx_tsx",
	946	"mic_avx512",
	947	"skylake_avx512",
	948	"skylake-avx512",
	949	"icelake_client",
	950	"icelake_server",
	951	"graniterapids_d",
	952	},
918	953	},
919	954	.{
920	955	.zig_name = "xcore",
...	...	@@ -1129,6 +1164,10 @@ fn processOneTarget(job: Job) anyerror!void {
1129	1164	if (hasSuperclass(&kv.value_ptr.object, "Processor")) {
1130	1165	const llvm_name = kv.value_ptr.object.get("Name").?.string;
1131	1166	if (llvm_name.len == 0) continue;
	1167	const omitted = for (llvm_target.omit_cpus) \|omit_cpu_name\| {
	1168	if (mem.eql(u8, omit_cpu_name, llvm_name)) break true;
	1169	} else false;
	1170	if (omitted) continue;
1132	1171
1133	1172	var zig_name = try llvmNameToZigName(arena, llvm_name);
1134	1173	var deps = std.ArrayList([]const u8).init(arena);