Commit 3ed40b114020ff774279a5af993851d74da64b52 | zig

author	Andrew Kelley <andrew@ziglang.org> 2023-08-11 16:15:19-07:00
committer	Andrew Kelley <andrew@ziglang.org> 2023-09-19 09:37:31-07:00
log	3ed40b114020ff774279a5af993851d74da64b52
tree	733076dbb0b66df6fd51a6bcadbc0091b4eab99f
parent	1c7adf5064386fe668fe580d701db07d226245ed

update CPU features to LLVM 17

release/17.x branch, commit 8f4dd44097c9ae25dd203d5ac87f3b48f854bba8

12 files changed, 1142 insertions(+), 295 deletions(-)

lib
- std
  - target
    aarch64.zig
    amdgpu.zig
    arm.zig
    avr.zig
    bpf.zig
    csky.zig
    loongarch.zig
    m68k.zig
    nvptx.zig
    riscv.zig
    x86.zig
tools
- update_cpu_features.zig

lib/std/target/aarch64.zig+53

...	@@ -37,6 +37,7 @@ pub const Feature = enum {	...	@@ -37,6 +37,7 @@ pub const Feature = enum {
37	ccdp,	37	ccdp,
38	ccidx,	38	ccidx,
39	ccpp,	39	ccpp,
		40	chk,
40	clrbhb,	41	clrbhb,
41	cmp_bcc_fusion,	42	cmp_bcc_fusion,
42	complxnum,	43	complxnum,
...	@@ -68,12 +69,14 @@ pub const Feature = enum {	...	@@ -68,12 +69,14 @@ pub const Feature = enum {
68	fptoint,	69	fptoint,
69	fullfp16,	70	fullfp16,
70	fuse_address,	71	fuse_address,
		72	fuse_addsub_2reg_const1,
71	fuse_adrp_add,	73	fuse_adrp_add,
72	fuse_aes,	74	fuse_aes,
73	fuse_arith_logic,	75	fuse_arith_logic,
74	fuse_crypto_eor,	76	fuse_crypto_eor,
75	fuse_csel,	77	fuse_csel,
76	fuse_literals,	78	fuse_literals,
		79	gcs,
77	harden_sls_blr,	80	harden_sls_blr,
78	harden_sls_nocomdat,	81	harden_sls_nocomdat,
79	harden_sls_retbr,	82	harden_sls_retbr,
...	@@ -96,6 +99,7 @@ pub const Feature = enum {	...	@@ -96,6 +99,7 @@ pub const Feature = enum {
96	nmi,	99	nmi,
97	no_bti_at_return_twice,	100	no_bti_at_return_twice,
98	no_neg_immediates,	101	no_neg_immediates,
		102	no_sve_fp_ld1r,
99	no_zcz_fp,	103	no_zcz_fp,
100	nv,	104	nv,
101	outline_atomics,	105	outline_atomics,
...	@@ -173,6 +177,7 @@ pub const Feature = enum {	...	@@ -173,6 +177,7 @@ pub const Feature = enum {
173	tpidr_el1,	177	tpidr_el1,
174	tpidr_el2,	178	tpidr_el2,
175	tpidr_el3,	179	tpidr_el3,
		180	tpidrro_el0,
176	tracev8_4,	181	tracev8_4,
177	trbe,	182	trbe,
178	uaops,	183	uaops,
...	@@ -233,6 +238,7 @@ pub const all_features = blk: {	...	@@ -233,6 +238,7 @@ pub const all_features = blk: {
233	.fuse_adrp_add,	238	.fuse_adrp_add,
234	.fuse_aes,	239	.fuse_aes,
235	.fuse_literals,	240	.fuse_literals,
		241	.predictable_select_expensive,
236	}),	242	}),
237	};	243	};
238	result[@intFromEnum(Feature.a710)] = .{	244	result[@intFromEnum(Feature.a710)] = .{
...	@@ -244,6 +250,7 @@ pub const all_features = blk: {	...	@@ -244,6 +250,7 @@ pub const all_features = blk: {
244	.fuse_adrp_add,	250	.fuse_adrp_add,
245	.fuse_aes,	251	.fuse_aes,
246	.lsl_fast,	252	.lsl_fast,
		253	.predictable_select_expensive,
247	.use_postra_scheduler,	254	.use_postra_scheduler,
248	}),	255	}),
249	};	256	};
...	@@ -255,6 +262,7 @@ pub const all_features = blk: {	...	@@ -255,6 +262,7 @@ pub const all_features = blk: {
255	.fuse_adrp_add,	262	.fuse_adrp_add,
256	.fuse_aes,	263	.fuse_aes,
257	.lsl_fast,	264	.lsl_fast,
		265	.predictable_select_expensive,
258	}),	266	}),
259	};	267	};
260	result[@intFromEnum(Feature.a78)] = .{	268	result[@intFromEnum(Feature.a78)] = .{
...	@@ -266,6 +274,7 @@ pub const all_features = blk: {	...	@@ -266,6 +274,7 @@ pub const all_features = blk: {
266	.fuse_adrp_add,	274	.fuse_adrp_add,
267	.fuse_aes,	275	.fuse_aes,
268	.lsl_fast,	276	.lsl_fast,
		277	.predictable_select_expensive,
269	.use_postra_scheduler,	278	.use_postra_scheduler,
270	}),	279	}),
271	};	280	};
...	@@ -278,6 +287,7 @@ pub const all_features = blk: {	...	@@ -278,6 +287,7 @@ pub const all_features = blk: {
278	.fuse_adrp_add,	287	.fuse_adrp_add,
279	.fuse_aes,	288	.fuse_aes,
280	.lsl_fast,	289	.lsl_fast,
		290	.predictable_select_expensive,
281	.use_postra_scheduler,	291	.use_postra_scheduler,
282	}),	292	}),
283	};	293	};
...	@@ -415,6 +425,11 @@ pub const all_features = blk: {	...	@@ -415,6 +425,11 @@ pub const all_features = blk: {
415	.description = "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)",	425	.description = "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)",
416	.dependencies = featureSet(&[_]Feature{}),	426	.dependencies = featureSet(&[_]Feature{}),
417	};	427	};
		428	result[@intFromEnum(Feature.chk)] = .{
		429	.llvm_name = "chk",
		430	.description = "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)",
		431	.dependencies = featureSet(&[_]Feature{}),
		432	};
418	result[@intFromEnum(Feature.clrbhb)] = .{	433	result[@intFromEnum(Feature.clrbhb)] = .{
419	.llvm_name = "clrbhb",	434	.llvm_name = "clrbhb",
420	.description = "Enable Clear BHB instruction (FEAT_CLRBHB)",	435	.description = "Enable Clear BHB instruction (FEAT_CLRBHB)",
...	@@ -591,6 +606,11 @@ pub const all_features = blk: {	...	@@ -591,6 +606,11 @@ pub const all_features = blk: {
591	.description = "CPU fuses address generation and memory operations",	606	.description = "CPU fuses address generation and memory operations",
592	.dependencies = featureSet(&[_]Feature{}),	607	.dependencies = featureSet(&[_]Feature{}),
593	};	608	};
		609	result[@intFromEnum(Feature.fuse_addsub_2reg_const1)] = .{
		610	.llvm_name = "fuse-addsub-2reg-const1",
		611	.description = "CPU fuses (a + b + 1) and (a - b - 1)",
		612	.dependencies = featureSet(&[_]Feature{}),
		613	};
594	result[@intFromEnum(Feature.fuse_adrp_add)] = .{	614	result[@intFromEnum(Feature.fuse_adrp_add)] = .{
595	.llvm_name = "fuse-adrp-add",	615	.llvm_name = "fuse-adrp-add",
596	.description = "CPU fuses adrp+add operations",	616	.description = "CPU fuses adrp+add operations",
...	@@ -621,6 +641,13 @@ pub const all_features = blk: {	...	@@ -621,6 +641,13 @@ pub const all_features = blk: {
621	.description = "CPU fuses literal generation operations",	641	.description = "CPU fuses literal generation operations",
622	.dependencies = featureSet(&[_]Feature{}),	642	.dependencies = featureSet(&[_]Feature{}),
623	};	643	};
		644	result[@intFromEnum(Feature.gcs)] = .{
		645	.llvm_name = "gcs",
		646	.description = "Enable Armv9.4-A Guarded Call Stack Extension",
		647	.dependencies = featureSet(&[_]Feature{
		648	.chk,
		649	}),
		650	};
624	result[@intFromEnum(Feature.harden_sls_blr)] = .{	651	result[@intFromEnum(Feature.harden_sls_blr)] = .{
625	.llvm_name = "harden-sls-blr",	652	.llvm_name = "harden-sls-blr",
626	.description = "Harden against straight line speculation across BLR instructions",	653	.description = "Harden against straight line speculation across BLR instructions",
...	@@ -741,6 +768,11 @@ pub const all_features = blk: {	...	@@ -741,6 +768,11 @@ pub const all_features = blk: {
741	.description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",	768	.description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
742	.dependencies = featureSet(&[_]Feature{}),	769	.dependencies = featureSet(&[_]Feature{}),
743	};	770	};
		771	result[@intFromEnum(Feature.no_sve_fp_ld1r)] = .{
		772	.llvm_name = "no-sve-fp-ld1r",
		773	.description = "Avoid using LD1RX instructions for FP",
		774	.dependencies = featureSet(&[_]Feature{}),
		775	};
744	result[@intFromEnum(Feature.no_zcz_fp)] = .{	776	result[@intFromEnum(Feature.no_zcz_fp)] = .{
745	.llvm_name = "no-zcz-fp",	777	.llvm_name = "no-zcz-fp",
746	.description = "Has no zero-cycle zeroing instructions for FP registers",	778	.description = "Has no zero-cycle zeroing instructions for FP registers",
...	@@ -1171,6 +1203,11 @@ pub const all_features = blk: {	...	@@ -1171,6 +1203,11 @@ pub const all_features = blk: {
1171	.description = "Permit use of TPIDR_EL3 for the TLS base",	1203	.description = "Permit use of TPIDR_EL3 for the TLS base",
1172	.dependencies = featureSet(&[_]Feature{}),	1204	.dependencies = featureSet(&[_]Feature{}),
1173	};	1205	};
		1206	result[@intFromEnum(Feature.tpidrro_el0)] = .{
		1207	.llvm_name = "tpidrro-el0",
		1208	.description = "Permit use of TPIDRRO_EL0 for the TLS base",
		1209	.dependencies = featureSet(&[_]Feature{}),
		1210	};
1174	result[@intFromEnum(Feature.tracev8_4)] = .{	1211	result[@intFromEnum(Feature.tracev8_4)] = .{
1175	.llvm_name = "tracev8.4",	1212	.llvm_name = "tracev8.4",
1176	.description = "Enable v8.4-A Trace extension (FEAT_TRF)",	1213	.description = "Enable v8.4-A Trace extension (FEAT_TRF)",
...	@@ -1311,6 +1348,7 @@ pub const all_features = blk: {	...	@@ -1311,6 +1348,7 @@ pub const all_features = blk: {
1311	.llvm_name = "v8.9a",	1348	.llvm_name = "v8.9a",
1312	.description = "Support ARM v8.9a instructions",	1349	.description = "Support ARM v8.9a instructions",
1313	.dependencies = featureSet(&[_]Feature{	1350	.dependencies = featureSet(&[_]Feature{
		1351	.chk,
1314	.clrbhb,	1352	.clrbhb,
1315	.cssc,	1353	.cssc,
1316	.prfm_slc_target,	1354	.prfm_slc_target,
...	@@ -1974,6 +2012,7 @@ pub const cpu = struct {	...	@@ -1974,6 +2012,7 @@ pub const cpu = struct {
1974	.lsl_fast,	2012	.lsl_fast,
1975	.mte,	2013	.mte,
1976	.perfmon,	2014	.perfmon,
		2015	.predictable_select_expensive,
1977	.spe,	2016	.spe,
1978	.sve2_bitperm,	2017	.sve2_bitperm,
1979	.use_postra_scheduler,	2018	.use_postra_scheduler,
...	@@ -1991,6 +2030,7 @@ pub const cpu = struct {	...	@@ -1991,6 +2030,7 @@ pub const cpu = struct {
1991	.fuse_aes,	2030	.fuse_aes,
1992	.fuse_literals,	2031	.fuse_literals,
1993	.perfmon,	2032	.perfmon,
		2033	.predictable_select_expensive,
1994	.v8a,	2034	.v8a,
1995	}),	2035	}),
1996	};	2036	};
...	@@ -2004,6 +2044,7 @@ pub const cpu = struct {	...	@@ -2004,6 +2044,7 @@ pub const cpu = struct {
2004	.fuse_adrp_add,	2044	.fuse_adrp_add,
2005	.fuse_aes,	2045	.fuse_aes,
2006	.perfmon,	2046	.perfmon,
		2047	.predictable_select_expensive,
2007	.v8a,	2048	.v8a,
2008	}),	2049	}),
2009	};	2050	};
...	@@ -2018,6 +2059,7 @@ pub const cpu = struct {	...	@@ -2018,6 +2059,7 @@ pub const cpu = struct {
2018	.fuse_adrp_add,	2059	.fuse_adrp_add,
2019	.fuse_aes,	2060	.fuse_aes,
2020	.perfmon,	2061	.perfmon,
		2062	.predictable_select_expensive,
2021	.rcpc,	2063	.rcpc,
2022	.v8_2a,	2064	.v8_2a,
2023	}),	2065	}),
...	@@ -2063,6 +2105,7 @@ pub const cpu = struct {	...	@@ -2063,6 +2105,7 @@ pub const cpu = struct {
2063	.fuse_aes,	2105	.fuse_aes,
2064	.lsl_fast,	2106	.lsl_fast,
2065	.perfmon,	2107	.perfmon,
		2108	.predictable_select_expensive,
2066	.rcpc,	2109	.rcpc,
2067	.ssbs,	2110	.ssbs,
2068	.v8_2a,	2111	.v8_2a,
...	@@ -2126,6 +2169,7 @@ pub const cpu = struct {	...	@@ -2126,6 +2169,7 @@ pub const cpu = struct {
2126	.fuse_aes,	2169	.fuse_aes,
2127	.lsl_fast,	2170	.lsl_fast,
2128	.perfmon,	2171	.perfmon,
		2172	.predictable_select_expensive,
2129	.rcpc,	2173	.rcpc,
2130	.spe,	2174	.spe,
2131	.ssbs,	2175	.ssbs,
...	@@ -2149,6 +2193,7 @@ pub const cpu = struct {	...	@@ -2149,6 +2193,7 @@ pub const cpu = struct {
2149	.lsl_fast,	2193	.lsl_fast,
2150	.pauth,	2194	.pauth,
2151	.perfmon,	2195	.perfmon,
		2196	.predictable_select_expensive,
2152	.rcpc_immo,	2197	.rcpc_immo,
2153	.spe,	2198	.spe,
2154	.ssbs,	2199	.ssbs,
...	@@ -2171,6 +2216,7 @@ pub const cpu = struct {	...	@@ -2171,6 +2216,7 @@ pub const cpu = struct {
2171	.lsl_fast,	2216	.lsl_fast,
2172	.mte,	2217	.mte,
2173	.perfmon,	2218	.perfmon,
		2219	.predictable_select_expensive,
2174	.sve2_bitperm,	2220	.sve2_bitperm,
2175	.use_postra_scheduler,	2221	.use_postra_scheduler,
2176	.v9a,	2222	.v9a,
...	@@ -2190,6 +2236,7 @@ pub const cpu = struct {	...	@@ -2190,6 +2236,7 @@ pub const cpu = struct {
2190	.lsl_fast,	2236	.lsl_fast,
2191	.mte,	2237	.mte,
2192	.perfmon,	2238	.perfmon,
		2239	.predictable_select_expensive,
2193	.spe,	2240	.spe,
2194	.sve2_bitperm,	2241	.sve2_bitperm,
2195	.use_postra_scheduler,	2242	.use_postra_scheduler,
...	@@ -2383,6 +2430,7 @@ pub const cpu = struct {	...	@@ -2383,6 +2430,7 @@ pub const cpu = struct {
2383	.i8mm,	2430	.i8mm,
2384	.lsl_fast,	2431	.lsl_fast,
2385	.perfmon,	2432	.perfmon,
		2433	.predictable_select_expensive,
2386	.rand,	2434	.rand,
2387	.spe,	2435	.spe,
2388	.ssbs,	2436	.ssbs,
...	@@ -2419,6 +2467,7 @@ pub const cpu = struct {	...	@@ -2419,6 +2467,7 @@ pub const cpu = struct {
2419	.fuse_aes,	2467	.fuse_aes,
2420	.lsl_fast,	2468	.lsl_fast,
2421	.perfmon,	2469	.perfmon,
		2470	.predictable_select_expensive,
2422	.rcpc,	2471	.rcpc,
2423	.spe,	2472	.spe,
2424	.ssbs,	2473	.ssbs,
...	@@ -2440,6 +2489,7 @@ pub const cpu = struct {	...	@@ -2440,6 +2489,7 @@ pub const cpu = struct {
2440	.lsl_fast,	2489	.lsl_fast,
2441	.mte,	2490	.mte,
2442	.perfmon,	2491	.perfmon,
		2492	.predictable_select_expensive,
2443	.sve2_bitperm,	2493	.sve2_bitperm,
2444	.use_postra_scheduler,	2494	.use_postra_scheduler,
2445	.v8_5a,	2495	.v8_5a,
...	@@ -2458,7 +2508,9 @@ pub const cpu = struct {	...	@@ -2458,7 +2508,9 @@ pub const cpu = struct {
2458	.fuse_aes,	2508	.fuse_aes,
2459	.i8mm,	2509	.i8mm,
2460	.lsl_fast,	2510	.lsl_fast,
		2511	.no_sve_fp_ld1r,
2461	.perfmon,	2512	.perfmon,
		2513	.predictable_select_expensive,
2462	.rand,	2514	.rand,
2463	.spe,	2515	.spe,
2464	.ssbs,	2516	.ssbs,
...	@@ -2480,6 +2532,7 @@ pub const cpu = struct {	...	@@ -2480,6 +2532,7 @@ pub const cpu = struct {
2480	.lsl_fast,	2532	.lsl_fast,
2481	.mte,	2533	.mte,
2482	.perfmon,	2534	.perfmon,
		2535	.predictable_select_expensive,
2483	.rand,	2536	.rand,
2484	.spe,	2537	.spe,
2485	.sve2_bitperm,	2538	.sve2_bitperm,

lib/std/target/amdgpu.zig+215-35

 @@ -10,14 +10,20 @@ pub const Feature = enum {
     add_no_carry_insts,
     aperture_regs,
     architected_flat_scratch,
+    architected_sgprs,
+    atomic_buffer_global_pk_add_f16_insts,
+    atomic_buffer_global_pk_add_f16_no_rtn_insts,
+    atomic_ds_pk_add_16_insts,
     atomic_fadd_no_rtn_insts,
     atomic_fadd_rtn_insts,
-    atomic_pk_fadd_no_rtn_insts,
+    atomic_flat_pk_add_16_insts,
+    atomic_global_pk_add_bf16_inst,
     auto_waitcnt_before_barrier,
     back_off_barrier,
     ci_insts,
     cumode,
     dl_insts,
+    dot10_insts,
     dot1_insts,
     dot2_insts,
     dot3_insts,
 @@ -46,6 +52,7 @@ pub const Feature = enum {
     fma_mix_insts,
     fmacf64_inst,
     fmaf,
+    force_store_sc0_sc1,
     fp64,
     fp8_insts,
     full_rate_64_ops,
 @@ -96,12 +103,11 @@ pub const Feature = enum {
     no_sdst_cmpx,
     nsa_clause_bug,
     nsa_encoding,
-    nsa_max_size_13,
-    nsa_max_size_5,
     nsa_to_vmem_bug,
     offset_3f_bug,
     packed_fp32_ops,
     packed_tid,
+    partial_nsa_encoding,
     pk_fmac_f16_inst,
     promote_alloca,
     prt_strict_null,
 @@ -187,6 +193,30 @@ pub const all_features = blk: {
         .description = "Flat Scratch register is a readonly SPI initialized architected register",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.architected_sgprs)] = .{
+        .llvm_name = "architected-sgprs",
+        .description = "Enable the architected SGPRs",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_insts)] = .{
+        .llvm_name = "atomic-buffer-global-pk-add-f16-insts",
+        .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that can return original value",
+        .dependencies = featureSet(&[_]Feature{
+            .flat_global_insts,
+        }),
+    };
+    result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_no_rtn_insts)] = .{
+        .llvm_name = "atomic-buffer-global-pk-add-f16-no-rtn-insts",
+        .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that don't return original value",
+        .dependencies = featureSet(&[_]Feature{
+            .flat_global_insts,
+        }),
+    };
+    result[@intFromEnum(Feature.atomic_ds_pk_add_16_insts)] = .{
+        .llvm_name = "atomic-ds-pk-add-16-insts",
+        .description = "Has ds_pk_add_bf16, ds_pk_add_f16, ds_pk_add_rtn_bf16, ds_pk_add_rtn_f16 instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@intFromEnum(Feature.atomic_fadd_no_rtn_insts)] = .{
         .llvm_name = "atomic-fadd-no-rtn-insts",
         .description = "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that don't return original value",
 @@ -201,9 +231,14 @@ pub const all_features = blk: {
             .flat_global_insts,
         }),
     };
-    result[@intFromEnum(Feature.atomic_pk_fadd_no_rtn_insts)] = .{
+    result[@intFromEnum(Feature.atomic_flat_pk_add_16_insts)] = .{
-        .llvm_name = "atomic-pk-fadd-no-rtn-insts",
+        .llvm_name = "atomic-flat-pk-add-16-insts",
-        .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that don't return original value",
+        .description = "Has flat_atomic_pk_add_f16 and flat_atomic_pk_add_bf16 instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@intFromEnum(Feature.atomic_global_pk_add_bf16_inst)] = .{
+        .llvm_name = "atomic-global-pk-add-bf16-inst",
+        .description = "Has global_atomic_pk_add_bf16 instruction",
         .dependencies = featureSet(&[_]Feature{
             .flat_global_insts,
         }),
 @@ -233,6 +268,11 @@ pub const all_features = blk: {
         .description = "Has v_fmac_f32 and v_xnor_b32 instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.dot10_insts)] = .{
+        .llvm_name = "dot10-insts",
+        .description = "Has v_dot2_f32_f16 instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@intFromEnum(Feature.dot1_insts)] = .{
         .llvm_name = "dot1-insts",
         .description = "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions",
 @@ -265,7 +305,7 @@ pub const all_features = blk: {
     };
     result[@intFromEnum(Feature.dot7_insts)] = .{
         .llvm_name = "dot7-insts",
-        .description = "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions",
+        .description = "Has v_dot4_u32_u8, v_dot8_u32_u4 instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.dot8_insts)] = .{
 @@ -373,6 +413,11 @@ pub const all_features = blk: {
         .description = "Enable single precision FMA (not as fast as mul+add, but fused)",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.force_store_sc0_sc1)] = .{
+        .llvm_name = "force-store-sc0-sc1",
+        .description = "Has SC0 and SC1 on stores",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@intFromEnum(Feature.fp64)] = .{
         .llvm_name = "fp64",
         .description = "Enable double precision operations",
 @@ -742,16 +787,6 @@ pub const all_features = blk: {
         .description = "Support NSA encoding for image instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@intFromEnum(Feature.nsa_max_size_13)] = .{
-        .llvm_name = "nsa-max-size-13",
-        .description = "The maximum non-sequential address size in VGPRs.",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@intFromEnum(Feature.nsa_max_size_5)] = .{
-        .llvm_name = "nsa-max-size-5",
-        .description = "The maximum non-sequential address size in VGPRs.",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@intFromEnum(Feature.nsa_to_vmem_bug)] = .{
         .llvm_name = "nsa-to-vmem-bug",
         .description = "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero",
 @@ -772,6 +807,11 @@ pub const all_features = blk: {
         .description = "Workitem IDs are packed into v0 at kernel launch",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.partial_nsa_encoding)] = .{
+        .llvm_name = "partial-nsa-encoding",
+        .description = "Support partial NSA encoding for image instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@intFromEnum(Feature.pk_fmac_f16_inst)] = .{
         .llvm_name = "pk-fmac-f16-inst",
         .description = "Has v_pk_fmac_f16 instruction",
 @@ -1146,7 +1186,6 @@ pub const cpu = struct {
             .negative_unaligned_scratch_offset_bug,
             .nsa_clause_bug,
             .nsa_encoding,
-            .nsa_max_size_5,
             .nsa_to_vmem_bug,
             .offset_3f_bug,
             .scalar_atomics,
 @@ -1166,6 +1205,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .back_off_barrier,
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot5_insts,
 @@ -1183,7 +1223,6 @@ pub const cpu = struct {
             .negative_unaligned_scratch_offset_bug,
             .nsa_clause_bug,
             .nsa_encoding,
-            .nsa_max_size_5,
             .nsa_to_vmem_bug,
             .offset_3f_bug,
             .scalar_atomics,
 @@ -1203,6 +1242,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .back_off_barrier,
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot5_insts,
 @@ -1220,7 +1260,6 @@ pub const cpu = struct {
             .negative_unaligned_scratch_offset_bug,
             .nsa_clause_bug,
             .nsa_encoding,
-            .nsa_max_size_5,
             .nsa_to_vmem_bug,
             .offset_3f_bug,
             .scalar_atomics,
 @@ -1253,7 +1292,6 @@ pub const cpu = struct {
             .negative_unaligned_scratch_offset_bug,
             .nsa_clause_bug,
             .nsa_encoding,
-            .nsa_max_size_5,
             .nsa_to_vmem_bug,
             .offset_3f_bug,
             .scalar_atomics,
 @@ -1273,6 +1311,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .back_off_barrier,
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot5_insts,
 @@ -1284,7 +1323,6 @@ pub const cpu = struct {
             .gfx10_b_encoding,
             .ldsbankcount32,
             .nsa_encoding,
-            .nsa_max_size_13,
             .shader_cycles_register,
             .wavefrontsize32,
         }),
 @@ -1295,6 +1333,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .back_off_barrier,
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot5_insts,
 @@ -1306,7 +1345,6 @@ pub const cpu = struct {
             .gfx10_b_encoding,
             .ldsbankcount32,
             .nsa_encoding,
-            .nsa_max_size_13,
             .shader_cycles_register,
             .wavefrontsize32,
         }),
 @@ -1317,6 +1355,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .back_off_barrier,
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot5_insts,
 @@ -1328,7 +1367,6 @@ pub const cpu = struct {
             .gfx10_b_encoding,
             .ldsbankcount32,
             .nsa_encoding,
-            .nsa_max_size_13,
             .shader_cycles_register,
             .wavefrontsize32,
         }),
 @@ -1339,6 +1377,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .back_off_barrier,
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot5_insts,
 @@ -1350,7 +1389,6 @@ pub const cpu = struct {
             .gfx10_b_encoding,
             .ldsbankcount32,
             .nsa_encoding,
-            .nsa_max_size_13,
             .shader_cycles_register,
             .wavefrontsize32,
         }),
 @@ -1361,6 +1399,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .back_off_barrier,
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot5_insts,
 @@ -1372,7 +1411,6 @@ pub const cpu = struct {
             .gfx10_b_encoding,
             .ldsbankcount32,
             .nsa_encoding,
-            .nsa_max_size_13,
             .shader_cycles_register,
             .wavefrontsize32,
         }),
 @@ -1383,6 +1421,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .back_off_barrier,
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot5_insts,
 @@ -1394,7 +1433,6 @@ pub const cpu = struct {
             .gfx10_b_encoding,
             .ldsbankcount32,
             .nsa_encoding,
-            .nsa_max_size_13,
             .shader_cycles_register,
             .wavefrontsize32,
         }),
 @@ -1405,6 +1443,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .back_off_barrier,
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot5_insts,
 @@ -1416,7 +1455,6 @@ pub const cpu = struct {
             .gfx10_b_encoding,
             .ldsbankcount32,
             .nsa_encoding,
-            .nsa_max_size_13,
             .shader_cycles_register,
             .wavefrontsize32,
         }),
 @@ -1429,6 +1467,7 @@ pub const cpu = struct {
             .atomic_fadd_no_rtn_insts,
             .atomic_fadd_rtn_insts,
             .dl_insts,
+            .dot10_insts,
             .dot5_insts,
             .dot7_insts,
             .dot8_insts,
 @@ -1440,8 +1479,8 @@ pub const cpu = struct {
             .ldsbankcount32,
             .mad_intra_fwd_bug,
             .nsa_encoding,
-            .nsa_max_size_5,
             .packed_tid,
+            .partial_nsa_encoding,
             .shader_cycles_register,
             .user_sgpr_init16_bug,
             .valu_trans_use_hazard,
 @@ -1457,6 +1496,7 @@ pub const cpu = struct {
             .atomic_fadd_no_rtn_insts,
             .atomic_fadd_rtn_insts,
             .dl_insts,
+            .dot10_insts,
             .dot5_insts,
             .dot7_insts,
             .dot8_insts,
 @@ -1468,8 +1508,8 @@ pub const cpu = struct {
             .ldsbankcount32,
             .mad_intra_fwd_bug,
             .nsa_encoding,
-            .nsa_max_size_5,
             .packed_tid,
+            .partial_nsa_encoding,
             .shader_cycles_register,
             .valu_trans_use_hazard,
             .vcmpx_permlane_hazard,
 @@ -1484,6 +1524,7 @@ pub const cpu = struct {
             .atomic_fadd_no_rtn_insts,
             .atomic_fadd_rtn_insts,
             .dl_insts,
+            .dot10_insts,
             .dot5_insts,
             .dot7_insts,
             .dot8_insts,
 @@ -1494,8 +1535,8 @@ pub const cpu = struct {
             .ldsbankcount32,
             .mad_intra_fwd_bug,
             .nsa_encoding,
-            .nsa_max_size_5,
             .packed_tid,
+            .partial_nsa_encoding,
             .shader_cycles_register,
             .user_sgpr_init16_bug,
             .valu_trans_use_hazard,
 @@ -1511,6 +1552,7 @@ pub const cpu = struct {
             .atomic_fadd_no_rtn_insts,
             .atomic_fadd_rtn_insts,
             .dl_insts,
+            .dot10_insts,
             .dot5_insts,
             .dot7_insts,
             .dot8_insts,
 @@ -1521,14 +1563,67 @@ pub const cpu = struct {
             .ldsbankcount32,
             .mad_intra_fwd_bug,
             .nsa_encoding,
-            .nsa_max_size_5,
             .packed_tid,
+            .partial_nsa_encoding,
             .shader_cycles_register,
             .valu_trans_use_hazard,
             .vcmpx_permlane_hazard,
             .wavefrontsize32,
         }),
     };
+    pub const gfx1150 = CpuModel{
+        .name = "gfx1150",
+        .llvm_name = "gfx1150",
+        .features = featureSet(&[_]Feature{
+            .architected_flat_scratch,
+            .atomic_fadd_no_rtn_insts,
+            .atomic_fadd_rtn_insts,
+            .dl_insts,
+            .dot10_insts,
+            .dot5_insts,
+            .dot7_insts,
+            .dot8_insts,
+            .dot9_insts,
+            .flat_atomic_fadd_f32_inst,
+            .gfx11,
+            .image_insts,
+            .ldsbankcount32,
+            .mad_intra_fwd_bug,
+            .nsa_encoding,
+            .packed_tid,
+            .partial_nsa_encoding,
+            .shader_cycles_register,
+            .vcmpx_permlane_hazard,
+            .wavefrontsize32,
+        }),
+    };
+    pub const gfx1151 = CpuModel{
+        .name = "gfx1151",
+        .llvm_name = "gfx1151",
+        .features = featureSet(&[_]Feature{
+            .architected_flat_scratch,
+            .atomic_fadd_no_rtn_insts,
+            .atomic_fadd_rtn_insts,
+            .dl_insts,
+            .dot10_insts,
+            .dot5_insts,
+            .dot7_insts,
+            .dot8_insts,
+            .dot9_insts,
+            .flat_atomic_fadd_f32_inst,
+            .gfx11,
+            .gfx11_full_vgprs,
+            .image_insts,
+            .ldsbankcount32,
+            .mad_intra_fwd_bug,
+            .nsa_encoding,
+            .packed_tid,
+            .partial_nsa_encoding,
+            .shader_cycles_register,
+            .vcmpx_permlane_hazard,
+            .wavefrontsize32,
+        }),
+    };
     pub const gfx600 = CpuModel{
         .name = "gfx600",
         .llvm_name = "gfx600",
 @@ -1702,6 +1797,7 @@ pub const cpu = struct {
         .llvm_name = "gfx906",
         .features = featureSet(&[_]Feature{
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot7_insts,
 @@ -1721,9 +1817,10 @@ pub const cpu = struct {
         .name = "gfx908",
         .llvm_name = "gfx908",
         .features = featureSet(&[_]Feature{
+            .atomic_buffer_global_pk_add_f16_no_rtn_insts,
             .atomic_fadd_no_rtn_insts,
-            .atomic_pk_fadd_no_rtn_insts,
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot3_insts,
 @@ -1764,11 +1861,12 @@ pub const cpu = struct {
         .name = "gfx90a",
         .llvm_name = "gfx90a",
         .features = featureSet(&[_]Feature{
+            .atomic_buffer_global_pk_add_f16_insts,
             .atomic_fadd_no_rtn_insts,
             .atomic_fadd_rtn_insts,
-            .atomic_pk_fadd_no_rtn_insts,
             .back_off_barrier,
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot3_insts,
 @@ -1811,11 +1909,93 @@ pub const cpu = struct {
         .llvm_name = "gfx940",
         .features = featureSet(&[_]Feature{
             .architected_flat_scratch,
+            .atomic_buffer_global_pk_add_f16_insts,
+            .atomic_ds_pk_add_16_insts,
+            .atomic_fadd_no_rtn_insts,
+            .atomic_fadd_rtn_insts,
+            .atomic_flat_pk_add_16_insts,
+            .atomic_global_pk_add_bf16_inst,
+            .back_off_barrier,
+            .dl_insts,
+            .dot10_insts,
+            .dot1_insts,
+            .dot2_insts,
+            .dot3_insts,
+            .dot4_insts,
+            .dot5_insts,
+            .dot6_insts,
+            .dot7_insts,
+            .dpp_64bit,
+            .flat_atomic_fadd_f32_inst,
+            .fma_mix_insts,
+            .fmacf64_inst,
+            .force_store_sc0_sc1,
+            .fp8_insts,
+            .full_rate_64_ops,
+            .gfx9,
+            .gfx90a_insts,
+            .gfx940_insts,
+            .ldsbankcount32,
+            .mai_insts,
+            .packed_fp32_ops,
+            .packed_tid,
+            .pk_fmac_f16_inst,
+            .sramecc_support,
+        }),
+    };
+    pub const gfx941 = CpuModel{
+        .name = "gfx941",
+        .llvm_name = "gfx941",
+        .features = featureSet(&[_]Feature{
+            .architected_flat_scratch,
+            .atomic_buffer_global_pk_add_f16_insts,
+            .atomic_ds_pk_add_16_insts,
+            .atomic_fadd_no_rtn_insts,
+            .atomic_fadd_rtn_insts,
+            .atomic_flat_pk_add_16_insts,
+            .atomic_global_pk_add_bf16_inst,
+            .back_off_barrier,
+            .dl_insts,
+            .dot10_insts,
+            .dot1_insts,
+            .dot2_insts,
+            .dot3_insts,
+            .dot4_insts,
+            .dot5_insts,
+            .dot6_insts,
+            .dot7_insts,
+            .dpp_64bit,
+            .flat_atomic_fadd_f32_inst,
+            .fma_mix_insts,
+            .fmacf64_inst,
+            .force_store_sc0_sc1,
+            .fp8_insts,
+            .full_rate_64_ops,
+            .gfx9,
+            .gfx90a_insts,
+            .gfx940_insts,
+            .ldsbankcount32,
+            .mai_insts,
+            .packed_fp32_ops,
+            .packed_tid,
+            .pk_fmac_f16_inst,
+            .sramecc_support,
+        }),
+    };
+    pub const gfx942 = CpuModel{
+        .name = "gfx942",
+        .llvm_name = "gfx942",
+        .features = featureSet(&[_]Feature{
+            .architected_flat_scratch,
+            .atomic_buffer_global_pk_add_f16_insts,
+            .atomic_ds_pk_add_16_insts,
             .atomic_fadd_no_rtn_insts,
             .atomic_fadd_rtn_insts,
-            .atomic_pk_fadd_no_rtn_insts,
+            .atomic_flat_pk_add_16_insts,
+            .atomic_global_pk_add_bf16_inst,
             .back_off_barrier,
             .dl_insts,
+            .dot10_insts,
             .dot1_insts,
             .dot2_insts,
             .dot3_insts,

lib/std/target/arm.zig+16-4

 @@ -122,7 +122,9 @@ pub const Feature = enum {
     r4,
     ras,
     rclass,
-    read_tp_hard,
+    read_tp_tpidrprw,
+    read_tp_tpidruro,
+    read_tp_tpidrurw,
     reserve_r9,
     ret_addr_stack,
     sb,
 @@ -949,9 +951,19 @@ pub const all_features = blk: {
         .description = "Is realtime profile ('R' series)",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@intFromEnum(Feature.read_tp_hard)] = .{
+    result[@intFromEnum(Feature.read_tp_tpidrprw)] = .{
-        .llvm_name = "read-tp-hard",
+        .llvm_name = "read-tp-tpidrprw",
-        .description = "Reading thread pointer from register",
+        .description = "Reading thread pointer from TPIDRPRW register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@intFromEnum(Feature.read_tp_tpidruro)] = .{
+        .llvm_name = "read-tp-tpidruro",
+        .description = "Reading thread pointer from TPIDRURO register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@intFromEnum(Feature.read_tp_tpidrurw)] = .{
+        .llvm_name = "read-tp-tpidrurw",
+        .description = "Reading thread pointer from TPIDRURW register",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.reserve_r9)] = .{

lib/std/target/avr.zig+8-9

 @@ -25,12 +25,12 @@ pub const Feature = enum {
     elpmx,
     ijmpcall,
     jmpcall,
+    lowbytefirst,
     lpm,
     lpmx,
     memmappedregs,
     movw,
     mul,
-    progmem,
     rmw,
     smallstack,
     special,
 @@ -69,7 +69,6 @@ pub const all_features = blk: {
             .avr0,
             .lpm,
             .memmappedregs,
-            .progmem,
         }),
     };
     result[@intFromEnum(Feature.avr2)] = .{
 @@ -207,6 +206,11 @@ pub const all_features = blk: {
         .description = "The device supports the `JMP` and `CALL` instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.lowbytefirst)] = .{
+        .llvm_name = "lowbytefirst",
+        .description = "Do the low byte first when writing a 16-bit port or storing a 16-bit word",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@intFromEnum(Feature.lpm)] = .{
         .llvm_name = "lpm",
         .description = "The device supports the `LPM` instruction",
 @@ -232,11 +236,6 @@ pub const all_features = blk: {
         .description = "The device supports the multiplication instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@intFromEnum(Feature.progmem)] = .{
-        .llvm_name = "progmem",
-        .description = "The device has a separate flash namespace",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@intFromEnum(Feature.rmw)] = .{
         .llvm_name = "rmw",
         .description = "The device supports the read-write-modify instructions: XCH, LAS, LAC, LAT",
 @@ -303,11 +302,11 @@ pub const all_features = blk: {
             .elpmx,
             .ijmpcall,
             .jmpcall,
+            .lowbytefirst,
             .lpm,
             .lpmx,
             .movw,
             .mul,
-            .progmem,
             .spm,
             .spmx,
             .sram,
 @@ -322,11 +321,11 @@ pub const all_features = blk: {
             .@"break",
             .ijmpcall,
             .jmpcall,
+            .lowbytefirst,
             .lpm,
             .lpmx,
             .movw,
             .mul,
-            .progmem,
             .sram,
         }),
     };

lib/std/target/bpf.zig+3-1

...	@@ -66,6 +66,8 @@ pub const cpu = struct {	...	@@ -66,6 +66,8 @@ pub const cpu = struct {
66	pub const v3 = CpuModel{	66	pub const v3 = CpuModel{
67	.name = "v3",	67	.name = "v3",
68	.llvm_name = "v3",	68	.llvm_name = "v3",
69	.features = featureSet(&[_]Feature{}),	69	.features = featureSet(&[_]Feature{
		70	.alu32,
		71	}),
70	};	72	};
71	};	73	};

lib/std/target/csky.zig+10-10

lib/std/target/loongarch.zig+17

 @@ -16,6 +16,7 @@ pub const Feature = enum {
     lbt,
     lsx,
     lvz,
+    ual,
 };
 pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
 @@ -88,6 +89,11 @@ pub const all_features = blk: {
         .description = "'LVZ' (Loongson Virtualization Extension)",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.ual)] = .{
+        .llvm_name = "ual",
+        .description = "Allow memory accesses to be unaligned",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     const ti = @typeInfo(Feature);
     for (&result, 0..) |*elem, i| {
         elem.index = i;
 @@ -114,6 +120,7 @@ pub const cpu = struct {
         .llvm_name = "generic-la64",
         .features = featureSet(&[_]Feature{
             .@"64bit",
+            .ual,
         }),
     };
     pub const la464 = CpuModel{
 @@ -124,6 +131,16 @@ pub const cpu = struct {
             .lasx,
             .lbt,
             .lvz,
+            .ual,
+        }),
+    };
+    pub const loongarch64 = CpuModel{
+        .name = "loongarch64",
+        .llvm_name = "loongarch64",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .d,
+            .ual,
         }),
     };
 };

lib/std/target/m68k.zig+15

 @@ -11,6 +11,8 @@ pub const Feature = enum {
     isa_68030,
     isa_68040,
     isa_68060,
+    isa_68881,
+    isa_68882,
     reserve_a0,
     reserve_a1,
     reserve_a2,
 @@ -68,6 +70,7 @@ pub const all_features = blk: {
         .description = "Is M68040 ISA supported",
         .dependencies = featureSet(&[_]Feature{
             .isa_68030,
+            .isa_68882,
         }),
     };
     result[@intFromEnum(Feature.isa_68060)] = .{
 @@ -77,6 +80,18 @@ pub const all_features = blk: {
             .isa_68040,
         }),
     };
+    result[@intFromEnum(Feature.isa_68881)] = .{
+        .llvm_name = "isa-68881",
+        .description = "Is M68881 (FPU) ISA supported",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@intFromEnum(Feature.isa_68882)] = .{
+        .llvm_name = "isa-68882",
+        .description = "Is M68882 (FPU) ISA supported",
+        .dependencies = featureSet(&[_]Feature{
+            .isa_68881,
+        }),
+    };
     result[@intFromEnum(Feature.reserve_a0)] = .{
         .llvm_name = "reserve-a0",
         .description = "Reserve A0 register",

lib/std/target/nvptx.zig+66-40

 @@ -25,6 +25,8 @@ pub const Feature = enum {
     ptx76,
     ptx77,
     ptx78,
+    ptx80,
+    ptx81,
     sm_20,
     sm_21,
     sm_30,
 @@ -45,6 +47,7 @@ pub const Feature = enum {
     sm_87,
     sm_89,
     sm_90,
+    sm_90,
 };
 pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
 @@ -58,202 +61,217 @@ pub const all_features = blk: {
     var result: [len]CpuFeature = undefined;
     result[@intFromEnum(Feature.ptx32)] = .{
         .llvm_name = "ptx32",
-        .description = "Use PTX version 3.2",
+        .description = "Use PTX version 32",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx40)] = .{
         .llvm_name = "ptx40",
-        .description = "Use PTX version 4.0",
+        .description = "Use PTX version 40",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx41)] = .{
         .llvm_name = "ptx41",
-        .description = "Use PTX version 4.1",
+        .description = "Use PTX version 41",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx42)] = .{
         .llvm_name = "ptx42",
-        .description = "Use PTX version 4.2",
+        .description = "Use PTX version 42",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx43)] = .{
         .llvm_name = "ptx43",
-        .description = "Use PTX version 4.3",
+        .description = "Use PTX version 43",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx50)] = .{
         .llvm_name = "ptx50",
-        .description = "Use PTX version 5.0",
+        .description = "Use PTX version 50",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx60)] = .{
         .llvm_name = "ptx60",
-        .description = "Use PTX version 6.0",
+        .description = "Use PTX version 60",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx61)] = .{
         .llvm_name = "ptx61",
-        .description = "Use PTX version 6.1",
+        .description = "Use PTX version 61",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx63)] = .{
         .llvm_name = "ptx63",
-        .description = "Use PTX version 6.3",
+        .description = "Use PTX version 63",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx64)] = .{
         .llvm_name = "ptx64",
-        .description = "Use PTX version 6.4",
+        .description = "Use PTX version 64",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx65)] = .{
         .llvm_name = "ptx65",
-        .description = "Use PTX version 6.5",
+        .description = "Use PTX version 65",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx70)] = .{
         .llvm_name = "ptx70",
-        .description = "Use PTX version 7.0",
+        .description = "Use PTX version 70",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx71)] = .{
         .llvm_name = "ptx71",
-        .description = "Use PTX version 7.1",
+        .description = "Use PTX version 71",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx72)] = .{
         .llvm_name = "ptx72",
-        .description = "Use PTX version 7.2",
+        .description = "Use PTX version 72",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx73)] = .{
         .llvm_name = "ptx73",
-        .description = "Use PTX version 7.3",
+        .description = "Use PTX version 73",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx74)] = .{
         .llvm_name = "ptx74",
-        .description = "Use PTX version 7.4",
+        .description = "Use PTX version 74",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx75)] = .{
         .llvm_name = "ptx75",
-        .description = "Use PTX version 7.5",
+        .description = "Use PTX version 75",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx76)] = .{
         .llvm_name = "ptx76",
-        .description = "Use PTX version 7.6",
+        .description = "Use PTX version 76",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx77)] = .{
         .llvm_name = "ptx77",
-        .description = "Use PTX version 7.7",
+        .description = "Use PTX version 77",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.ptx78)] = .{
         .llvm_name = "ptx78",
-        .description = "Use PTX version 7.8",
+        .description = "Use PTX version 78",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@intFromEnum(Feature.ptx80)] = .{
+        .llvm_name = "ptx80",
+        .description = "Use PTX version 80",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@intFromEnum(Feature.ptx81)] = .{
+        .llvm_name = "ptx81",
+        .description = "Use PTX version 81",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_20)] = .{
         .llvm_name = "sm_20",
-        .description = "Target SM 2.0",
+        .description = "Target SM 20",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_21)] = .{
         .llvm_name = "sm_21",
-        .description = "Target SM 2.1",
+        .description = "Target SM 21",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_30)] = .{
         .llvm_name = "sm_30",
-        .description = "Target SM 3.0",
+        .description = "Target SM 30",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_32)] = .{
         .llvm_name = "sm_32",
-        .description = "Target SM 3.2",
+        .description = "Target SM 32",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_35)] = .{
         .llvm_name = "sm_35",
-        .description = "Target SM 3.5",
+        .description = "Target SM 35",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_37)] = .{
         .llvm_name = "sm_37",
-        .description = "Target SM 3.7",
+        .description = "Target SM 37",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_50)] = .{
         .llvm_name = "sm_50",
-        .description = "Target SM 5.0",
+        .description = "Target SM 50",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_52)] = .{
         .llvm_name = "sm_52",
-        .description = "Target SM 5.2",
+        .description = "Target SM 52",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_53)] = .{
         .llvm_name = "sm_53",
-        .description = "Target SM 5.3",
+        .description = "Target SM 53",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_60)] = .{
         .llvm_name = "sm_60",
-        .description = "Target SM 6.0",
+        .description = "Target SM 60",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_61)] = .{
         .llvm_name = "sm_61",
-        .description = "Target SM 6.1",
+        .description = "Target SM 61",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_62)] = .{
         .llvm_name = "sm_62",
-        .description = "Target SM 6.2",
+        .description = "Target SM 62",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_70)] = .{
         .llvm_name = "sm_70",
-        .description = "Target SM 7.0",
+        .description = "Target SM 70",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_72)] = .{
         .llvm_name = "sm_72",
-        .description = "Target SM 7.2",
+        .description = "Target SM 72",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_75)] = .{
         .llvm_name = "sm_75",
-        .description = "Target SM 7.5",
+        .description = "Target SM 75",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_80)] = .{
         .llvm_name = "sm_80",
-        .description = "Target SM 8.0",
+        .description = "Target SM 80",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_86)] = .{
         .llvm_name = "sm_86",
-        .description = "Target SM 8.6",
+        .description = "Target SM 86",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_87)] = .{
         .llvm_name = "sm_87",
-        .description = "Target SM 8.7",
+        .description = "Target SM 87",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_89)] = .{
         .llvm_name = "sm_89",
-        .description = "Target SM 8.9",
+        .description = "Target SM 89",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@intFromEnum(Feature.sm_90)] = .{
         .llvm_name = "sm_90",
-        .description = "Target SM 9.0",
+        .description = "Target SM 90",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@intFromEnum(Feature.sm_90)] = .{
+        .llvm_name = "sm_90",
+        .description = "Target SM 90",
         .dependencies = featureSet(&[_]Feature{}),
     };
     const ti = @typeInfo(Feature);
 @@ -424,4 +442,12 @@ pub const cpu = struct {
             .sm_90,
         }),
     };
+    pub const sm_90a = CpuModel{
+        .name = "sm_90a",
+        .llvm_name = "sm_90a",
+        .features = featureSet(&[_]Feature{
+            .ptx80,
+            .sm_90,
+        }),
+    };
 };

lib/std/target/riscv.zig+401-26

...	@@ -10,14 +10,33 @@ pub const Feature = enum {	...	@@ -10,14 +10,33 @@ pub const Feature = enum {
10	a,	10	a,
11	c,	11	c,
12	d,	12	d,
		13	dlen_factor_2,
13	e,	14	e,
14	experimental_zawrs,	15	experimental_smaia,
15	experimental_zca,	16	experimental_ssaia,
16	experimental_zcd,	17	experimental_zacas,
17	experimental_zcf,	18	experimental_zfa,
		19	experimental_zfbfmin,
		20	experimental_zicond,
18	experimental_zihintntl,	21	experimental_zihintntl,
19	experimental_ztso,	22	experimental_ztso,
20	experimental_zvfh,	23	experimental_zvbb,
		24	experimental_zvbc,
		25	experimental_zvfbfmin,
		26	experimental_zvfbfwma,
		27	experimental_zvkg,
		28	experimental_zvkn,
		29	experimental_zvknc,
		30	experimental_zvkned,
		31	experimental_zvkng,
		32	experimental_zvknha,
		33	experimental_zvknhb,
		34	experimental_zvks,
		35	experimental_zvksc,
		36	experimental_zvksed,
		37	experimental_zvksg,
		38	experimental_zvksh,
		39	experimental_zvkt,
21	f,	40	f,
22	forced_atomics,	41	forced_atomics,
23	h,	42	h,
...	@@ -59,15 +78,32 @@ pub const Feature = enum {	...	@@ -59,15 +78,32 @@ pub const Feature = enum {
59	reserve_x8,	78	reserve_x8,
60	reserve_x9,	79	reserve_x9,
61	save_restore,	80	save_restore,
		81	seq_cst_trailing_fence,
62	short_forward_branch_opt,	82	short_forward_branch_opt,
63	svinval,	83	svinval,
64	svnapot,	84	svnapot,
65	svpbmt,	85	svpbmt,
66	tagged_globals,	86	tagged_globals,
67	unaligned_scalar_mem,	87	unaligned_scalar_mem,
		88	unaligned_vector_mem,
68	v,	89	v,
		90	xcvbitmanip,
		91	xcvmac,
		92	xsfcie,
		93	xsfvcp,
		94	xtheadba,
		95	xtheadbb,
		96	xtheadbs,
		97	xtheadcmo,
		98	xtheadcondmov,
		99	xtheadfmemidx,
		100	xtheadmac,
		101	xtheadmemidx,
		102	xtheadmempair,
		103	xtheadsync,
69	xtheadvdot,	104	xtheadvdot,
70	xventanacondops,	105	xventanacondops,
		106	zawrs,
71	zba,	107	zba,
72	zbb,	108	zbb,
73	zbc,	109	zbc,
...	@@ -75,6 +111,13 @@ pub const Feature = enum {	...	@@ -75,6 +111,13 @@ pub const Feature = enum {
75	zbkc,	111	zbkc,
76	zbkx,	112	zbkx,
77	zbs,	113	zbs,
		114	zca,
		115	zcb,
		116	zcd,
		117	zce,
		118	zcf,
		119	zcmp,
		120	zcmt,
78	zdinx,	121	zdinx,
79	zfh,	122	zfh,
80	zfhmin,	123	zfhmin,
...	@@ -84,7 +127,11 @@ pub const Feature = enum {	...	@@ -84,7 +127,11 @@ pub const Feature = enum {
84	zicbom,	127	zicbom,
85	zicbop,	128	zicbop,
86	zicboz,	129	zicboz,
		130	zicntr,
		131	zicsr,
		132	zifencei,
87	zihintpause,	133	zihintpause,
		134	zihpm,
88	zk,	135	zk,
89	zkn,	136	zkn,
90	zknd,	137	zknd,
...	@@ -101,6 +148,7 @@ pub const Feature = enum {	...	@@ -101,6 +148,7 @@ pub const Feature = enum {
101	zve64d,	148	zve64d,
102	zve64f,	149	zve64f,
103	zve64x,	150	zve64x,
		151	zvfh,
104	zvl1024b,	152	zvl1024b,
105	zvl128b,	153	zvl128b,
106	zvl16384b,	154	zvl16384b,
...	@@ -151,34 +199,53 @@ pub const all_features = blk: {	...	@@ -151,34 +199,53 @@ pub const all_features = blk: {
151	.f,	199	.f,
152	}),	200	}),
153	};	201	};
		202	result[@intFromEnum(Feature.dlen_factor_2)] = .{
		203	.llvm_name = "dlen-factor-2",
		204	.description = "Vector unit DLEN(data path width) is half of VLEN",
		205	.dependencies = featureSet(&[_]Feature{}),
		206	};
154	result[@intFromEnum(Feature.e)] = .{	207	result[@intFromEnum(Feature.e)] = .{
155	.llvm_name = "e",	208	.llvm_name = "e",
156	.description = "Implements RV32E (provides 16 rather than 32 GPRs)",	209	.description = "Implements RV{32,64}E (provides 16 rather than 32 GPRs)",
157	.dependencies = featureSet(&[_]Feature{}),	210	.dependencies = featureSet(&[_]Feature{}),
158	};	211	};
159	result[@intFromEnum(Feature.experimental_zawrs)] = .{	212	result[@intFromEnum(Feature.experimental_smaia)] = .{
160	.llvm_name = "experimental-zawrs",	213	.llvm_name = "experimental-smaia",
161	.description = "'Zawrs' (Wait on Reservation Set)",	214	.description = "'Smaia' (Smaia encompasses all added CSRs and all modifications to interrupt response behavior that the AIA specifies for a hart, over all privilege levels.)",
162	.dependencies = featureSet(&[_]Feature{}),	215	.dependencies = featureSet(&[_]Feature{}),
163	};	216	};
164	result[@intFromEnum(Feature.experimental_zca)] = .{	217	result[@intFromEnum(Feature.experimental_ssaia)] = .{
165	.llvm_name = "experimental-zca",	218	.llvm_name = "experimental-ssaia",
166	.description = "'Zca' (part of the C extension, excluding compressed floating point loads/stores)",	219	.description = "'Ssaia' (Ssaia is essentially the same as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level.)",
167	.dependencies = featureSet(&[_]Feature{}),	220	.dependencies = featureSet(&[_]Feature{}),
168	};	221	};
169	result[@intFromEnum(Feature.experimental_zcd)] = .{	222	result[@intFromEnum(Feature.experimental_zacas)] = .{
170	.llvm_name = "experimental-zcd",	223	.llvm_name = "experimental-zacas",
171	.description = "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",	224	.description = "'Zacas' (Atomic Compare-And-Swap Instructions)",
172	.dependencies = featureSet(&[_]Feature{}),	225	.dependencies = featureSet(&[_]Feature{}),
173	};	226	};
174	result[@intFromEnum(Feature.experimental_zcf)] = .{	227	result[@intFromEnum(Feature.experimental_zfa)] = .{
175	.llvm_name = "experimental-zcf",	228	.llvm_name = "experimental-zfa",
176	.description = "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",	229	.description = "'Zfa' (Additional Floating-Point)",
		230	.dependencies = featureSet(&[_]Feature{
		231	.f,
		232	}),
		233	};
		234	result[@intFromEnum(Feature.experimental_zfbfmin)] = .{
		235	.llvm_name = "experimental-zfbfmin",
		236	.description = "'Zfbfmin' (Scalar BF16 Converts)",
		237	.dependencies = featureSet(&[_]Feature{
		238	.f,
		239	}),
		240	};
		241	result[@intFromEnum(Feature.experimental_zicond)] = .{
		242	.llvm_name = "experimental-zicond",
		243	.description = "'Zicond' (Integer Conditional Operations)",
177	.dependencies = featureSet(&[_]Feature{}),	244	.dependencies = featureSet(&[_]Feature{}),
178	};	245	};
179	result[@intFromEnum(Feature.experimental_zihintntl)] = .{	246	result[@intFromEnum(Feature.experimental_zihintntl)] = .{
180	.llvm_name = "experimental-zihintntl",	247	.llvm_name = "experimental-zihintntl",
181	.description = "'zihintntl' (Non-Temporal Locality Hints)",	248	.description = "'Zihintntl' (Non-Temporal Locality Hints)",
182	.dependencies = featureSet(&[_]Feature{}),	249	.dependencies = featureSet(&[_]Feature{}),
183	};	250	};
184	result[@intFromEnum(Feature.experimental_ztso)] = .{	251	result[@intFromEnum(Feature.experimental_ztso)] = .{
...	@@ -186,17 +253,103 @@ pub const all_features = blk: {	...	@@ -186,17 +253,103 @@ pub const all_features = blk: {
186	.description = "'Ztso' (Memory Model - Total Store Order)",	253	.description = "'Ztso' (Memory Model - Total Store Order)",
187	.dependencies = featureSet(&[_]Feature{}),	254	.dependencies = featureSet(&[_]Feature{}),
188	};	255	};
189	result[@intFromEnum(Feature.experimental_zvfh)] = .{	256	result[@intFromEnum(Feature.experimental_zvbb)] = .{
190	.llvm_name = "experimental-zvfh",	257	.llvm_name = "experimental-zvbb",
191	.description = "'Zvfh' (Vector Half-Precision Floating-Point)",	258	.description = "'Zvbb' (Vector Bit-manipulation used in Cryptography)",
		259	.dependencies = featureSet(&[_]Feature{}),
		260	};
		261	result[@intFromEnum(Feature.experimental_zvbc)] = .{
		262	.llvm_name = "experimental-zvbc",
		263	.description = "'Zvbc' (Vector Carryless Multiplication)",
		264	.dependencies = featureSet(&[_]Feature{}),
		265	};
		266	result[@intFromEnum(Feature.experimental_zvfbfmin)] = .{
		267	.llvm_name = "experimental-zvfbfmin",
		268	.description = "'Zvbfmin' (Vector BF16 Converts)",
192	.dependencies = featureSet(&[_]Feature{	269	.dependencies = featureSet(&[_]Feature{
193	.zve32f,	270	.zve32f,
194	}),	271	}),
195	};	272	};
		273	result[@intFromEnum(Feature.experimental_zvfbfwma)] = .{
		274	.llvm_name = "experimental-zvfbfwma",
		275	.description = "'Zvfbfwma' (Vector BF16 widening mul-add)",
		276	.dependencies = featureSet(&[_]Feature{
		277	.zve32f,
		278	}),
		279	};
		280	result[@intFromEnum(Feature.experimental_zvkg)] = .{
		281	.llvm_name = "experimental-zvkg",
		282	.description = "'Zvkg' (Vector GCM instructions for Cryptography)",
		283	.dependencies = featureSet(&[_]Feature{}),
		284	};
		285	result[@intFromEnum(Feature.experimental_zvkn)] = .{
		286	.llvm_name = "experimental-zvkn",
		287	.description = "This extension is shorthand for the following set of other extensions: Zvkned, Zvknhb, Zvbb, Zvbc, and Zvkt.",
		288	.dependencies = featureSet(&[_]Feature{}),
		289	};
		290	result[@intFromEnum(Feature.experimental_zvknc)] = .{
		291	.llvm_name = "experimental-zvknc",
		292	.description = "This extension is shorthand for the following set of other extensions: Zvkn and Zvbc.",
		293	.dependencies = featureSet(&[_]Feature{}),
		294	};
		295	result[@intFromEnum(Feature.experimental_zvkned)] = .{
		296	.llvm_name = "experimental-zvkned",
		297	.description = "'Zvkned' (Vector AES Encryption & Decryption (Single Round))",
		298	.dependencies = featureSet(&[_]Feature{}),
		299	};
		300	result[@intFromEnum(Feature.experimental_zvkng)] = .{
		301	.llvm_name = "experimental-zvkng",
		302	.description = "This extension is shorthand for the following set of other extensions: Zvkn and Zvkg.",
		303	.dependencies = featureSet(&[_]Feature{}),
		304	};
		305	result[@intFromEnum(Feature.experimental_zvknha)] = .{
		306	.llvm_name = "experimental-zvknha",
		307	.description = "'Zvknha' (Vector SHA-2 (SHA-256 only))",
		308	.dependencies = featureSet(&[_]Feature{}),
		309	};
		310	result[@intFromEnum(Feature.experimental_zvknhb)] = .{
		311	.llvm_name = "experimental-zvknhb",
		312	.description = "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
		313	.dependencies = featureSet(&[_]Feature{
		314	.experimental_zvknha,
		315	}),
		316	};
		317	result[@intFromEnum(Feature.experimental_zvks)] = .{
		318	.llvm_name = "experimental-zvks",
		319	.description = "This extension is shorthand for the following set of other extensions: Zvksed, Zvksh, Zvbb, Zvbc, and Zvkt.",
		320	.dependencies = featureSet(&[_]Feature{}),
		321	};
		322	result[@intFromEnum(Feature.experimental_zvksc)] = .{
		323	.llvm_name = "experimental-zvksc",
		324	.description = "This extension is shorthand for the following set of other extensions: Zvks and Zvbc.",
		325	.dependencies = featureSet(&[_]Feature{}),
		326	};
		327	result[@intFromEnum(Feature.experimental_zvksed)] = .{
		328	.llvm_name = "experimental-zvksed",
		329	.description = "'Zvksed' (SM4 Block Cipher Instructions)",
		330	.dependencies = featureSet(&[_]Feature{}),
		331	};
		332	result[@intFromEnum(Feature.experimental_zvksg)] = .{
		333	.llvm_name = "experimental-zvksg",
		334	.description = "This extension is shorthand for the following set of other extensions: Zvks and Zvkg.",
		335	.dependencies = featureSet(&[_]Feature{}),
		336	};
		337	result[@intFromEnum(Feature.experimental_zvksh)] = .{
		338	.llvm_name = "experimental-zvksh",
		339	.description = "'Zvksh' (SM3 Hash Function Instructions)",
		340	.dependencies = featureSet(&[_]Feature{}),
		341	};
		342	result[@intFromEnum(Feature.experimental_zvkt)] = .{
		343	.llvm_name = "experimental-zvkt",
		344	.description = "'Zvkt' (Vector Data-Independent Execution Latency)",
		345	.dependencies = featureSet(&[_]Feature{}),
		346	};
196	result[@intFromEnum(Feature.f)] = .{	347	result[@intFromEnum(Feature.f)] = .{
197	.llvm_name = "f",	348	.llvm_name = "f",
198	.description = "'F' (Single-Precision Floating-Point)",	349	.description = "'F' (Single-Precision Floating-Point)",
199	.dependencies = featureSet(&[_]Feature{}),	350	.dependencies = featureSet(&[_]Feature{
		351	.zicsr,
		352	}),
200	};	353	};
201	result[@intFromEnum(Feature.forced_atomics)] = .{	354	result[@intFromEnum(Feature.forced_atomics)] = .{
202	.llvm_name = "forced-atomics",	355	.llvm_name = "forced-atomics",
...	@@ -398,6 +551,11 @@ pub const all_features = blk: {	...	@@ -398,6 +551,11 @@ pub const all_features = blk: {
398	.description = "Enable save/restore.",	551	.description = "Enable save/restore.",
399	.dependencies = featureSet(&[_]Feature{}),	552	.dependencies = featureSet(&[_]Feature{}),
400	};	553	};
		554	result[@intFromEnum(Feature.seq_cst_trailing_fence)] = .{
		555	.llvm_name = "seq-cst-trailing-fence",
		556	.description = "Enable trailing fence for seq-cst store.",
		557	.dependencies = featureSet(&[_]Feature{}),
		558	};
401	result[@intFromEnum(Feature.short_forward_branch_opt)] = .{	559	result[@intFromEnum(Feature.short_forward_branch_opt)] = .{
402	.llvm_name = "short-forward-branch-opt",	560	.llvm_name = "short-forward-branch-opt",
403	.description = "Enable short forward branch optimization",	561	.description = "Enable short forward branch optimization",
...	@@ -428,15 +586,93 @@ pub const all_features = blk: {	...	@@ -428,15 +586,93 @@ pub const all_features = blk: {
428	.description = "Has reasonably performant unaligned scalar loads and stores",	586	.description = "Has reasonably performant unaligned scalar loads and stores",
429	.dependencies = featureSet(&[_]Feature{}),	587	.dependencies = featureSet(&[_]Feature{}),
430	};	588	};
		589	result[@intFromEnum(Feature.unaligned_vector_mem)] = .{
		590	.llvm_name = "unaligned-vector-mem",
		591	.description = "Has reasonably performant unaligned vector loads and stores",
		592	.dependencies = featureSet(&[_]Feature{}),
		593	};
431	result[@intFromEnum(Feature.v)] = .{	594	result[@intFromEnum(Feature.v)] = .{
432	.llvm_name = "v",	595	.llvm_name = "v",
433	.description = "'V' (Vector Extension for Application Processors)",	596	.description = "'V' (Vector Extension for Application Processors)",
434	.dependencies = featureSet(&[_]Feature{	597	.dependencies = featureSet(&[_]Feature{
435	.d,
436	.zve64d,	598	.zve64d,
437	.zvl128b,	599	.zvl128b,
438	}),	600	}),
439	};	601	};
		602	result[@intFromEnum(Feature.xcvbitmanip)] = .{
		603	.llvm_name = "xcvbitmanip",
		604	.description = "'XCVbitmanip' (CORE-V Bit Manipulation)",
		605	.dependencies = featureSet(&[_]Feature{}),
		606	};
		607	result[@intFromEnum(Feature.xcvmac)] = .{
		608	.llvm_name = "xcvmac",
		609	.description = "'XCVmac' (CORE-V Multiply-Accumulate)",
		610	.dependencies = featureSet(&[_]Feature{}),
		611	};
		612	result[@intFromEnum(Feature.xsfcie)] = .{
		613	.llvm_name = "xsfcie",
		614	.description = "'XSfcie' (SiFive Custom Instruction Extension SCIE.)",
		615	.dependencies = featureSet(&[_]Feature{}),
		616	};
		617	result[@intFromEnum(Feature.xsfvcp)] = .{
		618	.llvm_name = "xsfvcp",
		619	.description = "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
		620	.dependencies = featureSet(&[_]Feature{
		621	.zve32x,
		622	}),
		623	};
		624	result[@intFromEnum(Feature.xtheadba)] = .{
		625	.llvm_name = "xtheadba",
		626	.description = "'xtheadba' (T-Head address calculation instructions)",
		627	.dependencies = featureSet(&[_]Feature{}),
		628	};
		629	result[@intFromEnum(Feature.xtheadbb)] = .{
		630	.llvm_name = "xtheadbb",
		631	.description = "'xtheadbb' (T-Head basic bit-manipulation instructions)",
		632	.dependencies = featureSet(&[_]Feature{}),
		633	};
		634	result[@intFromEnum(Feature.xtheadbs)] = .{
		635	.llvm_name = "xtheadbs",
		636	.description = "'xtheadbs' (T-Head single-bit instructions)",
		637	.dependencies = featureSet(&[_]Feature{}),
		638	};
		639	result[@intFromEnum(Feature.xtheadcmo)] = .{
		640	.llvm_name = "xtheadcmo",
		641	.description = "'xtheadcmo' (T-Head cache management instructions)",
		642	.dependencies = featureSet(&[_]Feature{}),
		643	};
		644	result[@intFromEnum(Feature.xtheadcondmov)] = .{
		645	.llvm_name = "xtheadcondmov",
		646	.description = "'xtheadcondmov' (T-Head conditional move instructions)",
		647	.dependencies = featureSet(&[_]Feature{}),
		648	};
		649	result[@intFromEnum(Feature.xtheadfmemidx)] = .{
		650	.llvm_name = "xtheadfmemidx",
		651	.description = "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)",
		652	.dependencies = featureSet(&[_]Feature{
		653	.f,
		654	}),
		655	};
		656	result[@intFromEnum(Feature.xtheadmac)] = .{
		657	.llvm_name = "xtheadmac",
		658	.description = "'xtheadmac' (T-Head Multiply-Accumulate Instructions)",
		659	.dependencies = featureSet(&[_]Feature{}),
		660	};
		661	result[@intFromEnum(Feature.xtheadmemidx)] = .{
		662	.llvm_name = "xtheadmemidx",
		663	.description = "'xtheadmemidx' (T-Head Indexed Memory Operations)",
		664	.dependencies = featureSet(&[_]Feature{}),
		665	};
		666	result[@intFromEnum(Feature.xtheadmempair)] = .{
		667	.llvm_name = "xtheadmempair",
		668	.description = "'xtheadmempair' (T-Head two-GPR Memory Operations)",
		669	.dependencies = featureSet(&[_]Feature{}),
		670	};
		671	result[@intFromEnum(Feature.xtheadsync)] = .{
		672	.llvm_name = "xtheadsync",
		673	.description = "'xtheadsync' (T-Head multicore synchronization instructions)",
		674	.dependencies = featureSet(&[_]Feature{}),
		675	};
440	result[@intFromEnum(Feature.xtheadvdot)] = .{	676	result[@intFromEnum(Feature.xtheadvdot)] = .{
441	.llvm_name = "xtheadvdot",	677	.llvm_name = "xtheadvdot",
442	.description = "'xtheadvdot' (T-Head Vector Extensions for Dot)",	678	.description = "'xtheadvdot' (T-Head Vector Extensions for Dot)",
...	@@ -449,6 +685,11 @@ pub const all_features = blk: {	...	@@ -449,6 +685,11 @@ pub const all_features = blk: {
449	.description = "'XVentanaCondOps' (Ventana Conditional Ops)",	685	.description = "'XVentanaCondOps' (Ventana Conditional Ops)",
450	.dependencies = featureSet(&[_]Feature{}),	686	.dependencies = featureSet(&[_]Feature{}),
451	};	687	};
		688	result[@intFromEnum(Feature.zawrs)] = .{
		689	.llvm_name = "zawrs",
		690	.description = "'Zawrs' (Wait on Reservation Set)",
		691	.dependencies = featureSet(&[_]Feature{}),
		692	};
452	result[@intFromEnum(Feature.zba)] = .{	693	result[@intFromEnum(Feature.zba)] = .{
453	.llvm_name = "zba",	694	.llvm_name = "zba",
454	.description = "'Zba' (Address Generation Instructions)",	695	.description = "'Zba' (Address Generation Instructions)",
...	@@ -484,6 +725,56 @@ pub const all_features = blk: {	...	@@ -484,6 +725,56 @@ pub const all_features = blk: {
484	.description = "'Zbs' (Single-Bit Instructions)",	725	.description = "'Zbs' (Single-Bit Instructions)",
485	.dependencies = featureSet(&[_]Feature{}),	726	.dependencies = featureSet(&[_]Feature{}),
486	};	727	};
		728	result[@intFromEnum(Feature.zca)] = .{
		729	.llvm_name = "zca",
		730	.description = "'Zca' (part of the C extension, excluding compressed floating point loads/stores)",
		731	.dependencies = featureSet(&[_]Feature{}),
		732	};
		733	result[@intFromEnum(Feature.zcb)] = .{
		734	.llvm_name = "zcb",
		735	.description = "'Zcb' (Compressed basic bit manipulation instructions)",
		736	.dependencies = featureSet(&[_]Feature{
		737	.zca,
		738	}),
		739	};
		740	result[@intFromEnum(Feature.zcd)] = .{
		741	.llvm_name = "zcd",
		742	.description = "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
		743	.dependencies = featureSet(&[_]Feature{
		744	.zca,
		745	}),
		746	};
		747	result[@intFromEnum(Feature.zce)] = .{
		748	.llvm_name = "zce",
		749	.description = "'Zce' (Compressed extensions for microcontrollers)",
		750	.dependencies = featureSet(&[_]Feature{
		751	.zcb,
		752	.zcmp,
		753	.zcmt,
		754	}),
		755	};
		756	result[@intFromEnum(Feature.zcf)] = .{
		757	.llvm_name = "zcf",
		758	.description = "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
		759	.dependencies = featureSet(&[_]Feature{
		760	.zca,
		761	}),
		762	};
		763	result[@intFromEnum(Feature.zcmp)] = .{
		764	.llvm_name = "zcmp",
		765	.description = "'Zcmp' (sequenced instuctions for code-size reduction)",
		766	.dependencies = featureSet(&[_]Feature{
		767	.zca,
		768	}),
		769	};
		770	result[@intFromEnum(Feature.zcmt)] = .{
		771	.llvm_name = "zcmt",
		772	.description = "'Zcmt' (table jump instuctions for code-size reduction)",
		773	.dependencies = featureSet(&[_]Feature{
		774	.zca,
		775	.zicsr,
		776	}),
		777	};
487	result[@intFromEnum(Feature.zdinx)] = .{	778	result[@intFromEnum(Feature.zdinx)] = .{
488	.llvm_name = "zdinx",	779	.llvm_name = "zdinx",
489	.description = "'Zdinx' (Double in Integer)",	780	.description = "'Zdinx' (Double in Integer)",
...	@@ -508,7 +799,9 @@ pub const all_features = blk: {	...	@@ -508,7 +799,9 @@ pub const all_features = blk: {
508	result[@intFromEnum(Feature.zfinx)] = .{	799	result[@intFromEnum(Feature.zfinx)] = .{
509	.llvm_name = "zfinx",	800	.llvm_name = "zfinx",
510	.description = "'Zfinx' (Float in Integer)",	801	.description = "'Zfinx' (Float in Integer)",
511	.dependencies = featureSet(&[_]Feature{}),	802	.dependencies = featureSet(&[_]Feature{
		803	.zicsr,
		804	}),
512	};	805	};
513	result[@intFromEnum(Feature.zhinx)] = .{	806	result[@intFromEnum(Feature.zhinx)] = .{
514	.llvm_name = "zhinx",	807	.llvm_name = "zhinx",
...	@@ -539,11 +832,35 @@ pub const all_features = blk: {	...	@@ -539,11 +832,35 @@ pub const all_features = blk: {
539	.description = "'Zicboz' (Cache-Block Zero Instructions)",	832	.description = "'Zicboz' (Cache-Block Zero Instructions)",
540	.dependencies = featureSet(&[_]Feature{}),	833	.dependencies = featureSet(&[_]Feature{}),
541	};	834	};
		835	result[@intFromEnum(Feature.zicntr)] = .{
		836	.llvm_name = "zicntr",
		837	.description = "'Zicntr' (Base Counters and Timers)",
		838	.dependencies = featureSet(&[_]Feature{
		839	.zicsr,
		840	}),
		841	};
		842	result[@intFromEnum(Feature.zicsr)] = .{
		843	.llvm_name = "zicsr",
		844	.description = "'zicsr' (CSRs)",
		845	.dependencies = featureSet(&[_]Feature{}),
		846	};
		847	result[@intFromEnum(Feature.zifencei)] = .{
		848	.llvm_name = "zifencei",
		849	.description = "'Zifencei' (fence.i)",
		850	.dependencies = featureSet(&[_]Feature{}),
		851	};
542	result[@intFromEnum(Feature.zihintpause)] = .{	852	result[@intFromEnum(Feature.zihintpause)] = .{
543	.llvm_name = "zihintpause",	853	.llvm_name = "zihintpause",
544	.description = "'zihintpause' (Pause Hint)",	854	.description = "'Zihintpause' (Pause Hint)",
545	.dependencies = featureSet(&[_]Feature{}),	855	.dependencies = featureSet(&[_]Feature{}),
546	};	856	};
		857	result[@intFromEnum(Feature.zihpm)] = .{
		858	.llvm_name = "zihpm",
		859	.description = "'Zihpm' (Hardware Performance Counters)",
		860	.dependencies = featureSet(&[_]Feature{
		861	.zicsr,
		862	}),
		863	};
547	result[@intFromEnum(Feature.zk)] = .{	864	result[@intFromEnum(Feature.zk)] = .{
548	.llvm_name = "zk",	865	.llvm_name = "zk",
549	.description = "'Zk' (Standard scalar cryptography extension)",	866	.description = "'Zk' (Standard scalar cryptography extension)",
...	@@ -620,6 +937,7 @@ pub const all_features = blk: {	...	@@ -620,6 +937,7 @@ pub const all_features = blk: {
620	.llvm_name = "zve32f",	937	.llvm_name = "zve32f",
621	.description = "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)",	938	.description = "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)",
622	.dependencies = featureSet(&[_]Feature{	939	.dependencies = featureSet(&[_]Feature{
		940	.f,
623	.zve32x,	941	.zve32x,
624	}),	942	}),
625	};	943	};
...	@@ -627,6 +945,7 @@ pub const all_features = blk: {	...	@@ -627,6 +945,7 @@ pub const all_features = blk: {
627	.llvm_name = "zve32x",	945	.llvm_name = "zve32x",
628	.description = "'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)",	946	.description = "'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)",
629	.dependencies = featureSet(&[_]Feature{	947	.dependencies = featureSet(&[_]Feature{
		948	.zicsr,
630	.zvl32b,	949	.zvl32b,
631	}),	950	}),
632	};	951	};
...	@@ -634,6 +953,7 @@ pub const all_features = blk: {	...	@@ -634,6 +953,7 @@ pub const all_features = blk: {
634	.llvm_name = "zve64d",	953	.llvm_name = "zve64d",
635	.description = "'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)",	954	.description = "'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)",
636	.dependencies = featureSet(&[_]Feature{	955	.dependencies = featureSet(&[_]Feature{
		956	.d,
637	.zve64f,	957	.zve64f,
638	}),	958	}),
639	};	959	};
...	@@ -653,6 +973,14 @@ pub const all_features = blk: {	...	@@ -653,6 +973,14 @@ pub const all_features = blk: {
653	.zvl64b,	973	.zvl64b,
654	}),	974	}),
655	};	975	};
		976	result[@intFromEnum(Feature.zvfh)] = .{
		977	.llvm_name = "zvfh",
		978	.description = "'Zvfh' (Vector Half-Precision Floating-Point)",
		979	.dependencies = featureSet(&[_]Feature{
		980	.zfhmin,
		981	.zve32f,
		982	}),
		983	};
656	result[@intFromEnum(Feature.zvl1024b)] = .{	984	result[@intFromEnum(Feature.zvl1024b)] = .{
657	.llvm_name = "zvl1024b",	985	.llvm_name = "zvl1024b",
658	.description = "'Zvl' (Minimum Vector Length) 1024",	986	.description = "'Zvl' (Minimum Vector Length) 1024",
...	@@ -795,6 +1123,8 @@ pub const cpu = struct {	...	@@ -795,6 +1123,8 @@ pub const cpu = struct {
795	.llvm_name = "rocket-rv32",	1123	.llvm_name = "rocket-rv32",
796	.features = featureSet(&[_]Feature{	1124	.features = featureSet(&[_]Feature{
797	.@"32bit",	1125	.@"32bit",
		1126	.zicsr,
		1127	.zifencei,
798	}),	1128	}),
799	};	1129	};
800	pub const rocket_rv64 = CpuModel{	1130	pub const rocket_rv64 = CpuModel{
...	@@ -802,6 +1132,8 @@ pub const cpu = struct {	...	@@ -802,6 +1132,8 @@ pub const cpu = struct {
802	.llvm_name = "rocket-rv64",	1132	.llvm_name = "rocket-rv64",
803	.features = featureSet(&[_]Feature{	1133	.features = featureSet(&[_]Feature{
804	.@"64bit",	1134	.@"64bit",
		1135	.zicsr,
		1136	.zifencei,
805	}),	1137	}),
806	};	1138	};
807	pub const sifive_7_series = CpuModel{	1139	pub const sifive_7_series = CpuModel{
...	@@ -819,6 +1151,8 @@ pub const cpu = struct {	...	@@ -819,6 +1151,8 @@ pub const cpu = struct {
819	.@"32bit",	1151	.@"32bit",
820	.c,	1152	.c,
821	.m,	1153	.m,
		1154	.zicsr,
		1155	.zifencei,
822	}),	1156	}),
823	};	1157	};
824	pub const sifive_e21 = CpuModel{	1158	pub const sifive_e21 = CpuModel{
...	@@ -829,6 +1163,8 @@ pub const cpu = struct {	...	@@ -829,6 +1163,8 @@ pub const cpu = struct {
829	.a,	1163	.a,
830	.c,	1164	.c,
831	.m,	1165	.m,
		1166	.zicsr,
		1167	.zifencei,
832	}),	1168	}),
833	};	1169	};
834	pub const sifive_e24 = CpuModel{	1170	pub const sifive_e24 = CpuModel{
...	@@ -840,6 +1176,7 @@ pub const cpu = struct {	...	@@ -840,6 +1176,7 @@ pub const cpu = struct {
840	.c,	1176	.c,
841	.f,	1177	.f,
842	.m,	1178	.m,
		1179	.zifencei,
843	}),	1180	}),
844	};	1181	};
845	pub const sifive_e31 = CpuModel{	1182	pub const sifive_e31 = CpuModel{
...	@@ -850,6 +1187,8 @@ pub const cpu = struct {	...	@@ -850,6 +1187,8 @@ pub const cpu = struct {
850	.a,	1187	.a,
851	.c,	1188	.c,
852	.m,	1189	.m,
		1190	.zicsr,
		1191	.zifencei,
853	}),	1192	}),
854	};	1193	};
855	pub const sifive_e34 = CpuModel{	1194	pub const sifive_e34 = CpuModel{
...	@@ -861,6 +1200,7 @@ pub const cpu = struct {	...	@@ -861,6 +1200,7 @@ pub const cpu = struct {
861	.c,	1200	.c,
862	.f,	1201	.f,
863	.m,	1202	.m,
		1203	.zifencei,
864	}),	1204	}),
865	};	1205	};
866	pub const sifive_e76 = CpuModel{	1206	pub const sifive_e76 = CpuModel{
...	@@ -874,6 +1214,7 @@ pub const cpu = struct {	...	@@ -874,6 +1214,7 @@ pub const cpu = struct {
874	.m,	1214	.m,
875	.no_default_unroll,	1215	.no_default_unroll,
876	.short_forward_branch_opt,	1216	.short_forward_branch_opt,
		1217	.zifencei,
877	}),	1218	}),
878	};	1219	};
879	pub const sifive_s21 = CpuModel{	1220	pub const sifive_s21 = CpuModel{
...	@@ -884,6 +1225,8 @@ pub const cpu = struct {	...	@@ -884,6 +1225,8 @@ pub const cpu = struct {
884	.a,	1225	.a,
885	.c,	1226	.c,
886	.m,	1227	.m,
		1228	.zicsr,
		1229	.zifencei,
887	}),	1230	}),
888	};	1231	};
889	pub const sifive_s51 = CpuModel{	1232	pub const sifive_s51 = CpuModel{
...	@@ -894,6 +1237,8 @@ pub const cpu = struct {	...	@@ -894,6 +1237,8 @@ pub const cpu = struct {
894	.a,	1237	.a,
895	.c,	1238	.c,
896	.m,	1239	.m,
		1240	.zicsr,
		1241	.zifencei,
897	}),	1242	}),
898	};	1243	};
899	pub const sifive_s54 = CpuModel{	1244	pub const sifive_s54 = CpuModel{
...	@@ -905,6 +1250,7 @@ pub const cpu = struct {	...	@@ -905,6 +1250,7 @@ pub const cpu = struct {
905	.c,	1250	.c,
906	.d,	1251	.d,
907	.m,	1252	.m,
		1253	.zifencei,
908	}),	1254	}),
909	};	1255	};
910	pub const sifive_s76 = CpuModel{	1256	pub const sifive_s76 = CpuModel{
...	@@ -918,6 +1264,9 @@ pub const cpu = struct {	...	@@ -918,6 +1264,9 @@ pub const cpu = struct {
918	.m,	1264	.m,
919	.no_default_unroll,	1265	.no_default_unroll,
920	.short_forward_branch_opt,	1266	.short_forward_branch_opt,
		1267	.xsfcie,
		1268	.zifencei,
		1269	.zihintpause,
921	}),	1270	}),
922	};	1271	};
923	pub const sifive_u54 = CpuModel{	1272	pub const sifive_u54 = CpuModel{
...	@@ -929,6 +1278,7 @@ pub const cpu = struct {	...	@@ -929,6 +1278,7 @@ pub const cpu = struct {
929	.c,	1278	.c,
930	.d,	1279	.d,
931	.m,	1280	.m,
		1281	.zifencei,
932	}),	1282	}),
933	};	1283	};
934	pub const sifive_u74 = CpuModel{	1284	pub const sifive_u74 = CpuModel{
...	@@ -942,6 +1292,27 @@ pub const cpu = struct {	...	@@ -942,6 +1292,27 @@ pub const cpu = struct {
942	.m,	1292	.m,
943	.no_default_unroll,	1293	.no_default_unroll,
944	.short_forward_branch_opt,	1294	.short_forward_branch_opt,
		1295	.zifencei,
		1296	}),
		1297	};
		1298	pub const sifive_x280 = CpuModel{
		1299	.name = "sifive_x280",
		1300	.llvm_name = "sifive-x280",
		1301	.features = featureSet(&[_]Feature{
		1302	.@"64bit",
		1303	.a,
		1304	.c,
		1305	.dlen_factor_2,
		1306	.m,
		1307	.no_default_unroll,
		1308	.short_forward_branch_opt,
		1309	.v,
		1310	.zba,
		1311	.zbb,
		1312	.zfh,
		1313	.zifencei,
		1314	.zvfh,
		1315	.zvl512b,
945	}),	1316	}),
946	};	1317	};
947	pub const syntacore_scr1_base = CpuModel{	1318	pub const syntacore_scr1_base = CpuModel{
...	@@ -951,6 +1322,8 @@ pub const cpu = struct {	...	@@ -951,6 +1322,8 @@ pub const cpu = struct {
951	.@"32bit",	1322	.@"32bit",
952	.c,	1323	.c,
953	.no_default_unroll,	1324	.no_default_unroll,
		1325	.zicsr,
		1326	.zifencei,
954	}),	1327	}),
955	};	1328	};
956	pub const syntacore_scr1_max = CpuModel{	1329	pub const syntacore_scr1_max = CpuModel{
...	@@ -961,6 +1334,8 @@ pub const cpu = struct {	...	@@ -961,6 +1334,8 @@ pub const cpu = struct {
961	.c,	1334	.c,
962	.m,	1335	.m,
963	.no_default_unroll,	1336	.no_default_unroll,
		1337	.zicsr,
		1338	.zifencei,
964	}),	1339	}),
965	};	1340	};
966	};	1341	};

lib/std/target/x86.zig+299-170

 @@ -14,6 +14,7 @@ pub const Feature = enum {
     aes,
     allow_light_256_bit,
     amx_bf16,
+    amx_complex,
     amx_fp16,
     amx_int8,
     amx_tile,
 @@ -38,6 +39,7 @@ pub const Feature = enum {
     avxifma,
     avxneconvert,
     avxvnni,
+    avxvnniint16,
     avxvnniint8,
     bmi,
     bmi2,
 @@ -76,6 +78,7 @@ pub const Feature = enum {
     fast_variable_perlane_shuffle,
     fast_vector_fsqrt,
     fast_vector_shift_masks,
+    faster_shift_than_shuffle,
     fma,
     fma4,
     fsgsbase,
 @@ -101,6 +104,10 @@ pub const Feature = enum {
     movdir64b,
     movdiri,
     mwaitx,
+    no_bypass_delay,
+    no_bypass_delay_blend,
+    no_bypass_delay_mov,
+    no_bypass_delay_shuffle,
     nopl,
     pad_short_functions,
     pclmul,
 @@ -110,6 +117,7 @@ pub const Feature = enum {
     prefer_128_bit,
     prefer_256_bit,
     prefer_mask_registers,
+    prefer_movmsk_over_vtest,
     prefetchi,
     prefetchwt1,
     prfchw,
 @@ -130,6 +138,7 @@ pub const Feature = enum {
     seses,
     sgx,
     sha,
+    sha512,
     shstk,
     slow_3ops_lea,
     slow_incdec,
 @@ -140,6 +149,8 @@ pub const Feature = enum {
     slow_two_mem_ops,
     slow_unaligned_mem_16,
     slow_unaligned_mem_32,
+    sm3,
+    sm4,
     soft_float,
     sse,
     sse2,
 @@ -152,6 +163,7 @@ pub const Feature = enum {
     tagged_globals,
     tbm,
     tsxldtrk,
+    tuning_fast_imm_vector_shift,
     uintr,
     use_glm_div_sqrt_costs,
     use_slm_arith_costs,
 @@ -231,6 +243,13 @@ pub const all_features = blk: {
             .amx_tile,
         }),
     };
+    result[@intFromEnum(Feature.amx_complex)] = .{
+        .llvm_name = "amx-complex",
+        .description = "Support AMX-COMPLEX instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .amx_tile,
+        }),
+    };
     result[@intFromEnum(Feature.amx_fp16)] = .{
         .llvm_name = "amx-fp16",
         .description = "Support AMX amx-fp16 instructions",
 @@ -326,7 +345,7 @@ pub const all_features = blk: {
     };
     result[@intFromEnum(Feature.avx512ifma)] = .{
         .llvm_name = "avx512ifma",
-        .description = "Enable AVX-512 Integer Fused Multiply-Add",
+        .description = "Enable AVX-512 Integer Fused Multiple-Add",
         .dependencies = featureSet(&[_]Feature{
             .avx512f,
         }),
 @@ -401,6 +420,13 @@ pub const all_features = blk: {
             .avx2,
         }),
     };
+    result[@intFromEnum(Feature.avxvnniint16)] = .{
+        .llvm_name = "avxvnniint16",
+        .description = "Enable AVX-VNNI-INT16",
+        .dependencies = featureSet(&[_]Feature{
+            .avx2,
+        }),
+    };
     result[@intFromEnum(Feature.avxvnniint8)] = .{
         .llvm_name = "avxvnniint8",
         .description = "Enable AVX-VNNI-INT8",
 @@ -597,16 +623,21 @@ pub const all_features = blk: {
         .description = "Prefer a left/right vector logical shift pair over a shift+and pair",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.faster_shift_than_shuffle)] = .{
+        .llvm_name = "faster-shift-than-shuffle",
+        .description = "Shifts are faster (or as fast) as shuffle",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@intFromEnum(Feature.fma)] = .{
         .llvm_name = "fma",
-        .description = "Enable three-operand fused multiply-add",
+        .description = "Enable three-operand fused multiple-add",
         .dependencies = featureSet(&[_]Feature{
             .avx,
         }),
     };
     result[@intFromEnum(Feature.fma4)] = .{
         .llvm_name = "fma4",
-        .description = "Enable four-operand fused multiply-add",
+        .description = "Enable four-operand fused multiple-add",
         .dependencies = featureSet(&[_]Feature{
             .avx,
             .sse4a,
 @@ -731,6 +762,26 @@ pub const all_features = blk: {
         .description = "Enable MONITORX/MWAITX timer functionality",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.no_bypass_delay)] = .{
+        .llvm_name = "no-bypass-delay",
+        .description = "Has no bypass delay when using the 'wrong' domain",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@intFromEnum(Feature.no_bypass_delay_blend)] = .{
+        .llvm_name = "no-bypass-delay-blend",
+        .description = "Has no bypass delay when using the 'wrong' blend type",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@intFromEnum(Feature.no_bypass_delay_mov)] = .{
+        .llvm_name = "no-bypass-delay-mov",
+        .description = "Has no bypass delay when using the 'wrong' mov type",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@intFromEnum(Feature.no_bypass_delay_shuffle)] = .{
+        .llvm_name = "no-bypass-delay-shuffle",
+        .description = "Has no bypass delay when using the 'wrong' shuffle type",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@intFromEnum(Feature.nopl)] = .{
         .llvm_name = "nopl",
         .description = "Enable NOPL instruction (generally pentium pro+)",
 @@ -778,6 +829,11 @@ pub const all_features = blk: {
         .description = "Prefer AVX512 mask registers over PTEST/MOVMSK",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.prefer_movmsk_over_vtest)] = .{
+        .llvm_name = "prefer-movmsk-over-vtest",
+        .description = "Prefer movmsk over vtest instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@intFromEnum(Feature.prefetchi)] = .{
         .llvm_name = "prefetchi",
         .description = "Prefetch instruction with T0 or T1 Hint",
 @@ -887,6 +943,13 @@ pub const all_features = blk: {
             .sse2,
         }),
     };
+    result[@intFromEnum(Feature.sha512)] = .{
+        .llvm_name = "sha512",
+        .description = "Support SHA512 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .avx,
+        }),
+    };
     result[@intFromEnum(Feature.shstk)] = .{
         .llvm_name = "shstk",
         .description = "Support CET Shadow-Stack instructions",
 @@ -937,6 +1000,20 @@ pub const all_features = blk: {
         .description = "Slow unaligned 32-byte memory access",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.sm3)] = .{
+        .llvm_name = "sm3",
+        .description = "Support SM3 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .avx,
+        }),
+    };
+    result[@intFromEnum(Feature.sm4)] = .{
+        .llvm_name = "sm4",
+        .description = "Support SM4 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .avx,
+        }),
+    };
     result[@intFromEnum(Feature.soft_float)] = .{
         .llvm_name = "soft-float",
         .description = "Use software floating point features",
 @@ -1009,6 +1086,11 @@ pub const all_features = blk: {
         .description = "Support TSXLDTRK instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.tuning_fast_imm_vector_shift)] = .{
+        .llvm_name = "tuning-fast-imm-vector-shift",
+        .description = "Vector shifts are fast (2/cycle) as opposed to slow (1/cycle)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@intFromEnum(Feature.uintr)] = .{
         .llvm_name = "uintr",
         .description = "Has UINTR Instructions",
 @@ -1148,10 +1230,14 @@ pub const cpu = struct {
             .movbe,
             .movdir64b,
             .movdiri,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pconfig,
             .pku,
             .popcnt,
+            .prefer_movmsk_over_vtest,
             .prfchw,
             .ptwrite,
             .rdpid,
 @@ -1162,6 +1248,7 @@ pub const cpu = struct {
             .sha,
             .shstk,
             .slow_3ops_lea,
+            .tuning_fast_imm_vector_shift,
             .vaes,
             .vpclmulqdq,
             .vzeroupper,
 @@ -1342,6 +1429,7 @@ pub const cpu = struct {
             .lea_uses_ag,
             .mmx,
             .movbe,
+            .no_bypass_delay,
             .nopl,
             .pad_short_functions,
             .sahf,
 @@ -1352,6 +1440,46 @@ pub const cpu = struct {
             .x87,
         }),
     };
+    pub const atom_sse4_2_movbe = CpuModel{
+        .name = "atom_sse4_2_movbe",
+        .llvm_name = "atom_sse4_2_movbe",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .aes,
+            .clflushopt,
+            .cmov,
+            .crc32,
+            .cx16,
+            .false_deps_popcnt,
+            .fast_7bytenop,
+            .fast_movbe,
+            .fsgsbase,
+            .fxsr,
+            .idivq_to_divl,
+            .mmx,
+            .movbe,
+            .no_bypass_delay,
+            .nopl,
+            .pclmul,
+            .popcnt,
+            .prfchw,
+            .rdrnd,
+            .rdseed,
+            .sahf,
+            .sha,
+            .slow_incdec,
+            .slow_lea,
+            .slow_pmulld,
+            .slow_two_mem_ops,
+            .sse4_2,
+            .use_slm_arith_costs,
+            .vzeroupper,
+            .x87,
+            .xsavec,
+            .xsaveopt,
+            .xsaves,
+        }),
+    };
     pub const barcelona = CpuModel{
         .name = "barcelona",
         .llvm_name = "barcelona",
 @@ -1529,6 +1657,7 @@ pub const cpu = struct {
             .lea_uses_ag,
             .mmx,
             .movbe,
+            .no_bypass_delay,
             .nopl,
             .pad_short_functions,
             .sahf,
 @@ -1570,6 +1699,8 @@ pub const cpu = struct {
             .macrofusion,
             .mmx,
             .movbe,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pclmul,
             .popcnt,
 @@ -1701,6 +1832,9 @@ pub const cpu = struct {
             .macrofusion,
             .mmx,
             .movbe,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pclmul,
             .pku,
 @@ -1712,6 +1846,7 @@ pub const cpu = struct {
             .sahf,
             .sha,
             .slow_3ops_lea,
+            .tuning_fast_imm_vector_shift,
             .vzeroupper,
             .x87,
             .xsavec,
 @@ -1748,6 +1883,7 @@ pub const cpu = struct {
             .fast_variable_crosslane_shuffle,
             .fast_variable_perlane_shuffle,
             .fast_vector_fsqrt,
+            .faster_shift_than_shuffle,
             .fsgsbase,
             .fxsr,
             .idivq_to_divl,
 @@ -1756,6 +1892,9 @@ pub const cpu = struct {
             .macrofusion,
             .mmx,
             .movbe,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pclmul,
             .pku,
 @@ -1766,6 +1905,7 @@ pub const cpu = struct {
             .rdseed,
             .sahf,
             .slow_3ops_lea,
+            .tuning_fast_imm_vector_shift,
             .vzeroupper,
             .x87,
             .xsavec,
 @@ -1802,6 +1942,7 @@ pub const cpu = struct {
             .fast_variable_crosslane_shuffle,
             .fast_variable_perlane_shuffle,
             .fast_vector_fsqrt,
+            .faster_shift_than_shuffle,
             .fsgsbase,
             .fxsr,
             .idivq_to_divl,
 @@ -1810,6 +1951,9 @@ pub const cpu = struct {
             .macrofusion,
             .mmx,
             .movbe,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pclmul,
             .pku,
 @@ -1820,6 +1964,7 @@ pub const cpu = struct {
             .rdseed,
             .sahf,
             .slow_3ops_lea,
+            .tuning_fast_imm_vector_shift,
             .vzeroupper,
             .x87,
             .xsavec,
 @@ -1845,77 +1990,6 @@ pub const cpu = struct {
             .x87,
         }),
     };
-    pub const core_avx2 = CpuModel{
-        .name = "core_avx2",
-        .llvm_name = "core-avx2",
-        .features = featureSet(&[_]Feature{
-            .@"64bit",
-            .allow_light_256_bit,
-            .avx2,
-            .bmi,
-            .bmi2,
-            .cmov,
-            .crc32,
-            .cx16,
-            .ermsb,
-            .f16c,
-            .false_deps_lzcnt_tzcnt,
-            .false_deps_popcnt,
-            .fast_15bytenop,
-            .fast_scalar_fsqrt,
-            .fast_shld_rotate,
-            .fast_variable_crosslane_shuffle,
-            .fast_variable_perlane_shuffle,
-            .fma,
-            .fsgsbase,
-            .fxsr,
-            .idivq_to_divl,
-            .invpcid,
-            .lzcnt,
-            .macrofusion,
-            .mmx,
-            .movbe,
-            .nopl,
-            .pclmul,
-            .popcnt,
-            .rdrnd,
-            .sahf,
-            .slow_3ops_lea,
-            .vzeroupper,
-            .x87,
-            .xsaveopt,
-        }),
-    };
-    pub const core_avx_i = CpuModel{
-        .name = "core_avx_i",
-        .llvm_name = "core-avx-i",
-        .features = featureSet(&[_]Feature{
-            .@"64bit",
-            .cmov,
-            .crc32,
-            .cx16,
-            .f16c,
-            .false_deps_popcnt,
-            .fast_15bytenop,
-            .fast_scalar_fsqrt,
-            .fast_shld_rotate,
-            .fsgsbase,
-            .fxsr,
-            .idivq_to_divl,
-            .macrofusion,
-            .mmx,
-            .nopl,
-            .pclmul,
-            .popcnt,
-            .rdrnd,
-            .sahf,
-            .slow_3ops_lea,
-            .slow_unaligned_mem_32,
-            .vzeroupper,
-            .x87,
-            .xsaveopt,
-        }),
-    };
     pub const corei7 = CpuModel{
         .name = "corei7",
         .llvm_name = "corei7",
 @@ -1927,6 +2001,7 @@ pub const cpu = struct {
             .fxsr,
             .macrofusion,
             .mmx,
+            .no_bypass_delay_mov,
             .nopl,
             .popcnt,
             .sahf,
 @@ -1935,34 +2010,6 @@ pub const cpu = struct {
             .x87,
         }),
     };
-    pub const corei7_avx = CpuModel{
-        .name = "corei7_avx",
-        .llvm_name = "corei7-avx",
-        .features = featureSet(&[_]Feature{
-            .@"64bit",
-            .avx,
-            .cmov,
-            .crc32,
-            .cx16,
-            .false_deps_popcnt,
-            .fast_15bytenop,
-            .fast_scalar_fsqrt,
-            .fast_shld_rotate,
-            .fxsr,
-            .idivq_to_divl,
-            .macrofusion,
-            .mmx,
-            .nopl,
-            .pclmul,
-            .popcnt,
-            .sahf,
-            .slow_3ops_lea,
-            .slow_unaligned_mem_32,
-            .vzeroupper,
-            .x87,
-            .xsaveopt,
-        }),
-    };
     pub const emeraldrapids = CpuModel{
         .name = "emeraldrapids",
         .llvm_name = "emeraldrapids",
 @@ -2016,6 +2063,9 @@ pub const cpu = struct {
             .movbe,
             .movdir64b,
             .movdiri,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pconfig,
             .pku,
 @@ -2031,6 +2081,7 @@ pub const cpu = struct {
             .sha,
             .shstk,
             .tsxldtrk,
+            .tuning_fast_imm_vector_shift,
             .uintr,
             .vaes,
             .vpclmulqdq,
 @@ -2085,6 +2136,7 @@ pub const cpu = struct {
             .fxsr,
             .mmx,
             .movbe,
+            .no_bypass_delay,
             .nopl,
             .pclmul,
             .popcnt,
 @@ -2120,6 +2172,7 @@ pub const cpu = struct {
             .fxsr,
             .mmx,
             .movbe,
+            .no_bypass_delay,
             .nopl,
             .pclmul,
             .popcnt,
 @@ -2161,6 +2214,7 @@ pub const cpu = struct {
             .cmpccxadd,
             .crc32,
             .cx16,
+            .enqcmd,
             .f16c,
             .fast_movbe,
             .fma,
 @@ -2174,6 +2228,7 @@ pub const cpu = struct {
             .movbe,
             .movdir64b,
             .movdiri,
+            .no_bypass_delay,
             .nopl,
             .pconfig,
             .pku,
 @@ -2191,6 +2246,7 @@ pub const cpu = struct {
             .slow_incdec,
             .slow_lea,
             .slow_two_mem_ops,
+            .uintr,
             .use_glm_div_sqrt_costs,
             .vaes,
             .vpclmulqdq,
 @@ -2257,6 +2313,96 @@ pub const cpu = struct {
             .movbe,
             .movdir64b,
             .movdiri,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
+            .nopl,
+            .pconfig,
+            .pku,
+            .popcnt,
+            .prefer_256_bit,
+            .prefetchi,
+            .prfchw,
+            .ptwrite,
+            .rdpid,
+            .rdrnd,
+            .rdseed,
+            .sahf,
+            .serialize,
+            .sha,
+            .shstk,
+            .tsxldtrk,
+            .tuning_fast_imm_vector_shift,
+            .uintr,
+            .vaes,
+            .vpclmulqdq,
+            .vzeroupper,
+            .waitpkg,
+            .wbnoinvd,
+            .x87,
+            .xsavec,
+            .xsaveopt,
+            .xsaves,
+        }),
+    };
+    pub const graniterapids_d = CpuModel{
+        .name = "graniterapids_d",
+        .llvm_name = "graniterapids-d",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .adx,
+            .allow_light_256_bit,
+            .amx_bf16,
+            .amx_complex,
+            .amx_fp16,
+            .amx_int8,
+            .avx512bf16,
+            .avx512bitalg,
+            .avx512cd,
+            .avx512fp16,
+            .avx512ifma,
+            .avx512vbmi,
+            .avx512vbmi2,
+            .avx512vnni,
+            .avx512vpopcntdq,
+            .avxvnni,
+            .bmi,
+            .bmi2,
+            .cldemote,
+            .clflushopt,
+            .clwb,
+            .cmov,
+            .crc32,
+            .cx16,
+            .enqcmd,
+            .ermsb,
+            .false_deps_getmant,
+            .false_deps_mulc,
+            .false_deps_mullq,
+            .false_deps_perm,
+            .false_deps_range,
+            .fast_15bytenop,
+            .fast_gather,
+            .fast_scalar_fsqrt,
+            .fast_shld_rotate,
+            .fast_variable_crosslane_shuffle,
+            .fast_variable_perlane_shuffle,
+            .fast_vector_fsqrt,
+            .fsgsbase,
+            .fsrm,
+            .fxsr,
+            .gfni,
+            .idivq_to_divl,
+            .invpcid,
+            .lzcnt,
+            .macrofusion,
+            .mmx,
+            .movbe,
+            .movdir64b,
+            .movdiri,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pconfig,
             .pku,
 @@ -2273,6 +2419,7 @@ pub const cpu = struct {
             .sha,
             .shstk,
             .tsxldtrk,
+            .tuning_fast_imm_vector_shift,
             .uintr,
             .vaes,
             .vpclmulqdq,
 @@ -2315,6 +2462,8 @@ pub const cpu = struct {
             .macrofusion,
             .mmx,
             .movbe,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pclmul,
             .popcnt,
 @@ -2405,6 +2554,9 @@ pub const cpu = struct {
             .macrofusion,
             .mmx,
             .movbe,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pku,
             .popcnt,
 @@ -2415,6 +2567,7 @@ pub const cpu = struct {
             .rdseed,
             .sahf,
             .sha,
+            .tuning_fast_imm_vector_shift,
             .vaes,
             .vpclmulqdq,
             .vzeroupper,
 @@ -2465,6 +2618,9 @@ pub const cpu = struct {
             .macrofusion,
             .mmx,
             .movbe,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pconfig,
             .pku,
 @@ -2476,6 +2632,7 @@ pub const cpu = struct {
             .rdseed,
             .sahf,
             .sha,
+            .tuning_fast_imm_vector_shift,
             .vaes,
             .vpclmulqdq,
             .vzeroupper,
 @@ -2504,6 +2661,7 @@ pub const cpu = struct {
             .idivq_to_divl,
             .macrofusion,
             .mmx,
+            .no_bypass_delay_mov,
             .nopl,
             .pclmul,
             .popcnt,
 @@ -2717,10 +2875,14 @@ pub const cpu = struct {
             .movbe,
             .movdir64b,
             .movdiri,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pconfig,
             .pku,
             .popcnt,
+            .prefer_movmsk_over_vtest,
             .prfchw,
             .ptwrite,
             .rdpid,
 @@ -2731,6 +2893,7 @@ pub const cpu = struct {
             .sha,
             .shstk,
             .slow_3ops_lea,
+            .tuning_fast_imm_vector_shift,
             .vaes,
             .vpclmulqdq,
             .vzeroupper,
 @@ -2753,6 +2916,7 @@ pub const cpu = struct {
             .fxsr,
             .macrofusion,
             .mmx,
+            .no_bypass_delay_mov,
             .nopl,
             .popcnt,
             .sahf,
 @@ -2902,21 +3066,6 @@ pub const cpu = struct {
             .x87,
         }),
     };
-    pub const pentium4m = CpuModel{
-        .name = "pentium4m",
-        .llvm_name = "pentium4m",
-        .features = featureSet(&[_]Feature{
-            .cmov,
-            .cx8,
-            .fxsr,
-            .mmx,
-            .nopl,
-            .slow_unaligned_mem_16,
-            .sse2,
-            .vzeroupper,
-            .x87,
-        }),
-    };
     pub const pentium_m = CpuModel{
         .name = "pentium_m",
         .llvm_name = "pentium-m",
 @@ -3009,10 +3158,14 @@ pub const cpu = struct {
             .movbe,
             .movdir64b,
             .movdiri,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pconfig,
             .pku,
             .popcnt,
+            .prefer_movmsk_over_vtest,
             .prfchw,
             .ptwrite,
             .rdpid,
 @@ -3023,6 +3176,7 @@ pub const cpu = struct {
             .sha,
             .shstk,
             .slow_3ops_lea,
+            .tuning_fast_imm_vector_shift,
             .vaes,
             .vpclmulqdq,
             .vzeroupper,
 @@ -3074,6 +3228,9 @@ pub const cpu = struct {
             .macrofusion,
             .mmx,
             .movbe,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pku,
             .popcnt,
 @@ -3084,6 +3241,7 @@ pub const cpu = struct {
             .rdseed,
             .sahf,
             .sha,
+            .tuning_fast_imm_vector_shift,
             .vaes,
             .vpclmulqdq,
             .vzeroupper,
 @@ -3110,6 +3268,7 @@ pub const cpu = struct {
             .idivq_to_divl,
             .macrofusion,
             .mmx,
+            .no_bypass_delay_mov,
             .nopl,
             .pclmul,
             .popcnt,
 @@ -3174,6 +3333,9 @@ pub const cpu = struct {
             .movbe,
             .movdir64b,
             .movdiri,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pconfig,
             .pku,
 @@ -3189,6 +3351,7 @@ pub const cpu = struct {
             .sha,
             .shstk,
             .tsxldtrk,
+            .tuning_fast_imm_vector_shift,
             .uintr,
             .vaes,
             .vpclmulqdq,
 @@ -3220,6 +3383,7 @@ pub const cpu = struct {
             .cmpccxadd,
             .crc32,
             .cx16,
+            .enqcmd,
             .f16c,
             .fast_movbe,
             .fma,
 @@ -3233,6 +3397,7 @@ pub const cpu = struct {
             .movbe,
             .movdir64b,
             .movdiri,
+            .no_bypass_delay,
             .nopl,
             .pconfig,
             .pku,
 @@ -3249,6 +3414,7 @@ pub const cpu = struct {
             .slow_incdec,
             .slow_lea,
             .slow_two_mem_ops,
+            .uintr,
             .use_glm_div_sqrt_costs,
             .vaes,
             .vpclmulqdq,
 @@ -3276,6 +3442,7 @@ pub const cpu = struct {
             .idivq_to_divl,
             .mmx,
             .movbe,
+            .no_bypass_delay,
             .nopl,
             .pclmul,
             .popcnt,
 @@ -3320,6 +3487,7 @@ pub const cpu = struct {
             .fast_variable_crosslane_shuffle,
             .fast_variable_perlane_shuffle,
             .fast_vector_fsqrt,
+            .faster_shift_than_shuffle,
             .fsgsbase,
             .fxsr,
             .idivq_to_divl,
 @@ -3328,6 +3496,9 @@ pub const cpu = struct {
             .macrofusion,
             .mmx,
             .movbe,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pclmul,
             .pku,
 @@ -3338,6 +3509,7 @@ pub const cpu = struct {
             .rdseed,
             .sahf,
             .slow_3ops_lea,
+            .tuning_fast_imm_vector_shift,
             .vzeroupper,
             .x87,
             .xsavec,
 @@ -3379,6 +3551,9 @@ pub const cpu = struct {
             .macrofusion,
             .mmx,
             .movbe,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pclmul,
             .popcnt,
 @@ -3394,59 +3569,6 @@ pub const cpu = struct {
             .xsaves,
         }),
     };
-    pub const skylake_avx512 = CpuModel{
-        .name = "skylake_avx512",
-        .llvm_name = "skylake-avx512",
-        .features = featureSet(&[_]Feature{
-            .@"64bit",
-            .adx,
-            .aes,
-            .allow_light_256_bit,
-            .avx512bw,
-            .avx512cd,
-            .avx512dq,
-            .avx512vl,
-            .bmi,
-            .bmi2,
-            .clflushopt,
-            .clwb,
-            .cmov,
-            .crc32,
-            .cx16,
-            .ermsb,
-            .false_deps_popcnt,
-            .fast_15bytenop,
-            .fast_gather,
-            .fast_scalar_fsqrt,
-            .fast_shld_rotate,
-            .fast_variable_crosslane_shuffle,
-            .fast_variable_perlane_shuffle,
-            .fast_vector_fsqrt,
-            .fsgsbase,
-            .fxsr,
-            .idivq_to_divl,
-            .invpcid,
-            .lzcnt,
-            .macrofusion,
-            .mmx,
-            .movbe,
-            .nopl,
-            .pclmul,
-            .pku,
-            .popcnt,
-            .prefer_256_bit,
-            .prfchw,
-            .rdrnd,
-            .rdseed,
-            .sahf,
-            .slow_3ops_lea,
-            .vzeroupper,
-            .x87,
-            .xsavec,
-            .xsaveopt,
-            .xsaves,
-        }),
-    };
     pub const slm = CpuModel{
         .name = "slm",
         .llvm_name = "slm",
 @@ -3462,6 +3584,7 @@ pub const cpu = struct {
             .idivq_to_divl,
             .mmx,
             .movbe,
+            .no_bypass_delay,
             .nopl,
             .pclmul,
             .popcnt,
 @@ -3522,6 +3645,9 @@ pub const cpu = struct {
             .movbe,
             .movdir64b,
             .movdiri,
+            .no_bypass_delay_blend,
+            .no_bypass_delay_mov,
+            .no_bypass_delay_shuffle,
             .nopl,
             .pku,
             .popcnt,
 @@ -3533,6 +3659,7 @@ pub const cpu = struct {
             .sahf,
             .sha,
             .shstk,
+            .tuning_fast_imm_vector_shift,
             .vaes,
             .vpclmulqdq,
             .vzeroupper,
 @@ -3559,6 +3686,7 @@ pub const cpu = struct {
             .gfni,
             .mmx,
             .movbe,
+            .no_bypass_delay,
             .nopl,
             .pclmul,
             .popcnt,
 @@ -3592,6 +3720,7 @@ pub const cpu = struct {
             .fxsr,
             .macrofusion,
             .mmx,
+            .no_bypass_delay_mov,
             .nopl,
             .pclmul,
             .popcnt,

tools/update_cpu_features.zig+39

...	@@ -40,6 +40,7 @@ const LlvmTarget = struct {	...	@@ -40,6 +40,7 @@ const LlvmTarget = struct {
40	feature_overrides: []const FeatureOverride = &.{},	40	feature_overrides: []const FeatureOverride = &.{},
41	extra_cpus: []const Cpu = &.{},	41	extra_cpus: []const Cpu = &.{},
42	extra_features: []const Feature = &.{},	42	extra_features: []const Feature = &.{},
		43	omit_cpus: []const []const u8 = &.{},
43	branch_quota: ?usize = null,	44	branch_quota: ?usize = null,
44	};	45	};
45		46
...	@@ -915,6 +916,40 @@ const llvm_targets = [_]LlvmTarget{	...	@@ -915,6 +916,40 @@ const llvm_targets = [_]LlvmTarget{
915	.extra_deps = &.{"soft_float"},	916	.extra_deps = &.{"soft_float"},
916	},	917	},
917	},	918	},
		919	.omit_cpus = &.{
		920	// LLVM defines a bunch of dumb aliases with foreach loops in X86.td.
		921	"pentium_mmx",
		922	"pentium_pro",
		923	"pentium_ii",
		924	"pentium_3m",
		925	"pentium_iii_no_xmm_regs",
		926	"pentium_iii",
		927	"pentium_m",
		928	"pentium4m",
		929	"pentium_4",
		930	"pentium_4_sse3",
		931	"core_2_duo_ssse3",
		932	"core_2_duo_sse4_1",
		933	"atom_sse4_2",
		934	"goldmont_plus",
		935	"core_i7_sse4_2",
		936	"core_aes_pclmulqdq",
		937	"corei7-avx",
		938	"core_2nd_gen_avx",
		939	"core-avx-i",
		940	"core_3rd_gen_avx",
		941	"core-avx2",
		942	"core_4th_gen_avx",
		943	"core_4th_gen_avx_tsx",
		944	"core_5th_gen_avx",
		945	"core_5th_gen_avx_tsx",
		946	"mic_avx512",
		947	"skylake_avx512",
		948	"skylake-avx512",
		949	"icelake_client",
		950	"icelake_server",
		951	"graniterapids_d",
		952	},
918	},	953	},
919	.{	954	.{
920	.zig_name = "xcore",	955	.zig_name = "xcore",
...	@@ -1129,6 +1164,10 @@ fn processOneTarget(job: Job) anyerror!void {	...	@@ -1129,6 +1164,10 @@ fn processOneTarget(job: Job) anyerror!void {
1129	if (hasSuperclass(&kv.value_ptr.object, "Processor")) {	1164	if (hasSuperclass(&kv.value_ptr.object, "Processor")) {
1130	const llvm_name = kv.value_ptr.object.get("Name").?.string;	1165	const llvm_name = kv.value_ptr.object.get("Name").?.string;
1131	if (llvm_name.len == 0) continue;	1166	if (llvm_name.len == 0) continue;
		1167	const omitted = for (llvm_target.omit_cpus) \|omit_cpu_name\| {
		1168	if (mem.eql(u8, omit_cpu_name, llvm_name)) break true;
		1169	} else false;
		1170	if (omitted) continue;
1132		1171
1133	var zig_name = try llvmNameToZigName(arena, llvm_name);	1172	var zig_name = try llvmNameToZigName(arena, llvm_name);
1134	var deps = std.ArrayList([]const u8).init(arena);	1173	var deps = std.ArrayList([]const u8).init(arena);

...	@@ -214,7 +214,7 @@ pub const all_features = blk: {	...	@@ -214,7 +214,7 @@ pub const all_features = blk: {
214	};	214	};
215	result[@intFromEnum(Feature.dsp_silan)] = .{	215	result[@intFromEnum(Feature.dsp_silan)] = .{
216	.llvm_name = "dsp_silan",	216	.llvm_name = "dsp_silan",
217	.description = "Enable DSP Silan instructions",	217	.description = "Enable DSP Silan instrutions",
218	.dependencies = featureSet(&[_]Feature{}),	218	.dependencies = featureSet(&[_]Feature{}),
219	};	219	};
220	result[@intFromEnum(Feature.dspe60)] = .{	220	result[@intFromEnum(Feature.dspe60)] = .{
...	@@ -224,7 +224,7 @@ pub const all_features = blk: {	...	@@ -224,7 +224,7 @@ pub const all_features = blk: {
224	};	224	};
225	result[@intFromEnum(Feature.dspv2)] = .{	225	result[@intFromEnum(Feature.dspv2)] = .{
226	.llvm_name = "dspv2",	226	.llvm_name = "dspv2",
227	.description = "Enable DSP V2.0 instructions",	227	.description = "Enable DSP V2.0 instrutions",
228	.dependencies = featureSet(&[_]Feature{}),	228	.dependencies = featureSet(&[_]Feature{}),
229	};	229	};
230	result[@intFromEnum(Feature.e1)] = .{	230	result[@intFromEnum(Feature.e1)] = .{
...	@@ -243,7 +243,7 @@ pub const all_features = blk: {	...	@@ -243,7 +243,7 @@ pub const all_features = blk: {
243	};	243	};
244	result[@intFromEnum(Feature.edsp)] = .{	244	result[@intFromEnum(Feature.edsp)] = .{
245	.llvm_name = "edsp",	245	.llvm_name = "edsp",
246	.description = "Enable DSP instructions",	246	.description = "Enable DSP instrutions",
247	.dependencies = featureSet(&[_]Feature{}),	247	.dependencies = featureSet(&[_]Feature{}),
248	};	248	};
249	result[@intFromEnum(Feature.elrw)] = .{	249	result[@intFromEnum(Feature.elrw)] = .{
...	@@ -298,12 +298,12 @@ pub const all_features = blk: {	...	@@ -298,12 +298,12 @@ pub const all_features = blk: {
298	};	298	};
299	result[@intFromEnum(Feature.fpuv3_hf)] = .{	299	result[@intFromEnum(Feature.fpuv3_hf)] = .{
300	.llvm_name = "fpuv3_hf",	300	.llvm_name = "fpuv3_hf",
301	.description = "Enable FPUv3 harf precision operate instructions",	301	.description = "Enable FPUv3 half precision operate instructions",
302	.dependencies = featureSet(&[_]Feature{}),	302	.dependencies = featureSet(&[_]Feature{}),
303	};	303	};
304	result[@intFromEnum(Feature.fpuv3_hi)] = .{	304	result[@intFromEnum(Feature.fpuv3_hi)] = .{
305	.llvm_name = "fpuv3_hi",	305	.llvm_name = "fpuv3_hi",
306	.description = "Enable FPUv3 harf word converting instructions",	306	.description = "Enable FPUv3 half word converting instructions",
307	.dependencies = featureSet(&[_]Feature{}),	307	.dependencies = featureSet(&[_]Feature{}),
308	};	308	};
309	result[@intFromEnum(Feature.fpuv3_sf)] = .{	309	result[@intFromEnum(Feature.fpuv3_sf)] = .{
...	@@ -333,12 +333,12 @@ pub const all_features = blk: {	...	@@ -333,12 +333,12 @@ pub const all_features = blk: {
333	};	333	};
334	result[@intFromEnum(Feature.hwdiv)] = .{	334	result[@intFromEnum(Feature.hwdiv)] = .{
335	.llvm_name = "hwdiv",	335	.llvm_name = "hwdiv",
336	.description = "Enable divide instructions",	336	.description = "Enable divide instrutions",
337	.dependencies = featureSet(&[_]Feature{}),	337	.dependencies = featureSet(&[_]Feature{}),
338	};	338	};
339	result[@intFromEnum(Feature.istack)] = .{	339	result[@intFromEnum(Feature.istack)] = .{
340	.llvm_name = "istack",	340	.llvm_name = "istack",
341	.description = "Enable interrupt attribute",	341	.description = "Enable interrput attribute",
342	.dependencies = featureSet(&[_]Feature{}),	342	.dependencies = featureSet(&[_]Feature{}),
343	};	343	};
344	result[@intFromEnum(Feature.java)] = .{	344	result[@intFromEnum(Feature.java)] = .{
...	@@ -362,7 +362,7 @@ pub const all_features = blk: {	...	@@ -362,7 +362,7 @@ pub const all_features = blk: {
362	};	362	};
363	result[@intFromEnum(Feature.multiple_stld)] = .{	363	result[@intFromEnum(Feature.multiple_stld)] = .{
364	.llvm_name = "multiple_stld",	364	.llvm_name = "multiple_stld",
365	.description = "Enable multiple load/store instructions",	365	.description = "Enable multiple load/store instrutions",
366	.dependencies = featureSet(&[_]Feature{}),	366	.dependencies = featureSet(&[_]Feature{}),
367	};	367	};
368	result[@intFromEnum(Feature.nvic)] = .{	368	result[@intFromEnum(Feature.nvic)] = .{
...	@@ -372,7 +372,7 @@ pub const all_features = blk: {	...	@@ -372,7 +372,7 @@ pub const all_features = blk: {
372	};	372	};
373	result[@intFromEnum(Feature.pushpop)] = .{	373	result[@intFromEnum(Feature.pushpop)] = .{
374	.llvm_name = "pushpop",	374	.llvm_name = "pushpop",
375	.description = "Enable push/pop instructions",	375	.description = "Enable push/pop instrutions",
376	.dependencies = featureSet(&[_]Feature{}),	376	.dependencies = featureSet(&[_]Feature{}),
377	};	377	};
378	result[@intFromEnum(Feature.smart)] = .{	378	result[@intFromEnum(Feature.smart)] = .{
...	@@ -3079,7 +3079,7 @@ pub const cpu = struct {	...	@@ -3079,7 +3079,7 @@ pub const cpu = struct {
3079	.btst16,	3079	.btst16,
3080	}),	3080	}),
3081	};	3081	};
3082	pub const @"i805" = CpuModel{	3082	pub const i805 = CpuModel{
3083	.name = "i805",	3083	.name = "i805",
3084	.llvm_name = "i805",	3084	.llvm_name = "i805",
3085	.features = featureSet(&[_]Feature{	3085	.features = featureSet(&[_]Feature{