authorgravatar for techatrix@mailbox.orgTechatrix <techatrix@mailbox.org> 2026-08-03 22:02:28+02:00
committergravatar for techatrix@mailbox.orgTechatrix <techatrix@mailbox.org> 2026-08-05 15:27:02+02:00
log46f98e366b10e1db59ca776c8cefcf827a66ffde
treec99db5f18662ca7810bb363d538a265cf3970e24
parentfd13c819264007e8731fdb5ae9af211d18c70e9a
signaturebadge-check Signed by SSH key SHA256:HYC3SjXQcAt6uwv9pu/6OoVQ2rUH8rb5zKiUHSe9uxk

c_abi: fix single element array on s390x

2 files changed, 1 insertions(+), 11 deletions(-)

src/codegen/s390x/abi.zig+1-8
...@@ -45,14 +45,7 @@ pub fn classifyType(ty: Type, context: Context, zcu: *Zcu) Class {...@@ -45,14 +45,7 @@ pub fn classifyType(ty: Type, context: Context, zcu: *Zcu) Class {
45 128 => return .pointer,45 128 => return .pointer,
46 },46 },
47 .pointer, .optional => return .simple,47 .pointer, .optional => return .simple,
48 .array => switch (ty.arrayLenIncludingSentinel(zcu)) {48 .array => {},
49 0 => return .none,
50 1 => switch (context) {
51 .ret => {},
52 .arg => return classifyType(ty.childType(zcu), context, zcu),
53 },
54 else => {},
55 },
56 .@"struct", .@"union" => |tag| switch (ty.containerLayout(zcu)) {49 .@"struct", .@"union" => |tag| switch (ty.containerLayout(zcu)) {
57 .auto => unreachable,50 .auto => unreachable,
58 .@"extern" => switch (context) {51 .@"extern" => switch (context) {
test/c_abi/main.zig-3
...@@ -16153,7 +16153,6 @@ test "struct [1]f32" {...@@ -16153,7 +16153,6 @@ test "struct [1]f32" {
16153 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16153 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16154 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16154 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16155 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;16155 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
16156 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1615716156
16158 const s = c_ret_struct_array_1_f32();16157 const s = c_ret_struct_array_1_f32();
16159 try expect(s.a[0] == 4);16158 try expect(s.a[0] == 4);
...@@ -16321,7 +16320,6 @@ test "struct [0:sentinel]f32" {...@@ -16321,7 +16320,6 @@ test "struct [0:sentinel]f32" {
16321 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16320 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16322 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16321 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16323 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;16322 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
16324 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1632516323
16326 var sentinel_index: usize = 0;16324 var sentinel_index: usize = 0;
16327 _ = &sentinel_index;16325 _ = &sentinel_index;
...@@ -16802,7 +16800,6 @@ test "struct [1]f64" {...@@ -16802,7 +16800,6 @@ test "struct [1]f64" {
16802 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;16800 if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest;
16803 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;16801 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
16804 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;16802 if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
16805 if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
1680616803
16807 const s = c_ret_struct_array_1_f64();16804 const s = c_ret_struct_array_1_f64();
16808 try expect(s.a[0] == 4);16805 try expect(s.a[0] == 4);