| ... | ... | @@ -16153,7 +16153,6 @@ test "struct [1]f32" { |
| 16153 | 16153 | if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest; |
| 16154 | 16154 | if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; |
| 16155 | 16155 | if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest; |
| 16156 | | if (builtin.cpu.arch == .s390x) return error.SkipZigTest; |
| 16157 | 16156 | |
| 16158 | 16157 | const s = c_ret_struct_array_1_f32(); |
| 16159 | 16158 | try expect(s.a[0] == 4); |
| ... | ... | @@ -16321,7 +16320,6 @@ test "struct [0:sentinel]f32" { |
| 16321 | 16320 | if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest; |
| 16322 | 16321 | if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; |
| 16323 | 16322 | if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest; |
| 16324 | | if (builtin.cpu.arch == .s390x) return error.SkipZigTest; |
| 16325 | 16323 | |
| 16326 | 16324 | var sentinel_index: usize = 0; |
| 16327 | 16325 | _ = &sentinel_index; |
| ... | ... | @@ -16802,7 +16800,6 @@ test "struct [1]f64" { |
| 16802 | 16800 | if (builtin.cpu.arch.isMIPS64()) return error.SkipZigTest; |
| 16803 | 16801 | if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; |
| 16804 | 16802 | if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest; |
| 16805 | | if (builtin.cpu.arch == .s390x) return error.SkipZigTest; |
| 16806 | 16803 | |
| 16807 | 16804 | const s = c_ret_struct_array_1_f64(); |
| 16808 | 16805 | try expect(s.a[0] == 4); |