authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-11-20 06:38:51+01:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-11-21 12:15:15+01:00
log47df2f9abe204849198084e367312db94aeca405
treea3b7314bb48c3dd3aa29648f3fc61d10b8e3cfc1
parent534370c4dede07c692ced0c5526a5370f233b4d3
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.zig.system.linux: don't arbitrarily limit sparc CPU detection to 64-bit

1 files changed, 1 insertions(+), 7 deletions(-)

lib/std/zig/system/linux.zig+1-7
...@@ -11,7 +11,6 @@ const assert = std.debug.assert;...@@ -11,7 +11,6 @@ const assert = std.debug.assert;
1111
12const SparcCpuinfoImpl = struct {12const SparcCpuinfoImpl = struct {
13 model: ?*const Target.Cpu.Model = null,13 model: ?*const Target.Cpu.Model = null,
14 is_64bit: bool = false,
1514
16 const cpu_names = .{15 const cpu_names = .{
17 .{ "SuperSparc", &Target.sparc.cpu.supersparc },16 .{ "SuperSparc", &Target.sparc.cpu.supersparc },
...@@ -41,17 +40,12 @@ const SparcCpuinfoImpl = struct {...@@ -41,17 +40,12 @@ const SparcCpuinfoImpl = struct {
41 break;40 break;
42 }41 }
43 }42 }
44 } else if (mem.eql(u8, key, "type")) {
45 self.is_64bit = mem.eql(u8, value, "sun4u") or mem.eql(u8, value, "sun4v");
46 }43 }
4744
48 return true;45 return true;
49 }46 }
5047
51 fn finalize(self: *const SparcCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {48 fn finalize(self: *const SparcCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
52 // At the moment we only support 64bit SPARC systems.
53 assert(self.is_64bit);
54
55 const model = self.model orelse return null;49 const model = self.model orelse return null;
56 return Target.Cpu{50 return Target.Cpu{
57 .arch = arch,51 .arch = arch,
...@@ -411,7 +405,7 @@ pub fn detectNativeCpuAndFeatures(io: Io) ?Target.Cpu {...@@ -411,7 +405,7 @@ pub fn detectNativeCpuAndFeatures(io: Io) ?Target.Cpu {
411 const core = @import("arm.zig").aarch64.detectNativeCpuAndFeatures(current_arch, registers);405 const core = @import("arm.zig").aarch64.detectNativeCpuAndFeatures(current_arch, registers);
412 return core;406 return core;
413 },407 },
414 .sparc64 => {408 .sparc, .sparc64 => {
415 return SparcCpuinfoParser.parse(current_arch, &file_reader.interface) catch null;409 return SparcCpuinfoParser.parse(current_arch, &file_reader.interface) catch null;
416 },410 },
417 .powerpc, .powerpcle, .powerpc64, .powerpc64le => {411 .powerpc, .powerpcle, .powerpc64, .powerpc64le => {