| ... | ... | @@ -11,7 +11,6 @@ const assert = std.debug.assert; |
| 11 | 11 | |
| 12 | 12 | const SparcCpuinfoImpl = struct { |
| 13 | 13 | model: ?*const Target.Cpu.Model = null, |
| 14 | | is_64bit: bool = false, |
| 15 | 14 | |
| 16 | 15 | const cpu_names = .{ |
| 17 | 16 | .{ "SuperSparc", &Target.sparc.cpu.supersparc }, |
| ... | ... | @@ -41,17 +40,12 @@ const SparcCpuinfoImpl = struct { |
| 41 | 40 | break; |
| 42 | 41 | } |
| 43 | 42 | } |
| 44 | | } else if (mem.eql(u8, key, "type")) { |
| 45 | | self.is_64bit = mem.eql(u8, value, "sun4u") or mem.eql(u8, value, "sun4v"); |
| 46 | 43 | } |
| 47 | 44 | |
| 48 | 45 | return true; |
| 49 | 46 | } |
| 50 | 47 | |
| 51 | 48 | fn finalize(self: *const SparcCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu { |
| 52 | | // At the moment we only support 64bit SPARC systems. |
| 53 | | assert(self.is_64bit); |
| 54 | | |
| 55 | 49 | const model = self.model orelse return null; |
| 56 | 50 | return Target.Cpu{ |
| 57 | 51 | .arch = arch, |
| ... | ... | @@ -411,7 +405,7 @@ pub fn detectNativeCpuAndFeatures(io: Io) ?Target.Cpu { |
| 411 | 405 | const core = @import("arm.zig").aarch64.detectNativeCpuAndFeatures(current_arch, registers); |
| 412 | 406 | return core; |
| 413 | 407 | }, |
| 414 | | .sparc64 => { |
| 408 | .sparc, .sparc64 => { |
| 415 | 409 | return SparcCpuinfoParser.parse(current_arch, &file_reader.interface) catch null; |
| 416 | 410 | }, |
| 417 | 411 | .powerpc, .powerpcle, .powerpc64, .powerpc64le => { |
Alex Rønne Petersen <alex@alexrp.com> 2025-11-20 06:38:51+01:00
Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM
lib