authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-14 05:12:46-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-15 03:07:51-04:00
log6c6d8d67cfe14c50684c04a579c1e62bf287e8cb
tree22be2a1952c3077a0c60c66fb4b2f47684c5bf43
parentb6d61028508c5b1e1961a124bc17d4d9bda9686f

x86_64: redo movement, float negation, and `@fabs`

8 files changed, 359 insertions(+), 118 deletions(-)

src/arch/x86_64/CodeGen.zig+248-109
...@@ -4681,61 +4681,136 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {...@@ -4681,61 +4681,136 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {
4681}4681}
46824682
4683fn airFloatSign(self: *Self, inst: Air.Inst.Index) !void {4683fn airFloatSign(self: *Self, inst: Air.Inst.Index) !void {
4684 const tag = self.air.instructions.items(.tag)[inst];
4684 const un_op = self.air.instructions.items(.data)[inst].un_op;4685 const un_op = self.air.instructions.items(.data)[inst].un_op;
4685 const ty = self.air.typeOf(un_op);4686 const ty = self.air.typeOf(un_op);
4686 const ty_bits = ty.floatBits(self.target.*);4687 const abi_size: u32 = switch (ty.abiSize(self.target.*)) {
4688 1...16 => 16,
4689 17...32 => 32,
4690 else => return self.fail("TODO implement airFloatSign for {}", .{
4691 ty.fmt(self.bin_file.options.module.?),
4692 }),
4693 };
4694 const scalar_bits = ty.scalarType().floatBits(self.target.*);
4695
4696 const src_mcv = try self.resolveInst(un_op);
4697 const src_lock = if (src_mcv.getReg()) |reg| self.register_manager.lockReg(reg) else null;
4698 defer if (src_lock) |lock| self.register_manager.unlockReg(lock);
4699
4700 const dst_mcv: MCValue = if (src_mcv.isRegister() and self.reuseOperand(inst, un_op, 0, src_mcv))
4701 src_mcv
4702 else if (self.hasFeature(.avx))
4703 .{ .register = try self.register_manager.allocReg(inst, sse) }
4704 else
4705 try self.copyToRegisterWithInstTracking(inst, ty, src_mcv);
4706 const dst_reg = dst_mcv.getReg().?;
4707 const dst_lock = self.register_manager.lockReg(dst_reg);
4708 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
46874709
4688 var arena = std.heap.ArenaAllocator.init(self.gpa);4710 var arena = std.heap.ArenaAllocator.init(self.gpa);
4689 defer arena.deinit();4711 defer arena.deinit();
46904712
4691 const ExpectedContents = union {4713 const ExpectedContents = struct {
4692 f16: Value.Payload.Float_16,4714 scalar: union {
4693 f32: Value.Payload.Float_32,4715 i64: Value.Payload.I64,
4694 f64: Value.Payload.Float_64,4716 big: struct {
4695 f80: Value.Payload.Float_80,4717 limbs: [
4696 f128: Value.Payload.Float_128,4718 @max(
4719 std.math.big.int.Managed.default_capacity,
4720 std.math.big.int.calcTwosCompLimbCount(128),
4721 )
4722 ]std.math.big.Limb,
4723 pl: Value.Payload.BigInt,
4724 },
4725 },
4726 repeated: Value.Payload.SubValue,
4697 };4727 };
4698 var stack align(@alignOf(ExpectedContents)) =4728 var stack align(@alignOf(ExpectedContents)) =
4699 std.heap.stackFallback(@sizeOf(ExpectedContents), arena.allocator());4729 std.heap.stackFallback(@sizeOf(ExpectedContents), arena.allocator());
47004730
4731 var int_pl = Type.Payload.Bits{
4732 .base = .{ .tag = .int_signed },
4733 .data = scalar_bits,
4734 };
4701 var vec_pl = Type.Payload.Array{4735 var vec_pl = Type.Payload.Array{
4702 .base = .{ .tag = .vector },4736 .base = .{ .tag = .vector },
4703 .data = .{4737 .data = .{
4704 .len = @divExact(128, ty_bits),4738 .len = @divExact(abi_size * 8, scalar_bits),
4705 .elem_type = ty,4739 .elem_type = Type.initPayload(&int_pl.base),
4706 },4740 },
4707 };4741 };
4708 const vec_ty = Type.initPayload(&vec_pl.base);4742 const vec_ty = Type.initPayload(&vec_pl.base);
47094743 const sign_val = switch (tag) {
4710 var sign_pl = Value.Payload.SubValue{4744 .neg => try vec_ty.minInt(stack.get(), self.target.*),
4711 .base = .{ .tag = .repeated },4745 .fabs => try vec_ty.maxInt(stack.get(), self.target.*),
4712 .data = try Value.floatToValue(-0.0, stack.get(), ty, self.target.*),4746 else => unreachable,
4713 };4747 };
4714 const sign_val = Value.initPayload(&sign_pl.base);
47154748
4716 const sign_mcv = try self.genTypedValue(.{ .ty = vec_ty, .val = sign_val });4749 const sign_mcv = try self.genTypedValue(.{ .ty = vec_ty, .val = sign_val });
47174750 const sign_mem = if (sign_mcv.isMemory())
4718 const src_mcv = try self.resolveInst(un_op);4751 sign_mcv.mem(Memory.PtrSize.fromSize(abi_size))
4719 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, un_op, 0, src_mcv))
4720 src_mcv
4721 else4752 else
4722 try self.copyToRegisterWithInstTracking(inst, ty, src_mcv);4753 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
4723 const dst_lock = self.register_manager.lockReg(dst_mcv.register);4754 .base = .{ .reg = try self.copyToTmpRegister(Type.usize, sign_mcv.address()) },
4724 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);4755 });
47254756
4726 const tag = self.air.instructions.items(.tag)[inst];4757 if (self.hasFeature(.avx)) try self.asmRegisterRegisterMemory(
4727 try self.genBinOpMir(switch (ty_bits) {4758 switch (scalar_bits) {
4728 // No point using an extra prefix byte for *pd which performs the same operation.4759 16, 128 => if (abi_size <= 16 or self.hasFeature(.avx2)) switch (tag) {
4729 16, 32, 64, 128 => switch (tag) {4760 .neg => .{ .vp_, .xor },
4730 .neg => .{ ._ps, .xor },4761 .fabs => .{ .vp_, .@"and" },
4731 .fabs => .{ ._ps, .andn },4762 else => unreachable,
4763 } else switch (tag) {
4764 .neg => .{ .v_ps, .xor },
4765 .fabs => .{ .v_ps, .@"and" },
4766 else => unreachable,
4767 },
4768 32 => switch (tag) {
4769 .neg => .{ .v_ps, .xor },
4770 .fabs => .{ .v_ps, .@"and" },
4771 else => unreachable,
4772 },
4773 64 => switch (tag) {
4774 .neg => .{ .v_pd, .xor },
4775 .fabs => .{ .v_pd, .@"and" },
4776 else => unreachable,
4777 },
4778 80 => return self.fail("TODO implement airFloatSign for {}", .{
4779 ty.fmt(self.bin_file.options.module.?),
4780 }),
4732 else => unreachable,4781 else => unreachable,
4733 },4782 },
4734 80 => return self.fail("TODO implement airFloatSign for {}", .{4783 registerAlias(dst_reg, abi_size),
4735 ty.fmt(self.bin_file.options.module.?),4784 registerAlias(if (src_mcv.isRegister())
4736 }),4785 src_mcv.getReg().?
4737 else => unreachable,4786 else
4738 }, vec_ty, dst_mcv, sign_mcv);4787 try self.copyToTmpRegister(ty, src_mcv), abi_size),
4788 sign_mem,
4789 ) else try self.asmRegisterMemory(
4790 switch (scalar_bits) {
4791 16, 128 => switch (tag) {
4792 .neg => .{ .p_, .xor },
4793 .fabs => .{ .p_, .@"and" },
4794 else => unreachable,
4795 },
4796 32 => switch (tag) {
4797 .neg => .{ ._ps, .xor },
4798 .fabs => .{ ._ps, .@"and" },
4799 else => unreachable,
4800 },
4801 64 => switch (tag) {
4802 .neg => .{ ._pd, .xor },
4803 .fabs => .{ ._pd, .@"and" },
4804 else => unreachable,
4805 },
4806 80 => return self.fail("TODO implement airFloatSign for {}", .{
4807 ty.fmt(self.bin_file.options.module.?),
4808 }),
4809 else => unreachable,
4810 },
4811 registerAlias(dst_reg, abi_size),
4812 sign_mem,
4813 );
4739 return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none });4814 return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none });
4740}4815}
47414816
...@@ -8593,7 +8668,6 @@ const MoveStrategy = union(enum) {...@@ -8593,7 +8668,6 @@ const MoveStrategy = union(enum) {
8593 const InsertExtract = struct {8668 const InsertExtract = struct {
8594 insert: Mir.Inst.FixedTag,8669 insert: Mir.Inst.FixedTag,
8595 extract: Mir.Inst.FixedTag,8670 extract: Mir.Inst.FixedTag,
8596 imm: Immediate,
8597 };8671 };
8598};8672};
8599fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {8673fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {
...@@ -8603,17 +8677,15 @@ fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {...@@ -8603,17 +8677,15 @@ fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {
8603 16 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{8677 16 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{
8604 .insert = .{ .vp_w, .insr },8678 .insert = .{ .vp_w, .insr },
8605 .extract = .{ .vp_w, .extr },8679 .extract = .{ .vp_w, .extr },
8606 .imm = Immediate.u(0),
8607 } } else .{ .insert_extract = .{8680 } } else .{ .insert_extract = .{
8608 .insert = .{ .p_w, .insr },8681 .insert = .{ .p_w, .insr },
8609 .extract = .{ .p_w, .extr },8682 .extract = .{ .p_w, .extr },
8610 .imm = Immediate.u(0),
8611 } },8683 } },
8612 32 => return .{ .move = if (self.hasFeature(.avx)) .{ .v_ss, .mov } else .{ ._ss, .mov } },8684 32 => return .{ .move = if (self.hasFeature(.avx)) .{ .v_ss, .mov } else .{ ._ss, .mov } },
8613 64 => return .{ .move = if (self.hasFeature(.avx)) .{ .v_sd, .mov } else .{ ._sd, .mov } },8685 64 => return .{ .move = if (self.hasFeature(.avx)) .{ .v_sd, .mov } else .{ ._sd, .mov } },
8614 128 => return .{ .move = if (self.hasFeature(.avx))8686 128 => return .{ .move = if (self.hasFeature(.avx))
8615 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }8687 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8616 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },8688 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
8617 else => {},8689 else => {},
8618 },8690 },
8619 .Vector => switch (ty.childType().zigTypeTag()) {8691 .Vector => switch (ty.childType().zigTypeTag()) {
...@@ -8622,101 +8694,120 @@ fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {...@@ -8622,101 +8694,120 @@ fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {
8622 1 => if (self.hasFeature(.avx)) return .{ .vex_insert_extract = .{8694 1 => if (self.hasFeature(.avx)) return .{ .vex_insert_extract = .{
8623 .insert = .{ .vp_b, .insr },8695 .insert = .{ .vp_b, .insr },
8624 .extract = .{ .vp_b, .extr },8696 .extract = .{ .vp_b, .extr },
8625 .imm = Immediate.u(0),
8626 } } else if (self.hasFeature(.sse4_2)) return .{ .insert_extract = .{8697 } } else if (self.hasFeature(.sse4_2)) return .{ .insert_extract = .{
8627 .insert = .{ .p_b, .insr },8698 .insert = .{ .p_b, .insr },
8628 .extract = .{ .p_b, .extr },8699 .extract = .{ .p_b, .extr },
8629 .imm = Immediate.u(0),
8630 } },8700 } },
8631 2 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{8701 2 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{
8632 .insert = .{ .vp_w, .insr },8702 .insert = .{ .vp_w, .insr },
8633 .extract = .{ .vp_w, .extr },8703 .extract = .{ .vp_w, .extr },
8634 .imm = Immediate.u(0),
8635 } } else .{ .insert_extract = .{8704 } } else .{ .insert_extract = .{
8636 .insert = .{ .p_w, .insr },8705 .insert = .{ .p_w, .insr },
8637 .extract = .{ .p_w, .extr },8706 .extract = .{ .p_w, .extr },
8638 .imm = Immediate.u(0),
8639 } },8707 } },
8640 3...4 => return .{ .move = if (self.hasFeature(.avx))8708 3...4 => return .{ .move = if (self.hasFeature(.avx))
8641 .{ .v_ss, .mov }8709 .{ .v_d, .mov }
8642 else8710 else
8643 .{ ._ss, .mov } },8711 .{ ._d, .mov } },
8644 5...8 => return .{ .move = if (self.hasFeature(.avx))8712 5...8 => return .{ .move = if (self.hasFeature(.avx))
8645 .{ .v_sd, .mov }8713 .{ .v_q, .mov }
8646 else8714 else
8647 .{ ._sd, .mov } },8715 .{ ._q, .mov } },
8716 9...16 => return .{ .move = if (self.hasFeature(.avx))
8717 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8718 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
8719 17...32 => if (self.hasFeature(.avx))
8720 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
8648 else => {},8721 else => {},
8649 },8722 },
8650 16 => switch (ty.vectorLen()) {8723 16 => switch (ty.vectorLen()) {
8651 1 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{8724 1 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{
8652 .insert = .{ .vp_w, .insr },8725 .insert = .{ .vp_w, .insr },
8653 .extract = .{ .vp_w, .extr },8726 .extract = .{ .vp_w, .extr },
8654 .imm = Immediate.u(0),
8655 } } else .{ .insert_extract = .{8727 } } else .{ .insert_extract = .{
8656 .insert = .{ .p_w, .insr },8728 .insert = .{ .p_w, .insr },
8657 .extract = .{ .p_w, .extr },8729 .extract = .{ .p_w, .extr },
8658 .imm = Immediate.u(0),
8659 } },8730 } },
8660 2 => return .{ .move = if (self.hasFeature(.avx))8731 2 => return .{ .move = if (self.hasFeature(.avx))
8661 .{ .v_ss, .mov }8732 .{ .v_d, .mov }
8662 else8733 else
8663 .{ ._ss, .mov } },8734 .{ ._d, .mov } },
8664 3...4 => return .{ .move = if (self.hasFeature(.avx))8735 3...4 => return .{ .move = if (self.hasFeature(.avx))
8665 .{ .v_sd, .mov }8736 .{ .v_q, .mov }
8666 else8737 else
8667 .{ ._sd, .mov } },8738 .{ ._q, .mov } },
8668 5...8 => return .{ .move = if (self.hasFeature(.avx))8739 5...8 => return .{ .move = if (self.hasFeature(.avx))
8669 .{ .v_ps, .mov }8740 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8670 else8741 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
8671 .{ ._ps, .mov } },8742 9...16 => if (self.hasFeature(.avx))
8743 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
8672 else => {},8744 else => {},
8673 },8745 },
8674 32 => switch (ty.vectorLen()) {8746 32 => switch (ty.vectorLen()) {
8675 1 => return .{ .move = if (self.hasFeature(.avx))8747 1 => return .{ .move = if (self.hasFeature(.avx))
8676 .{ .v_ss, .mov }8748 .{ .v_d, .mov }
8677 else8749 else
8678 .{ ._ss, .mov } },8750 .{ ._d, .mov } },
8679 2 => return .{ .move = if (self.hasFeature(.avx))8751 2 => return .{ .move = if (self.hasFeature(.avx))
8680 .{ .v_sd, .mov }8752 .{ .v_q, .mov }
8681 else8753 else
8682 .{ ._sd, .mov } },8754 .{ ._q, .mov } },
8683 3...4 => return .{ .move = if (self.hasFeature(.avx))8755 3...4 => return .{ .move = if (self.hasFeature(.avx))
8684 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }8756 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8685 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },8757 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
8686 5...8 => if (self.hasFeature(.avx))8758 5...8 => if (self.hasFeature(.avx))
8687 return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },8759 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
8688 else => {},8760 else => {},
8689 },8761 },
8690 64 => switch (ty.vectorLen()) {8762 64 => switch (ty.vectorLen()) {
8691 1 => return .{ .move = if (self.hasFeature(.avx))8763 1 => return .{ .move = if (self.hasFeature(.avx))
8692 .{ .v_sd, .mov }8764 .{ .v_q, .mov }
8693 else8765 else
8694 .{ ._sd, .mov } },8766 .{ ._q, .mov } },
8695 2 => return .{ .move = if (self.hasFeature(.avx))8767 2 => return .{ .move = if (self.hasFeature(.avx))
8696 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }8768 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8697 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },8769 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
8698 3...4 => if (self.hasFeature(.avx))8770 3...4 => if (self.hasFeature(.avx))
8699 return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },8771 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
8772 else => {},
8773 },
8774 128 => switch (ty.vectorLen()) {
8775 1 => return .{ .move = if (self.hasFeature(.avx))
8776 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8777 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
8778 2 => if (self.hasFeature(.avx))
8779 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
8780 else => {},
8781 },
8782 256 => switch (ty.vectorLen()) {
8783 1 => if (self.hasFeature(.avx))
8784 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
8700 else => {},8785 else => {},
8701 },8786 },
8702 else => {},8787 else => {},
8703 },8788 },
8704 .Float => switch (ty.childType().floatBits(self.target.*)) {8789 .Float => switch (ty.childType().floatBits(self.target.*)) {
8705 16 => switch (ty.vectorLen()) {8790 16 => switch (ty.vectorLen()) {
8706 1 => {},8791 1 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{
8792 .insert = .{ .vp_w, .insr },
8793 .extract = .{ .vp_w, .extr },
8794 } } else .{ .insert_extract = .{
8795 .insert = .{ .p_w, .insr },
8796 .extract = .{ .p_w, .extr },
8797 } },
8707 2 => return .{ .move = if (self.hasFeature(.avx))8798 2 => return .{ .move = if (self.hasFeature(.avx))
8708 .{ .v_ss, .mov }8799 .{ .v_d, .mov }
8709 else8800 else
8710 .{ ._ss, .mov } },8801 .{ ._d, .mov } },
8711 3...4 => return .{ .move = if (self.hasFeature(.avx))8802 3...4 => return .{ .move = if (self.hasFeature(.avx))
8712 .{ .v_sd, .mov }8803 .{ .v_q, .mov }
8713 else8804 else
8714 .{ ._sd, .mov } },8805 .{ ._q, .mov } },
8715 5...8 => return .{ .move = if (self.hasFeature(.avx))8806 5...8 => return .{ .move = if (self.hasFeature(.avx))
8716 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }8807 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8717 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },8808 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
8718 9...16 => if (self.hasFeature(.avx))8809 9...16 => if (self.hasFeature(.avx))
8719 return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },8810 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
8720 else => {},8811 else => {},
8721 },8812 },
8722 32 => switch (ty.vectorLen()) {8813 32 => switch (ty.vectorLen()) {
...@@ -8741,18 +8832,18 @@ fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {...@@ -8741,18 +8832,18 @@ fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {
8741 else8832 else
8742 .{ ._sd, .mov } },8833 .{ ._sd, .mov } },
8743 2 => return .{ .move = if (self.hasFeature(.avx))8834 2 => return .{ .move = if (self.hasFeature(.avx))
8744 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }8835 if (aligned) .{ .v_pd, .mova } else .{ .v_pd, .movu }
8745 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },8836 else if (aligned) .{ ._pd, .mova } else .{ ._pd, .movu } },
8746 3...4 => if (self.hasFeature(.avx))8837 3...4 => if (self.hasFeature(.avx))
8747 return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },8838 return .{ .move = if (aligned) .{ .v_pd, .mova } else .{ .v_pd, .movu } },
8748 else => {},8839 else => {},
8749 },8840 },
8750 128 => switch (ty.vectorLen()) {8841 128 => switch (ty.vectorLen()) {
8751 1 => return .{ .move = if (self.hasFeature(.avx))8842 1 => return .{ .move = if (self.hasFeature(.avx))
8752 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }8843 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8753 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },8844 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
8754 2 => if (self.hasFeature(.avx))8845 2 => if (self.hasFeature(.avx))
8755 return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },8846 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
8756 else => {},8847 else => {},
8757 },8848 },
8758 else => {},8849 else => {},
...@@ -8860,29 +8951,69 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -8860,29 +8951,69 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
8860 );8951 );
8861 }8952 }
8862 },8953 },
8863 .register => |src_reg| if (dst_reg.id() != src_reg.id()) try self.asmRegisterRegister(8954 .register => |src_reg| if (dst_reg.id() != src_reg.id()) switch (dst_reg.class()) {
8864 if ((dst_reg.class() == .sse) == (src_reg.class() == .sse))8955 .general_purpose => switch (src_reg.class()) {
8865 switch (ty.zigTypeTag()) {8956 .general_purpose => try self.asmRegisterRegister(
8866 else => .{ ._, .mov },8957 .{ ._, .mov },
8867 .Float, .Vector => .{ ._ps, .mova },8958 registerAlias(dst_reg, abi_size),
8868 }8959 registerAlias(src_reg, abi_size),
8869 else switch (abi_size) {
8870 2 => return try self.asmRegisterRegisterImmediate(
8871 if (dst_reg.class() == .sse) .{ .p_w, .insr } else .{ .p_w, .extr },
8872 registerAlias(dst_reg, 4),
8873 registerAlias(src_reg, 4),
8874 Immediate.u(0),
8875 ),8960 ),
8876 4 => .{ ._d, .mov },8961 .segment => try self.asmRegisterRegister(
8877 8 => .{ ._q, .mov },8962 .{ ._, .mov },
8878 else => return self.fail(8963 registerAlias(dst_reg, abi_size),
8879 "unsupported register copy from {s} to {s}",8964 src_reg,
8880 .{ @tagName(src_reg), @tagName(dst_reg) },
8881 ),8965 ),
8966 .sse => try self.asmRegisterRegister(
8967 switch (abi_size) {
8968 1...4 => if (self.hasFeature(.avx)) .{ .v_d, .mov } else .{ ._d, .mov },
8969 5...8 => if (self.hasFeature(.avx)) .{ .v_q, .mov } else .{ ._q, .mov },
8970 else => unreachable,
8971 },
8972 registerAlias(dst_reg, @max(abi_size, 4)),
8973 src_reg.to128(),
8974 ),
8975 .x87, .mmx => unreachable,
8882 },8976 },
8883 registerAlias(dst_reg, abi_size),8977 .segment => try self.asmRegisterRegister(
8884 registerAlias(src_reg, abi_size),8978 .{ ._, .mov },
8885 ),8979 dst_reg,
8980 switch (src_reg.class()) {
8981 .general_purpose, .segment => registerAlias(src_reg, abi_size),
8982 .sse => try self.copyToTmpRegister(ty, src_mcv),
8983 .x87, .mmx => unreachable,
8984 },
8985 ),
8986 .sse => switch (src_reg.class()) {
8987 .general_purpose => try self.asmRegisterRegister(
8988 switch (abi_size) {
8989 1...4 => if (self.hasFeature(.avx)) .{ .v_d, .mov } else .{ ._d, .mov },
8990 5...8 => if (self.hasFeature(.avx)) .{ .v_q, .mov } else .{ ._q, .mov },
8991 else => unreachable,
8992 },
8993 dst_reg.to128(),
8994 registerAlias(src_reg, @max(abi_size, 4)),
8995 ),
8996 .segment => try self.genSetReg(
8997 dst_reg,
8998 ty,
8999 .{ .register = try self.copyToTmpRegister(ty, src_mcv) },
9000 ),
9001 .sse => try self.asmRegisterRegister(
9002 switch (ty.scalarType().zigTypeTag()) {
9003 else => if (self.hasFeature(.avx)) .{ .v_, .movdqa } else .{ ._, .movdqa },
9004 .Float => switch (ty.floatBits(self.target.*)) {
9005 else => if (self.hasFeature(.avx)) .{ .v_, .movdqa } else .{ ._, .movdqa },
9006 32 => if (self.hasFeature(.avx)) .{ .v_ps, .mova } else .{ ._ps, .mova },
9007 64 => if (self.hasFeature(.avx)) .{ .v_pd, .mova } else .{ ._pd, .mova },
9008 },
9009 },
9010 registerAlias(dst_reg, abi_size),
9011 registerAlias(src_reg, abi_size),
9012 ),
9013 .x87, .mmx => unreachable,
9014 },
9015 .x87, .mmx => unreachable,
9016 },
8886 .register_offset,9017 .register_offset,
8887 .indirect,9018 .indirect,
8888 .load_frame,9019 .load_frame,
...@@ -8918,14 +9049,14 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -8918,14 +9049,14 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
8918 ie.insert,9049 ie.insert,
8919 dst_alias,9050 dst_alias,
8920 src_mem,9051 src_mem,
8921 ie.imm,9052 Immediate.u(0),
8922 ),9053 ),
8923 .vex_insert_extract => |ie| try self.asmRegisterRegisterMemoryImmediate(9054 .vex_insert_extract => |ie| try self.asmRegisterRegisterMemoryImmediate(
8924 ie.insert,9055 ie.insert,
8925 dst_alias,9056 dst_alias,
8926 dst_alias,9057 dst_alias,
8927 src_mem,9058 src_mem,
8928 ie.imm,9059 Immediate.u(0),
8929 ),9060 ),
8930 }9061 }
8931 },9062 },
...@@ -8947,14 +9078,14 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -8947,14 +9078,14 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
8947 ie.insert,9078 ie.insert,
8948 dst_alias,9079 dst_alias,
8949 src_mem,9080 src_mem,
8950 ie.imm,9081 Immediate.u(0),
8951 ),9082 ),
8952 .vex_insert_extract => |ie| try self.asmRegisterRegisterMemoryImmediate(9083 .vex_insert_extract => |ie| try self.asmRegisterRegisterMemoryImmediate(
8953 ie.insert,9084 ie.insert,
8954 dst_alias,9085 dst_alias,
8955 dst_alias,9086 dst_alias,
8956 src_mem,9087 src_mem,
8957 ie.imm,9088 Immediate.u(0),
8958 ),9089 ),
8959 }9090 }
8960 },9091 },
...@@ -8994,14 +9125,14 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -8994,14 +9125,14 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
8994 ie.insert,9125 ie.insert,
8995 dst_alias,9126 dst_alias,
8996 src_mem,9127 src_mem,
8997 ie.imm,9128 Immediate.u(0),
8998 ),9129 ),
8999 .vex_insert_extract => |ie| try self.asmRegisterRegisterMemoryImmediate(9130 .vex_insert_extract => |ie| try self.asmRegisterRegisterMemoryImmediate(
9000 ie.insert,9131 ie.insert,
9001 dst_alias,9132 dst_alias,
9002 dst_alias,9133 dst_alias,
9003 src_mem,9134 src_mem,
9004 ie.imm,9135 Immediate.u(0),
9005 ),9136 ),
9006 }9137 }
9007 },9138 },
...@@ -9129,7 +9260,7 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal...@@ -9129,7 +9260,7 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal
9129 ie.extract,9260 ie.extract,
9130 dst_mem,9261 dst_mem,
9131 src_alias,9262 src_alias,
9132 ie.imm,9263 Immediate.u(0),
9133 ),9264 ),
9134 }9265 }
9135 },9266 },
...@@ -10499,7 +10630,7 @@ fn airUnionInit(self: *Self, inst: Air.Inst.Index) !void {...@@ -10499,7 +10630,7 @@ fn airUnionInit(self: *Self, inst: Air.Inst.Index) !void {
10499 if (self.reuseOperand(inst, extra.init, 0, src_mcv)) break :result src_mcv;10630 if (self.reuseOperand(inst, extra.init, 0, src_mcv)) break :result src_mcv;
1050010631
10501 const dst_mcv = try self.allocRegOrMem(inst, true);10632 const dst_mcv = try self.allocRegOrMem(inst, true);
10502 try self.genCopy(src_ty, dst_mcv, src_mcv);10633 try self.genCopy(union_ty, dst_mcv, src_mcv);
10503 break :result dst_mcv;10634 break :result dst_mcv;
10504 }10635 }
1050510636
...@@ -11000,7 +11131,15 @@ fn registerAlias(reg: Register, size_bytes: u32) Register {...@@ -11000,7 +11131,15 @@ fn registerAlias(reg: Register, size_bytes: u32) Register {
11000 reg.to64()11131 reg.to64()
11001 else11132 else
11002 unreachable,11133 unreachable,
11003 .segment, .x87, .mmx => unreachable,11134 .segment => if (size_bytes <= 2)
11135 reg
11136 else
11137 unreachable,
11138 .x87 => unreachable,
11139 .mmx => if (size_bytes <= 8)
11140 reg
11141 else
11142 unreachable,
11004 .sse => if (size_bytes <= 16)11143 .sse => if (size_bytes <= 16)
11005 reg.to128()11144 reg.to128()
11006 else if (size_bytes <= 32)11145 else if (size_bytes <= 32)
src/arch/x86_64/Encoding.zig+15-3
...@@ -261,7 +261,8 @@ pub const Mnemonic = enum {...@@ -261,7 +261,8 @@ pub const Mnemonic = enum {
261 // X87261 // X87
262 fisttp, fld,262 fisttp, fld,
263 // MMX263 // MMX
264 movd,264 movd, movq,
265 pand, pandn, por, pxor,
265 // SSE266 // SSE
266 addps, addss,267 addps, addss,
267 andps,268 andps,
...@@ -293,7 +294,8 @@ pub const Mnemonic = enum {...@@ -293,7 +294,8 @@ pub const Mnemonic = enum {
293 maxpd, maxsd,294 maxpd, maxsd,
294 minpd, minsd,295 minpd, minsd,
295 movapd,296 movapd,
296 movq, //movd, movsd,297 movdqa, movdqu,
298 //movsd,
297 movupd,299 movupd,
298 mulpd, mulsd,300 mulpd, mulsd,
299 orpd,301 orpd,
...@@ -316,6 +318,7 @@ pub const Mnemonic = enum {...@@ -316,6 +318,7 @@ pub const Mnemonic = enum {
316 roundpd, roundps, roundsd, roundss,318 roundpd, roundps, roundsd, roundss,
317 // AVX319 // AVX
318 vaddpd, vaddps, vaddsd, vaddss,320 vaddpd, vaddps, vaddsd, vaddss,
321 vandnpd, vandnps, vandpd, vandps,
319 vbroadcastf128, vbroadcastsd, vbroadcastss,322 vbroadcastf128, vbroadcastsd, vbroadcastss,
320 vcvtdq2pd, vcvtdq2ps, vcvtpd2dq, vcvtpd2ps,323 vcvtdq2pd, vcvtdq2ps, vcvtpd2dq, vcvtpd2ps,
321 vcvtps2dq, vcvtps2pd, vcvtsd2si, vcvtsd2ss,324 vcvtps2dq, vcvtps2pd, vcvtsd2si, vcvtsd2ss,
...@@ -327,22 +330,31 @@ pub const Mnemonic = enum {...@@ -327,22 +330,31 @@ pub const Mnemonic = enum {
327 vmaxpd, vmaxps, vmaxsd, vmaxss,330 vmaxpd, vmaxps, vmaxsd, vmaxss,
328 vminpd, vminps, vminsd, vminss,331 vminpd, vminps, vminsd, vminss,
329 vmovapd, vmovaps,332 vmovapd, vmovaps,
330 vmovddup, vmovhlps, vmovlhps,333 vmovd,
334 vmovddup,
335 vmovdqa, vmovdqu,
336 vmovhlps, vmovlhps,
337 vmovq,
331 vmovsd,338 vmovsd,
332 vmovshdup, vmovsldup,339 vmovshdup, vmovsldup,
333 vmovss,340 vmovss,
334 vmovupd, vmovups,341 vmovupd, vmovups,
335 vmulpd, vmulps, vmulsd, vmulss,342 vmulpd, vmulps, vmulsd, vmulss,
343 vorpd, vorps,
344 vpand, vpandn,
336 vpextrb, vpextrd, vpextrq, vpextrw,345 vpextrb, vpextrd, vpextrq, vpextrw,
337 vpinsrb, vpinsrd, vpinsrq, vpinsrw,346 vpinsrb, vpinsrd, vpinsrq, vpinsrw,
347 vpor,
338 vpshufhw, vpshuflw,348 vpshufhw, vpshuflw,
339 vpsrld, vpsrlq, vpsrlw,349 vpsrld, vpsrlq, vpsrlw,
340 vpunpckhbw, vpunpckhdq, vpunpckhqdq, vpunpckhwd,350 vpunpckhbw, vpunpckhdq, vpunpckhqdq, vpunpckhwd,
341 vpunpcklbw, vpunpckldq, vpunpcklqdq, vpunpcklwd,351 vpunpcklbw, vpunpckldq, vpunpcklqdq, vpunpcklwd,
352 vpxor,
342 vroundpd, vroundps, vroundsd, vroundss,353 vroundpd, vroundps, vroundsd, vroundss,
343 vshufpd, vshufps,354 vshufpd, vshufps,
344 vsqrtpd, vsqrtps, vsqrtsd, vsqrtss,355 vsqrtpd, vsqrtps, vsqrtsd, vsqrtss,
345 vsubpd, vsubps, vsubsd, vsubss,356 vsubpd, vsubps, vsubsd, vsubss,
357 vxorpd, vxorps,
346 // F16C358 // F16C
347 vcvtph2ps, vcvtps2ph,359 vcvtph2ps, vcvtps2ph,
348 // FMA360 // FMA
src/arch/x86_64/Mir.zig+12
...@@ -236,6 +236,14 @@ pub const Inst = struct {...@@ -236,6 +236,14 @@ pub const Inst = struct {
236236
237 /// VEX-Encoded ___237 /// VEX-Encoded ___
238 v_,238 v_,
239 /// VEX-Encoded ___ Byte
240 v_b,
241 /// VEX-Encoded ___ Word
242 v_w,
243 /// VEX-Encoded ___ Doubleword
244 v_d,
245 /// VEX-Encoded ___ QuadWord
246 v_q,
239 /// VEX-Encoded Packed ___247 /// VEX-Encoded Packed ___
240 vp_,248 vp_,
241 /// VEX-Encoded Packed ___ Byte249 /// VEX-Encoded Packed ___ Byte
...@@ -526,6 +534,10 @@ pub const Inst = struct {...@@ -526,6 +534,10 @@ pub const Inst = struct {
526 cvttps2dq,534 cvttps2dq,
527 /// Convert with truncation scalar double-precision floating-point value to doubleword integer535 /// Convert with truncation scalar double-precision floating-point value to doubleword integer
528 cvttsd2si,536 cvttsd2si,
537 /// Move aligned packed integer values
538 movdqa,
539 /// Move unaligned packed integer values
540 movdqu,
529 /// Packed interleave shuffle of quadruplets of single-precision floating-point values541 /// Packed interleave shuffle of quadruplets of single-precision floating-point values
530 /// Packed interleave shuffle of pairs of double-precision floating-point values542 /// Packed interleave shuffle of pairs of double-precision floating-point values
531 shuf,543 shuf,
src/arch/x86_64/encodings.zig+73-2
...@@ -970,11 +970,16 @@ pub const table = [_]Entry{...@@ -970,11 +970,16 @@ pub const table = [_]Entry{
970 .{ .movapd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x29 }, 0, .none, .sse2 },970 .{ .movapd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x29 }, 0, .none, .sse2 },
971971
972 .{ .movd, .rm, &.{ .xmm, .rm32 }, &.{ 0x66, 0x0f, 0x6e }, 0, .none, .sse2 },972 .{ .movd, .rm, &.{ .xmm, .rm32 }, &.{ 0x66, 0x0f, 0x6e }, 0, .none, .sse2 },
973 .{ .movd, .mr, &.{ .rm32, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .none, .sse2 },
974
975 .{ .movq, .rm, &.{ .xmm, .rm64 }, &.{ 0x66, 0x0f, 0x6e }, 0, .long, .sse2 },973 .{ .movq, .rm, &.{ .xmm, .rm64 }, &.{ 0x66, 0x0f, 0x6e }, 0, .long, .sse2 },
974 .{ .movd, .mr, &.{ .rm32, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .none, .sse2 },
976 .{ .movq, .mr, &.{ .rm64, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .long, .sse2 },975 .{ .movq, .mr, &.{ .rm64, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .long, .sse2 },
977976
977 .{ .movdqa, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6f }, 0, .none, .sse2 },
978 .{ .movdqa, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x7f }, 0, .none, .sse2 },
979
980 .{ .movdqu, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x6f }, 0, .none, .sse2 },
981 .{ .movdqu, .mr, &.{ .xmm_m128, .xmm }, &.{ 0xf3, 0x0f, 0x7f }, 0, .none, .sse2 },
982
978 .{ .movq, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf3, 0x0f, 0x7e }, 0, .none, .sse2 },983 .{ .movq, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf3, 0x0f, 0x7e }, 0, .none, .sse2 },
979 .{ .movq, .mr, &.{ .xmm_m64, .xmm }, &.{ 0x66, 0x0f, 0xd6 }, 0, .none, .sse2 },984 .{ .movq, .mr, &.{ .xmm_m64, .xmm }, &.{ 0x66, 0x0f, 0xd6 }, 0, .none, .sse2 },
980985
...@@ -987,10 +992,16 @@ pub const table = [_]Entry{...@@ -987,10 +992,16 @@ pub const table = [_]Entry{
987992
988 .{ .orpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x56 }, 0, .none, .sse2 },993 .{ .orpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x56 }, 0, .none, .sse2 },
989994
995 .{ .pand, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xdb }, 0, .none, .sse2 },
996
997 .{ .pandn, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xdf }, 0, .none, .sse2 },
998
990 .{ .pextrw, .rmi, &.{ .r32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0xc5 }, 0, .none, .sse2 },999 .{ .pextrw, .rmi, &.{ .r32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0xc5 }, 0, .none, .sse2 },
9911000
992 .{ .pinsrw, .rmi, &.{ .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .none, .sse2 },1001 .{ .pinsrw, .rmi, &.{ .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .none, .sse2 },
9931002
1003 .{ .por, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xeb }, 0, .none, .sse2 },
1004
994 .{ .pshufhw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf3, 0x0f, 0x70 }, 0, .none, .sse2 },1005 .{ .pshufhw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf3, 0x0f, 0x70 }, 0, .none, .sse2 },
9951006
996 .{ .pshuflw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf2, 0x0f, 0x70 }, 0, .none, .sse2 },1007 .{ .pshuflw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf2, 0x0f, 0x70 }, 0, .none, .sse2 },
...@@ -1012,6 +1023,8 @@ pub const table = [_]Entry{...@@ -1012,6 +1023,8 @@ pub const table = [_]Entry{
1012 .{ .punpckldq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .none, .sse2 },1023 .{ .punpckldq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .none, .sse2 },
1013 .{ .punpcklqdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .none, .sse2 },1024 .{ .punpcklqdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .none, .sse2 },
10141025
1026 .{ .pxor, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xef }, 0, .none, .sse2 },
1027
1015 .{ .shufpd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0xc6 }, 0, .none, .sse2 },1028 .{ .shufpd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0xc6 }, 0, .none, .sse2 },
10161029
1017 .{ .sqrtpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x51 }, 0, .none, .sse2 },1030 .{ .sqrtpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x51 }, 0, .none, .sse2 },
...@@ -1070,6 +1083,18 @@ pub const table = [_]Entry{...@@ -1070,6 +1083,18 @@ pub const table = [_]Entry{
10701083
1071 .{ .vaddss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x58 }, 0, .vex_lig_wig, .avx },1084 .{ .vaddss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x58 }, 0, .vex_lig_wig, .avx },
10721085
1086 .{ .vandnpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x55 }, 0, .vex_128_wig, .avx },
1087 .{ .vandnpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x55 }, 0, .vex_256_wig, .avx },
1088
1089 .{ .vandnps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x0f, 0x55 }, 0, .vex_128_wig, .avx },
1090 .{ .vandnps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x0f, 0x55 }, 0, .vex_256_wig, .avx },
1091
1092 .{ .vandpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x54 }, 0, .vex_128_wig, .avx },
1093 .{ .vandpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x54 }, 0, .vex_256_wig, .avx },
1094
1095 .{ .vandps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x0f, 0x54 }, 0, .vex_128_wig, .avx },
1096 .{ .vandps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x0f, 0x54 }, 0, .vex_256_wig, .avx },
1097
1073 .{ .vbroadcastss, .rm, &.{ .xmm, .m32 }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_128_w0, .avx },1098 .{ .vbroadcastss, .rm, &.{ .xmm, .m32 }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_128_w0, .avx },
1074 .{ .vbroadcastss, .rm, &.{ .ymm, .m32 }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_256_w0, .avx },1099 .{ .vbroadcastss, .rm, &.{ .ymm, .m32 }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_256_w0, .avx },
1075 .{ .vbroadcastsd, .rm, &.{ .ymm, .m64 }, &.{ 0x66, 0x0f, 0x38, 0x19 }, 0, .vex_256_w0, .avx },1100 .{ .vbroadcastsd, .rm, &.{ .ymm, .m64 }, &.{ 0x66, 0x0f, 0x38, 0x19 }, 0, .vex_256_w0, .avx },
...@@ -1169,13 +1194,31 @@ pub const table = [_]Entry{...@@ -1169,13 +1194,31 @@ pub const table = [_]Entry{
1169 .{ .vmovaps, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x28 }, 0, .vex_256_wig, .avx },1194 .{ .vmovaps, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x28 }, 0, .vex_256_wig, .avx },
1170 .{ .vmovaps, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x29 }, 0, .vex_256_wig, .avx },1195 .{ .vmovaps, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x29 }, 0, .vex_256_wig, .avx },
11711196
1197 .{ .vmovd, .rm, &.{ .xmm, .rm32 }, &.{ 0x66, 0x0f, 0x6e }, 0, .vex_128_w0, .avx },
1198 .{ .vmovq, .rm, &.{ .xmm, .rm64 }, &.{ 0x66, 0x0f, 0x6e }, 0, .vex_128_w1, .avx },
1199 .{ .vmovd, .mr, &.{ .rm32, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .vex_128_w0, .avx },
1200 .{ .vmovq, .mr, &.{ .rm64, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .vex_128_w1, .avx },
1201
1172 .{ .vmovddup, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_128_wig, .avx },1202 .{ .vmovddup, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_128_wig, .avx },
1173 .{ .vmovddup, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_256_wig, .avx },1203 .{ .vmovddup, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_256_wig, .avx },
11741204
1205 .{ .vmovdqa, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6f }, 0, .vex_128_wig, .avx },
1206 .{ .vmovdqa, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x7f }, 0, .vex_128_wig, .avx },
1207 .{ .vmovdqa, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x6f }, 0, .vex_256_wig, .avx },
1208 .{ .vmovdqa, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x7f }, 0, .vex_256_wig, .avx },
1209
1210 .{ .vmovdqu, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x6f }, 0, .vex_128_wig, .avx },
1211 .{ .vmovdqu, .mr, &.{ .xmm_m128, .xmm }, &.{ 0xf3, 0x0f, 0x7f }, 0, .vex_128_wig, .avx },
1212 .{ .vmovdqu, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0xf3, 0x0f, 0x6f }, 0, .vex_256_wig, .avx },
1213 .{ .vmovdqu, .mr, &.{ .ymm_m256, .ymm }, &.{ 0xf3, 0x0f, 0x7f }, 0, .vex_256_wig, .avx },
1214
1175 .{ .vmovhlps, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0x0f, 0x12 }, 0, .vex_128_wig, .avx },1215 .{ .vmovhlps, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0x0f, 0x12 }, 0, .vex_128_wig, .avx },
11761216
1177 .{ .vmovlhps, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0x0f, 0x16 }, 0, .vex_128_wig, .avx },1217 .{ .vmovlhps, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0x0f, 0x16 }, 0, .vex_128_wig, .avx },
11781218
1219 .{ .vmovq, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf3, 0x0f, 0x7e }, 0, .vex_128_wig, .avx },
1220 .{ .vmovq, .mr, &.{ .xmm_m64, .xmm }, &.{ 0x66, 0x0f, 0xd6 }, 0, .vex_128_wig, .avx },
1221
1179 .{ .vmovsd, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },1222 .{ .vmovsd, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
1180 .{ .vmovsd, .rm, &.{ .xmm, .m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },1223 .{ .vmovsd, .rm, &.{ .xmm, .m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
1181 .{ .vmovsd, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_lig_wig, .avx },1224 .{ .vmovsd, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_lig_wig, .avx },
...@@ -1212,6 +1255,16 @@ pub const table = [_]Entry{...@@ -1212,6 +1255,16 @@ pub const table = [_]Entry{
12121255
1213 .{ .vmulss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x59 }, 0, .vex_lig_wig, .avx },1256 .{ .vmulss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x59 }, 0, .vex_lig_wig, .avx },
12141257
1258 .{ .vorpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x56 }, 0, .vex_128_wig, .avx },
1259 .{ .vorpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x56 }, 0, .vex_256_wig, .avx },
1260
1261 .{ .vorps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x0f, 0x56 }, 0, .vex_128_wig, .avx },
1262 .{ .vorps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x0f, 0x56 }, 0, .vex_256_wig, .avx },
1263
1264 .{ .vpand, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xdb }, 0, .vex_128_wig, .avx },
1265
1266 .{ .vpandn, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xdf }, 0, .vex_128_wig, .avx },
1267
1215 .{ .vpextrb, .mri, &.{ .r32_m8, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x14 }, 0, .vex_128_w0, .avx },1268 .{ .vpextrb, .mri, &.{ .r32_m8, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x14 }, 0, .vex_128_w0, .avx },
1216 .{ .vpextrd, .mri, &.{ .rm32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x16 }, 0, .vex_128_w0, .avx },1269 .{ .vpextrd, .mri, &.{ .rm32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x16 }, 0, .vex_128_w0, .avx },
1217 .{ .vpextrq, .mri, &.{ .rm64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x16 }, 0, .vex_128_w1, .avx },1270 .{ .vpextrq, .mri, &.{ .rm64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x16 }, 0, .vex_128_w1, .avx },
...@@ -1225,6 +1278,8 @@ pub const table = [_]Entry{...@@ -1225,6 +1278,8 @@ pub const table = [_]Entry{
12251278
1226 .{ .vpinsrw, .rvmi, &.{ .xmm, .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .vex_128_wig, .avx },1279 .{ .vpinsrw, .rvmi, &.{ .xmm, .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .vex_128_wig, .avx },
12271280
1281 .{ .vpor, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xeb }, 0, .vex_128_wig, .avx },
1282
1228 .{ .vpsrlw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_128_wig, .avx },1283 .{ .vpsrlw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_128_wig, .avx },
1229 .{ .vpsrlw, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_128_wig, .avx },1284 .{ .vpsrlw, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_128_wig, .avx },
1230 .{ .vpsrld, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_128_wig, .avx },1285 .{ .vpsrld, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_128_wig, .avx },
...@@ -1242,6 +1297,8 @@ pub const table = [_]Entry{...@@ -1242,6 +1297,8 @@ pub const table = [_]Entry{
1242 .{ .vpunpckldq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .vex_128_wig, .avx },1297 .{ .vpunpckldq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .vex_128_wig, .avx },
1243 .{ .vpunpcklqdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .vex_128_wig, .avx },1298 .{ .vpunpcklqdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .vex_128_wig, .avx },
12441299
1300 .{ .vpxor, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xef }, 0, .vex_128_wig, .avx },
1301
1245 .{ .vroundpd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x09 }, 0, .vex_128_wig, .avx },1302 .{ .vroundpd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x09 }, 0, .vex_128_wig, .avx },
1246 .{ .vroundpd, .rmi, &.{ .ymm, .ymm_m256, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x09 }, 0, .vex_256_wig, .avx },1303 .{ .vroundpd, .rmi, &.{ .ymm, .ymm_m256, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x09 }, 0, .vex_256_wig, .avx },
12471304
...@@ -1278,6 +1335,12 @@ pub const table = [_]Entry{...@@ -1278,6 +1335,12 @@ pub const table = [_]Entry{
12781335
1279 .{ .vsubss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5c }, 0, .vex_lig_wig, .avx },1336 .{ .vsubss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5c }, 0, .vex_lig_wig, .avx },
12801337
1338 .{ .vxorpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x57 }, 0, .vex_128_wig, .avx },
1339 .{ .vxorpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x57 }, 0, .vex_256_wig, .avx },
1340
1341 .{ .vxorps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x0f, 0x57 }, 0, .vex_128_wig, .avx },
1342 .{ .vxorps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x0f, 0x57 }, 0, .vex_256_wig, .avx },
1343
1281 // F16C1344 // F16C
1282 .{ .vcvtph2ps, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_128_w0, .f16c },1345 .{ .vcvtph2ps, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_128_w0, .f16c },
1283 .{ .vcvtph2ps, .rm, &.{ .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_256_w0, .f16c },1346 .{ .vcvtph2ps, .rm, &.{ .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_256_w0, .f16c },
...@@ -1313,6 +1376,12 @@ pub const table = [_]Entry{...@@ -1313,6 +1376,12 @@ pub const table = [_]Entry{
1313 .{ .vbroadcastss, .rm, &.{ .ymm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_256_w0, .avx2 },1376 .{ .vbroadcastss, .rm, &.{ .ymm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_256_w0, .avx2 },
1314 .{ .vbroadcastsd, .rm, &.{ .ymm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x19 }, 0, .vex_256_w0, .avx2 },1377 .{ .vbroadcastsd, .rm, &.{ .ymm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x19 }, 0, .vex_256_w0, .avx2 },
13151378
1379 .{ .vpand, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xdb }, 0, .vex_256_wig, .avx2 },
1380
1381 .{ .vpandn, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xdf }, 0, .vex_256_wig, .avx2 },
1382
1383 .{ .vpor, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xeb }, 0, .vex_256_wig, .avx2 },
1384
1316 .{ .vpsrlw, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_256_wig, .avx2 },1385 .{ .vpsrlw, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_256_wig, .avx2 },
1317 .{ .vpsrlw, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_256_wig, .avx2 },1386 .{ .vpsrlw, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_256_wig, .avx2 },
1318 .{ .vpsrld, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_256_wig, .avx2 },1387 .{ .vpsrld, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_256_wig, .avx2 },
...@@ -1329,5 +1398,7 @@ pub const table = [_]Entry{...@@ -1329,5 +1398,7 @@ pub const table = [_]Entry{
1329 .{ .vpunpcklwd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x61 }, 0, .vex_256_wig, .avx2 },1398 .{ .vpunpcklwd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x61 }, 0, .vex_256_wig, .avx2 },
1330 .{ .vpunpckldq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x62 }, 0, .vex_256_wig, .avx2 },1399 .{ .vpunpckldq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x62 }, 0, .vex_256_wig, .avx2 },
1331 .{ .vpunpcklqdq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x6c }, 0, .vex_256_wig, .avx2 },1400 .{ .vpunpcklqdq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x6c }, 0, .vex_256_wig, .avx2 },
1401
1402 .{ .vpxor, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xef }, 0, .vex_256_wig, .avx2 },
1332};1403};
1333// zig fmt: on1404// zig fmt: on
src/type.zig+11-1
...@@ -5433,8 +5433,18 @@ pub const Type = extern union {...@@ -5433,8 +5433,18 @@ pub const Type = extern union {
5433 }5433 }
5434 }5434 }
54355435
5436 // Works for vectors and vectors of integers.
5437 pub fn maxInt(ty: Type, arena: Allocator, target: Target) !Value {
5438 const scalar = try maxIntScalar(ty.scalarType(), arena, target);
5439 if (ty.zigTypeTag() == .Vector and scalar.tag() != .the_only_possible_value) {
5440 return Value.Tag.repeated.create(arena, scalar);
5441 } else {
5442 return scalar;
5443 }
5444 }
5445
5436 /// Asserts that self.zigTypeTag() == .Int.5446 /// Asserts that self.zigTypeTag() == .Int.
5437 pub fn maxInt(self: Type, arena: Allocator, target: Target) !Value {5447 pub fn maxIntScalar(self: Type, arena: Allocator, target: Target) !Value {
5438 assert(self.zigTypeTag() == .Int);5448 assert(self.zigTypeTag() == .Int);
5439 const info = self.intInfo(target);5449 const info = self.intInfo(target);
54405450
test/behavior/floatop.zig-1
...@@ -532,7 +532,6 @@ fn testFabs() !void {...@@ -532,7 +532,6 @@ fn testFabs() !void {
532532
533test "@fabs with vectors" {533test "@fabs with vectors" {
534 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO534 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
535 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
536 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO535 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
537 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO536 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
538 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;537 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
test/behavior/math.zig-1
...@@ -1612,7 +1612,6 @@ test "absFloat" {...@@ -1612,7 +1612,6 @@ test "absFloat" {
1612 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO1612 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
1613 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO1613 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1614 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO1614 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1615 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
1616 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO1615 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1617 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;1616 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
16181617
test/behavior/translate_c_macros.zig-1
...@@ -65,7 +65,6 @@ test "cast negative integer to pointer" {...@@ -65,7 +65,6 @@ test "cast negative integer to pointer" {
6565
66test "casting to union with a macro" {66test "casting to union with a macro" {
67 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO67 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
68 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
69 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO68 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
70 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO69 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
71 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO70 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO