authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-14 05:12:46-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-15 03:07:51-04:00
log6c6d8d67cfe14c50684c04a579c1e62bf287e8cb
tree22be2a1952c3077a0c60c66fb4b2f47684c5bf43
parentb6d61028508c5b1e1961a124bc17d4d9bda9686f

x86_64: redo movement, float negation, and `@fabs`

8 files changed, 359 insertions(+), 118 deletions(-)

src/arch/x86_64/CodeGen.zig+248-109
......@@ -4681,61 +4681,136 @@ fn airBitReverse(self: *Self, inst: Air.Inst.Index) !void {
46814681}
46824682
46834683fn airFloatSign(self: *Self, inst: Air.Inst.Index) !void {
4684 const tag = self.air.instructions.items(.tag)[inst];
46844685 const un_op = self.air.instructions.items(.data)[inst].un_op;
46854686 const ty = self.air.typeOf(un_op);
4686 const ty_bits = ty.floatBits(self.target.*);
4687 const abi_size: u32 = switch (ty.abiSize(self.target.*)) {
4688 1...16 => 16,
4689 17...32 => 32,
4690 else => return self.fail("TODO implement airFloatSign for {}", .{
4691 ty.fmt(self.bin_file.options.module.?),
4692 }),
4693 };
4694 const scalar_bits = ty.scalarType().floatBits(self.target.*);
4695
4696 const src_mcv = try self.resolveInst(un_op);
4697 const src_lock = if (src_mcv.getReg()) |reg| self.register_manager.lockReg(reg) else null;
4698 defer if (src_lock) |lock| self.register_manager.unlockReg(lock);
4699
4700 const dst_mcv: MCValue = if (src_mcv.isRegister() and self.reuseOperand(inst, un_op, 0, src_mcv))
4701 src_mcv
4702 else if (self.hasFeature(.avx))
4703 .{ .register = try self.register_manager.allocReg(inst, sse) }
4704 else
4705 try self.copyToRegisterWithInstTracking(inst, ty, src_mcv);
4706 const dst_reg = dst_mcv.getReg().?;
4707 const dst_lock = self.register_manager.lockReg(dst_reg);
4708 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
46874709
46884710 var arena = std.heap.ArenaAllocator.init(self.gpa);
46894711 defer arena.deinit();
46904712
4691 const ExpectedContents = union {
4692 f16: Value.Payload.Float_16,
4693 f32: Value.Payload.Float_32,
4694 f64: Value.Payload.Float_64,
4695 f80: Value.Payload.Float_80,
4696 f128: Value.Payload.Float_128,
4713 const ExpectedContents = struct {
4714 scalar: union {
4715 i64: Value.Payload.I64,
4716 big: struct {
4717 limbs: [
4718 @max(
4719 std.math.big.int.Managed.default_capacity,
4720 std.math.big.int.calcTwosCompLimbCount(128),
4721 )
4722 ]std.math.big.Limb,
4723 pl: Value.Payload.BigInt,
4724 },
4725 },
4726 repeated: Value.Payload.SubValue,
46974727 };
46984728 var stack align(@alignOf(ExpectedContents)) =
46994729 std.heap.stackFallback(@sizeOf(ExpectedContents), arena.allocator());
47004730
4731 var int_pl = Type.Payload.Bits{
4732 .base = .{ .tag = .int_signed },
4733 .data = scalar_bits,
4734 };
47014735 var vec_pl = Type.Payload.Array{
47024736 .base = .{ .tag = .vector },
47034737 .data = .{
4704 .len = @divExact(128, ty_bits),
4705 .elem_type = ty,
4738 .len = @divExact(abi_size * 8, scalar_bits),
4739 .elem_type = Type.initPayload(&int_pl.base),
47064740 },
47074741 };
47084742 const vec_ty = Type.initPayload(&vec_pl.base);
4709
4710 var sign_pl = Value.Payload.SubValue{
4711 .base = .{ .tag = .repeated },
4712 .data = try Value.floatToValue(-0.0, stack.get(), ty, self.target.*),
4743 const sign_val = switch (tag) {
4744 .neg => try vec_ty.minInt(stack.get(), self.target.*),
4745 .fabs => try vec_ty.maxInt(stack.get(), self.target.*),
4746 else => unreachable,
47134747 };
4714 const sign_val = Value.initPayload(&sign_pl.base);
47154748
47164749 const sign_mcv = try self.genTypedValue(.{ .ty = vec_ty, .val = sign_val });
4717
4718 const src_mcv = try self.resolveInst(un_op);
4719 const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, un_op, 0, src_mcv))
4720 src_mcv
4750 const sign_mem = if (sign_mcv.isMemory())
4751 sign_mcv.mem(Memory.PtrSize.fromSize(abi_size))
47214752 else
4722 try self.copyToRegisterWithInstTracking(inst, ty, src_mcv);
4723 const dst_lock = self.register_manager.lockReg(dst_mcv.register);
4724 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
4753 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
4754 .base = .{ .reg = try self.copyToTmpRegister(Type.usize, sign_mcv.address()) },
4755 });
47254756
4726 const tag = self.air.instructions.items(.tag)[inst];
4727 try self.genBinOpMir(switch (ty_bits) {
4728 // No point using an extra prefix byte for *pd which performs the same operation.
4729 16, 32, 64, 128 => switch (tag) {
4730 .neg => .{ ._ps, .xor },
4731 .fabs => .{ ._ps, .andn },
4757 if (self.hasFeature(.avx)) try self.asmRegisterRegisterMemory(
4758 switch (scalar_bits) {
4759 16, 128 => if (abi_size <= 16 or self.hasFeature(.avx2)) switch (tag) {
4760 .neg => .{ .vp_, .xor },
4761 .fabs => .{ .vp_, .@"and" },
4762 else => unreachable,
4763 } else switch (tag) {
4764 .neg => .{ .v_ps, .xor },
4765 .fabs => .{ .v_ps, .@"and" },
4766 else => unreachable,
4767 },
4768 32 => switch (tag) {
4769 .neg => .{ .v_ps, .xor },
4770 .fabs => .{ .v_ps, .@"and" },
4771 else => unreachable,
4772 },
4773 64 => switch (tag) {
4774 .neg => .{ .v_pd, .xor },
4775 .fabs => .{ .v_pd, .@"and" },
4776 else => unreachable,
4777 },
4778 80 => return self.fail("TODO implement airFloatSign for {}", .{
4779 ty.fmt(self.bin_file.options.module.?),
4780 }),
47324781 else => unreachable,
47334782 },
4734 80 => return self.fail("TODO implement airFloatSign for {}", .{
4735 ty.fmt(self.bin_file.options.module.?),
4736 }),
4737 else => unreachable,
4738 }, vec_ty, dst_mcv, sign_mcv);
4783 registerAlias(dst_reg, abi_size),
4784 registerAlias(if (src_mcv.isRegister())
4785 src_mcv.getReg().?
4786 else
4787 try self.copyToTmpRegister(ty, src_mcv), abi_size),
4788 sign_mem,
4789 ) else try self.asmRegisterMemory(
4790 switch (scalar_bits) {
4791 16, 128 => switch (tag) {
4792 .neg => .{ .p_, .xor },
4793 .fabs => .{ .p_, .@"and" },
4794 else => unreachable,
4795 },
4796 32 => switch (tag) {
4797 .neg => .{ ._ps, .xor },
4798 .fabs => .{ ._ps, .@"and" },
4799 else => unreachable,
4800 },
4801 64 => switch (tag) {
4802 .neg => .{ ._pd, .xor },
4803 .fabs => .{ ._pd, .@"and" },
4804 else => unreachable,
4805 },
4806 80 => return self.fail("TODO implement airFloatSign for {}", .{
4807 ty.fmt(self.bin_file.options.module.?),
4808 }),
4809 else => unreachable,
4810 },
4811 registerAlias(dst_reg, abi_size),
4812 sign_mem,
4813 );
47394814 return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none });
47404815}
47414816
......@@ -8593,7 +8668,6 @@ const MoveStrategy = union(enum) {
85938668 const InsertExtract = struct {
85948669 insert: Mir.Inst.FixedTag,
85958670 extract: Mir.Inst.FixedTag,
8596 imm: Immediate,
85978671 };
85988672};
85998673fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {
......@@ -8603,17 +8677,15 @@ fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {
86038677 16 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{
86048678 .insert = .{ .vp_w, .insr },
86058679 .extract = .{ .vp_w, .extr },
8606 .imm = Immediate.u(0),
86078680 } } else .{ .insert_extract = .{
86088681 .insert = .{ .p_w, .insr },
86098682 .extract = .{ .p_w, .extr },
8610 .imm = Immediate.u(0),
86118683 } },
86128684 32 => return .{ .move = if (self.hasFeature(.avx)) .{ .v_ss, .mov } else .{ ._ss, .mov } },
86138685 64 => return .{ .move = if (self.hasFeature(.avx)) .{ .v_sd, .mov } else .{ ._sd, .mov } },
86148686 128 => return .{ .move = if (self.hasFeature(.avx))
8615 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
8616 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
8687 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8688 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
86178689 else => {},
86188690 },
86198691 .Vector => switch (ty.childType().zigTypeTag()) {
......@@ -8622,101 +8694,120 @@ fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {
86228694 1 => if (self.hasFeature(.avx)) return .{ .vex_insert_extract = .{
86238695 .insert = .{ .vp_b, .insr },
86248696 .extract = .{ .vp_b, .extr },
8625 .imm = Immediate.u(0),
86268697 } } else if (self.hasFeature(.sse4_2)) return .{ .insert_extract = .{
86278698 .insert = .{ .p_b, .insr },
86288699 .extract = .{ .p_b, .extr },
8629 .imm = Immediate.u(0),
86308700 } },
86318701 2 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{
86328702 .insert = .{ .vp_w, .insr },
86338703 .extract = .{ .vp_w, .extr },
8634 .imm = Immediate.u(0),
86358704 } } else .{ .insert_extract = .{
86368705 .insert = .{ .p_w, .insr },
86378706 .extract = .{ .p_w, .extr },
8638 .imm = Immediate.u(0),
86398707 } },
86408708 3...4 => return .{ .move = if (self.hasFeature(.avx))
8641 .{ .v_ss, .mov }
8709 .{ .v_d, .mov }
86428710 else
8643 .{ ._ss, .mov } },
8711 .{ ._d, .mov } },
86448712 5...8 => return .{ .move = if (self.hasFeature(.avx))
8645 .{ .v_sd, .mov }
8713 .{ .v_q, .mov }
86468714 else
8647 .{ ._sd, .mov } },
8715 .{ ._q, .mov } },
8716 9...16 => return .{ .move = if (self.hasFeature(.avx))
8717 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8718 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
8719 17...32 => if (self.hasFeature(.avx))
8720 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
86488721 else => {},
86498722 },
86508723 16 => switch (ty.vectorLen()) {
86518724 1 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{
86528725 .insert = .{ .vp_w, .insr },
86538726 .extract = .{ .vp_w, .extr },
8654 .imm = Immediate.u(0),
86558727 } } else .{ .insert_extract = .{
86568728 .insert = .{ .p_w, .insr },
86578729 .extract = .{ .p_w, .extr },
8658 .imm = Immediate.u(0),
86598730 } },
86608731 2 => return .{ .move = if (self.hasFeature(.avx))
8661 .{ .v_ss, .mov }
8732 .{ .v_d, .mov }
86628733 else
8663 .{ ._ss, .mov } },
8734 .{ ._d, .mov } },
86648735 3...4 => return .{ .move = if (self.hasFeature(.avx))
8665 .{ .v_sd, .mov }
8736 .{ .v_q, .mov }
86668737 else
8667 .{ ._sd, .mov } },
8738 .{ ._q, .mov } },
86688739 5...8 => return .{ .move = if (self.hasFeature(.avx))
8669 .{ .v_ps, .mov }
8670 else
8671 .{ ._ps, .mov } },
8740 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8741 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
8742 9...16 => if (self.hasFeature(.avx))
8743 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
86728744 else => {},
86738745 },
86748746 32 => switch (ty.vectorLen()) {
86758747 1 => return .{ .move = if (self.hasFeature(.avx))
8676 .{ .v_ss, .mov }
8748 .{ .v_d, .mov }
86778749 else
8678 .{ ._ss, .mov } },
8750 .{ ._d, .mov } },
86798751 2 => return .{ .move = if (self.hasFeature(.avx))
8680 .{ .v_sd, .mov }
8752 .{ .v_q, .mov }
86818753 else
8682 .{ ._sd, .mov } },
8754 .{ ._q, .mov } },
86838755 3...4 => return .{ .move = if (self.hasFeature(.avx))
8684 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
8685 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
8756 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8757 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
86868758 5...8 => if (self.hasFeature(.avx))
8687 return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },
8759 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
86888760 else => {},
86898761 },
86908762 64 => switch (ty.vectorLen()) {
86918763 1 => return .{ .move = if (self.hasFeature(.avx))
8692 .{ .v_sd, .mov }
8764 .{ .v_q, .mov }
86938765 else
8694 .{ ._sd, .mov } },
8766 .{ ._q, .mov } },
86958767 2 => return .{ .move = if (self.hasFeature(.avx))
8696 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
8697 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
8768 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8769 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
86988770 3...4 => if (self.hasFeature(.avx))
8699 return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },
8771 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
8772 else => {},
8773 },
8774 128 => switch (ty.vectorLen()) {
8775 1 => return .{ .move = if (self.hasFeature(.avx))
8776 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8777 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
8778 2 => if (self.hasFeature(.avx))
8779 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
8780 else => {},
8781 },
8782 256 => switch (ty.vectorLen()) {
8783 1 => if (self.hasFeature(.avx))
8784 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
87008785 else => {},
87018786 },
87028787 else => {},
87038788 },
87048789 .Float => switch (ty.childType().floatBits(self.target.*)) {
87058790 16 => switch (ty.vectorLen()) {
8706 1 => {},
8791 1 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{
8792 .insert = .{ .vp_w, .insr },
8793 .extract = .{ .vp_w, .extr },
8794 } } else .{ .insert_extract = .{
8795 .insert = .{ .p_w, .insr },
8796 .extract = .{ .p_w, .extr },
8797 } },
87078798 2 => return .{ .move = if (self.hasFeature(.avx))
8708 .{ .v_ss, .mov }
8799 .{ .v_d, .mov }
87098800 else
8710 .{ ._ss, .mov } },
8801 .{ ._d, .mov } },
87118802 3...4 => return .{ .move = if (self.hasFeature(.avx))
8712 .{ .v_sd, .mov }
8803 .{ .v_q, .mov }
87138804 else
8714 .{ ._sd, .mov } },
8805 .{ ._q, .mov } },
87158806 5...8 => return .{ .move = if (self.hasFeature(.avx))
8716 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
8717 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
8807 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8808 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
87188809 9...16 => if (self.hasFeature(.avx))
8719 return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },
8810 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
87208811 else => {},
87218812 },
87228813 32 => switch (ty.vectorLen()) {
......@@ -8741,18 +8832,18 @@ fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {
87418832 else
87428833 .{ ._sd, .mov } },
87438834 2 => return .{ .move = if (self.hasFeature(.avx))
8744 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
8745 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
8835 if (aligned) .{ .v_pd, .mova } else .{ .v_pd, .movu }
8836 else if (aligned) .{ ._pd, .mova } else .{ ._pd, .movu } },
87468837 3...4 => if (self.hasFeature(.avx))
8747 return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },
8838 return .{ .move = if (aligned) .{ .v_pd, .mova } else .{ .v_pd, .movu } },
87488839 else => {},
87498840 },
87508841 128 => switch (ty.vectorLen()) {
87518842 1 => return .{ .move = if (self.hasFeature(.avx))
8752 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
8753 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
8843 if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu }
8844 else if (aligned) .{ ._, .movdqa } else .{ ._, .movdqu } },
87548845 2 => if (self.hasFeature(.avx))
8755 return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },
8846 return .{ .move = if (aligned) .{ .v_, .movdqa } else .{ .v_, .movdqu } },
87568847 else => {},
87578848 },
87588849 else => {},
......@@ -8860,29 +8951,69 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
88608951 );
88618952 }
88628953 },
8863 .register => |src_reg| if (dst_reg.id() != src_reg.id()) try self.asmRegisterRegister(
8864 if ((dst_reg.class() == .sse) == (src_reg.class() == .sse))
8865 switch (ty.zigTypeTag()) {
8866 else => .{ ._, .mov },
8867 .Float, .Vector => .{ ._ps, .mova },
8868 }
8869 else switch (abi_size) {
8870 2 => return try self.asmRegisterRegisterImmediate(
8871 if (dst_reg.class() == .sse) .{ .p_w, .insr } else .{ .p_w, .extr },
8872 registerAlias(dst_reg, 4),
8873 registerAlias(src_reg, 4),
8874 Immediate.u(0),
8954 .register => |src_reg| if (dst_reg.id() != src_reg.id()) switch (dst_reg.class()) {
8955 .general_purpose => switch (src_reg.class()) {
8956 .general_purpose => try self.asmRegisterRegister(
8957 .{ ._, .mov },
8958 registerAlias(dst_reg, abi_size),
8959 registerAlias(src_reg, abi_size),
88758960 ),
8876 4 => .{ ._d, .mov },
8877 8 => .{ ._q, .mov },
8878 else => return self.fail(
8879 "unsupported register copy from {s} to {s}",
8880 .{ @tagName(src_reg), @tagName(dst_reg) },
8961 .segment => try self.asmRegisterRegister(
8962 .{ ._, .mov },
8963 registerAlias(dst_reg, abi_size),
8964 src_reg,
88818965 ),
8966 .sse => try self.asmRegisterRegister(
8967 switch (abi_size) {
8968 1...4 => if (self.hasFeature(.avx)) .{ .v_d, .mov } else .{ ._d, .mov },
8969 5...8 => if (self.hasFeature(.avx)) .{ .v_q, .mov } else .{ ._q, .mov },
8970 else => unreachable,
8971 },
8972 registerAlias(dst_reg, @max(abi_size, 4)),
8973 src_reg.to128(),
8974 ),
8975 .x87, .mmx => unreachable,
88828976 },
8883 registerAlias(dst_reg, abi_size),
8884 registerAlias(src_reg, abi_size),
8885 ),
8977 .segment => try self.asmRegisterRegister(
8978 .{ ._, .mov },
8979 dst_reg,
8980 switch (src_reg.class()) {
8981 .general_purpose, .segment => registerAlias(src_reg, abi_size),
8982 .sse => try self.copyToTmpRegister(ty, src_mcv),
8983 .x87, .mmx => unreachable,
8984 },
8985 ),
8986 .sse => switch (src_reg.class()) {
8987 .general_purpose => try self.asmRegisterRegister(
8988 switch (abi_size) {
8989 1...4 => if (self.hasFeature(.avx)) .{ .v_d, .mov } else .{ ._d, .mov },
8990 5...8 => if (self.hasFeature(.avx)) .{ .v_q, .mov } else .{ ._q, .mov },
8991 else => unreachable,
8992 },
8993 dst_reg.to128(),
8994 registerAlias(src_reg, @max(abi_size, 4)),
8995 ),
8996 .segment => try self.genSetReg(
8997 dst_reg,
8998 ty,
8999 .{ .register = try self.copyToTmpRegister(ty, src_mcv) },
9000 ),
9001 .sse => try self.asmRegisterRegister(
9002 switch (ty.scalarType().zigTypeTag()) {
9003 else => if (self.hasFeature(.avx)) .{ .v_, .movdqa } else .{ ._, .movdqa },
9004 .Float => switch (ty.floatBits(self.target.*)) {
9005 else => if (self.hasFeature(.avx)) .{ .v_, .movdqa } else .{ ._, .movdqa },
9006 32 => if (self.hasFeature(.avx)) .{ .v_ps, .mova } else .{ ._ps, .mova },
9007 64 => if (self.hasFeature(.avx)) .{ .v_pd, .mova } else .{ ._pd, .mova },
9008 },
9009 },
9010 registerAlias(dst_reg, abi_size),
9011 registerAlias(src_reg, abi_size),
9012 ),
9013 .x87, .mmx => unreachable,
9014 },
9015 .x87, .mmx => unreachable,
9016 },
88869017 .register_offset,
88879018 .indirect,
88889019 .load_frame,
......@@ -8918,14 +9049,14 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
89189049 ie.insert,
89199050 dst_alias,
89209051 src_mem,
8921 ie.imm,
9052 Immediate.u(0),
89229053 ),
89239054 .vex_insert_extract => |ie| try self.asmRegisterRegisterMemoryImmediate(
89249055 ie.insert,
89259056 dst_alias,
89269057 dst_alias,
89279058 src_mem,
8928 ie.imm,
9059 Immediate.u(0),
89299060 ),
89309061 }
89319062 },
......@@ -8947,14 +9078,14 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
89479078 ie.insert,
89489079 dst_alias,
89499080 src_mem,
8950 ie.imm,
9081 Immediate.u(0),
89519082 ),
89529083 .vex_insert_extract => |ie| try self.asmRegisterRegisterMemoryImmediate(
89539084 ie.insert,
89549085 dst_alias,
89559086 dst_alias,
89569087 src_mem,
8957 ie.imm,
9088 Immediate.u(0),
89589089 ),
89599090 }
89609091 },
......@@ -8994,14 +9125,14 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
89949125 ie.insert,
89959126 dst_alias,
89969127 src_mem,
8997 ie.imm,
9128 Immediate.u(0),
89989129 ),
89999130 .vex_insert_extract => |ie| try self.asmRegisterRegisterMemoryImmediate(
90009131 ie.insert,
90019132 dst_alias,
90029133 dst_alias,
90039134 src_mem,
9004 ie.imm,
9135 Immediate.u(0),
90059136 ),
90069137 }
90079138 },
......@@ -9129,7 +9260,7 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal
91299260 ie.extract,
91309261 dst_mem,
91319262 src_alias,
9132 ie.imm,
9263 Immediate.u(0),
91339264 ),
91349265 }
91359266 },
......@@ -10499,7 +10630,7 @@ fn airUnionInit(self: *Self, inst: Air.Inst.Index) !void {
1049910630 if (self.reuseOperand(inst, extra.init, 0, src_mcv)) break :result src_mcv;
1050010631
1050110632 const dst_mcv = try self.allocRegOrMem(inst, true);
10502 try self.genCopy(src_ty, dst_mcv, src_mcv);
10633 try self.genCopy(union_ty, dst_mcv, src_mcv);
1050310634 break :result dst_mcv;
1050410635 }
1050510636
......@@ -11000,7 +11131,15 @@ fn registerAlias(reg: Register, size_bytes: u32) Register {
1100011131 reg.to64()
1100111132 else
1100211133 unreachable,
11003 .segment, .x87, .mmx => unreachable,
11134 .segment => if (size_bytes <= 2)
11135 reg
11136 else
11137 unreachable,
11138 .x87 => unreachable,
11139 .mmx => if (size_bytes <= 8)
11140 reg
11141 else
11142 unreachable,
1100411143 .sse => if (size_bytes <= 16)
1100511144 reg.to128()
1100611145 else if (size_bytes <= 32)
src/arch/x86_64/Encoding.zig+15-3
......@@ -261,7 +261,8 @@ pub const Mnemonic = enum {
261261 // X87
262262 fisttp, fld,
263263 // MMX
264 movd,
264 movd, movq,
265 pand, pandn, por, pxor,
265266 // SSE
266267 addps, addss,
267268 andps,
......@@ -293,7 +294,8 @@ pub const Mnemonic = enum {
293294 maxpd, maxsd,
294295 minpd, minsd,
295296 movapd,
296 movq, //movd, movsd,
297 movdqa, movdqu,
298 //movsd,
297299 movupd,
298300 mulpd, mulsd,
299301 orpd,
......@@ -316,6 +318,7 @@ pub const Mnemonic = enum {
316318 roundpd, roundps, roundsd, roundss,
317319 // AVX
318320 vaddpd, vaddps, vaddsd, vaddss,
321 vandnpd, vandnps, vandpd, vandps,
319322 vbroadcastf128, vbroadcastsd, vbroadcastss,
320323 vcvtdq2pd, vcvtdq2ps, vcvtpd2dq, vcvtpd2ps,
321324 vcvtps2dq, vcvtps2pd, vcvtsd2si, vcvtsd2ss,
......@@ -327,22 +330,31 @@ pub const Mnemonic = enum {
327330 vmaxpd, vmaxps, vmaxsd, vmaxss,
328331 vminpd, vminps, vminsd, vminss,
329332 vmovapd, vmovaps,
330 vmovddup, vmovhlps, vmovlhps,
333 vmovd,
334 vmovddup,
335 vmovdqa, vmovdqu,
336 vmovhlps, vmovlhps,
337 vmovq,
331338 vmovsd,
332339 vmovshdup, vmovsldup,
333340 vmovss,
334341 vmovupd, vmovups,
335342 vmulpd, vmulps, vmulsd, vmulss,
343 vorpd, vorps,
344 vpand, vpandn,
336345 vpextrb, vpextrd, vpextrq, vpextrw,
337346 vpinsrb, vpinsrd, vpinsrq, vpinsrw,
347 vpor,
338348 vpshufhw, vpshuflw,
339349 vpsrld, vpsrlq, vpsrlw,
340350 vpunpckhbw, vpunpckhdq, vpunpckhqdq, vpunpckhwd,
341351 vpunpcklbw, vpunpckldq, vpunpcklqdq, vpunpcklwd,
352 vpxor,
342353 vroundpd, vroundps, vroundsd, vroundss,
343354 vshufpd, vshufps,
344355 vsqrtpd, vsqrtps, vsqrtsd, vsqrtss,
345356 vsubpd, vsubps, vsubsd, vsubss,
357 vxorpd, vxorps,
346358 // F16C
347359 vcvtph2ps, vcvtps2ph,
348360 // FMA
src/arch/x86_64/Mir.zig+12
......@@ -236,6 +236,14 @@ pub const Inst = struct {
236236
237237 /// VEX-Encoded ___
238238 v_,
239 /// VEX-Encoded ___ Byte
240 v_b,
241 /// VEX-Encoded ___ Word
242 v_w,
243 /// VEX-Encoded ___ Doubleword
244 v_d,
245 /// VEX-Encoded ___ QuadWord
246 v_q,
239247 /// VEX-Encoded Packed ___
240248 vp_,
241249 /// VEX-Encoded Packed ___ Byte
......@@ -526,6 +534,10 @@ pub const Inst = struct {
526534 cvttps2dq,
527535 /// Convert with truncation scalar double-precision floating-point value to doubleword integer
528536 cvttsd2si,
537 /// Move aligned packed integer values
538 movdqa,
539 /// Move unaligned packed integer values
540 movdqu,
529541 /// Packed interleave shuffle of quadruplets of single-precision floating-point values
530542 /// Packed interleave shuffle of pairs of double-precision floating-point values
531543 shuf,
src/arch/x86_64/encodings.zig+73-2
......@@ -970,11 +970,16 @@ pub const table = [_]Entry{
970970 .{ .movapd, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x29 }, 0, .none, .sse2 },
971971
972972 .{ .movd, .rm, &.{ .xmm, .rm32 }, &.{ 0x66, 0x0f, 0x6e }, 0, .none, .sse2 },
973 .{ .movd, .mr, &.{ .rm32, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .none, .sse2 },
974
975973 .{ .movq, .rm, &.{ .xmm, .rm64 }, &.{ 0x66, 0x0f, 0x6e }, 0, .long, .sse2 },
974 .{ .movd, .mr, &.{ .rm32, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .none, .sse2 },
976975 .{ .movq, .mr, &.{ .rm64, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .long, .sse2 },
977976
977 .{ .movdqa, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6f }, 0, .none, .sse2 },
978 .{ .movdqa, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x7f }, 0, .none, .sse2 },
979
980 .{ .movdqu, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x6f }, 0, .none, .sse2 },
981 .{ .movdqu, .mr, &.{ .xmm_m128, .xmm }, &.{ 0xf3, 0x0f, 0x7f }, 0, .none, .sse2 },
982
978983 .{ .movq, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf3, 0x0f, 0x7e }, 0, .none, .sse2 },
979984 .{ .movq, .mr, &.{ .xmm_m64, .xmm }, &.{ 0x66, 0x0f, 0xd6 }, 0, .none, .sse2 },
980985
......@@ -987,10 +992,16 @@ pub const table = [_]Entry{
987992
988993 .{ .orpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x56 }, 0, .none, .sse2 },
989994
995 .{ .pand, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xdb }, 0, .none, .sse2 },
996
997 .{ .pandn, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xdf }, 0, .none, .sse2 },
998
990999 .{ .pextrw, .rmi, &.{ .r32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0xc5 }, 0, .none, .sse2 },
9911000
9921001 .{ .pinsrw, .rmi, &.{ .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .none, .sse2 },
9931002
1003 .{ .por, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xeb }, 0, .none, .sse2 },
1004
9941005 .{ .pshufhw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf3, 0x0f, 0x70 }, 0, .none, .sse2 },
9951006
9961007 .{ .pshuflw, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0xf2, 0x0f, 0x70 }, 0, .none, .sse2 },
......@@ -1012,6 +1023,8 @@ pub const table = [_]Entry{
10121023 .{ .punpckldq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .none, .sse2 },
10131024 .{ .punpcklqdq, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .none, .sse2 },
10141025
1026 .{ .pxor, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xef }, 0, .none, .sse2 },
1027
10151028 .{ .shufpd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0xc6 }, 0, .none, .sse2 },
10161029
10171030 .{ .sqrtpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x51 }, 0, .none, .sse2 },
......@@ -1070,6 +1083,18 @@ pub const table = [_]Entry{
10701083
10711084 .{ .vaddss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x58 }, 0, .vex_lig_wig, .avx },
10721085
1086 .{ .vandnpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x55 }, 0, .vex_128_wig, .avx },
1087 .{ .vandnpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x55 }, 0, .vex_256_wig, .avx },
1088
1089 .{ .vandnps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x0f, 0x55 }, 0, .vex_128_wig, .avx },
1090 .{ .vandnps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x0f, 0x55 }, 0, .vex_256_wig, .avx },
1091
1092 .{ .vandpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x54 }, 0, .vex_128_wig, .avx },
1093 .{ .vandpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x54 }, 0, .vex_256_wig, .avx },
1094
1095 .{ .vandps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x0f, 0x54 }, 0, .vex_128_wig, .avx },
1096 .{ .vandps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x0f, 0x54 }, 0, .vex_256_wig, .avx },
1097
10731098 .{ .vbroadcastss, .rm, &.{ .xmm, .m32 }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_128_w0, .avx },
10741099 .{ .vbroadcastss, .rm, &.{ .ymm, .m32 }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_256_w0, .avx },
10751100 .{ .vbroadcastsd, .rm, &.{ .ymm, .m64 }, &.{ 0x66, 0x0f, 0x38, 0x19 }, 0, .vex_256_w0, .avx },
......@@ -1169,13 +1194,31 @@ pub const table = [_]Entry{
11691194 .{ .vmovaps, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x0f, 0x28 }, 0, .vex_256_wig, .avx },
11701195 .{ .vmovaps, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x0f, 0x29 }, 0, .vex_256_wig, .avx },
11711196
1197 .{ .vmovd, .rm, &.{ .xmm, .rm32 }, &.{ 0x66, 0x0f, 0x6e }, 0, .vex_128_w0, .avx },
1198 .{ .vmovq, .rm, &.{ .xmm, .rm64 }, &.{ 0x66, 0x0f, 0x6e }, 0, .vex_128_w1, .avx },
1199 .{ .vmovd, .mr, &.{ .rm32, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .vex_128_w0, .avx },
1200 .{ .vmovq, .mr, &.{ .rm64, .xmm }, &.{ 0x66, 0x0f, 0x7e }, 0, .vex_128_w1, .avx },
1201
11721202 .{ .vmovddup, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_128_wig, .avx },
11731203 .{ .vmovddup, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0xf2, 0x0f, 0x12 }, 0, .vex_256_wig, .avx },
11741204
1205 .{ .vmovdqa, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6f }, 0, .vex_128_wig, .avx },
1206 .{ .vmovdqa, .mr, &.{ .xmm_m128, .xmm }, &.{ 0x66, 0x0f, 0x7f }, 0, .vex_128_wig, .avx },
1207 .{ .vmovdqa, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x6f }, 0, .vex_256_wig, .avx },
1208 .{ .vmovdqa, .mr, &.{ .ymm_m256, .ymm }, &.{ 0x66, 0x0f, 0x7f }, 0, .vex_256_wig, .avx },
1209
1210 .{ .vmovdqu, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0xf3, 0x0f, 0x6f }, 0, .vex_128_wig, .avx },
1211 .{ .vmovdqu, .mr, &.{ .xmm_m128, .xmm }, &.{ 0xf3, 0x0f, 0x7f }, 0, .vex_128_wig, .avx },
1212 .{ .vmovdqu, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0xf3, 0x0f, 0x6f }, 0, .vex_256_wig, .avx },
1213 .{ .vmovdqu, .mr, &.{ .ymm_m256, .ymm }, &.{ 0xf3, 0x0f, 0x7f }, 0, .vex_256_wig, .avx },
1214
11751215 .{ .vmovhlps, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0x0f, 0x12 }, 0, .vex_128_wig, .avx },
11761216
11771217 .{ .vmovlhps, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0x0f, 0x16 }, 0, .vex_128_wig, .avx },
11781218
1219 .{ .vmovq, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0xf3, 0x0f, 0x7e }, 0, .vex_128_wig, .avx },
1220 .{ .vmovq, .mr, &.{ .xmm_m64, .xmm }, &.{ 0x66, 0x0f, 0xd6 }, 0, .vex_128_wig, .avx },
1221
11791222 .{ .vmovsd, .rvm, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
11801223 .{ .vmovsd, .rm, &.{ .xmm, .m64 }, &.{ 0xf2, 0x0f, 0x10 }, 0, .vex_lig_wig, .avx },
11811224 .{ .vmovsd, .mvr, &.{ .xmm, .xmm, .xmm }, &.{ 0xf2, 0x0f, 0x11 }, 0, .vex_lig_wig, .avx },
......@@ -1212,6 +1255,16 @@ pub const table = [_]Entry{
12121255
12131256 .{ .vmulss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x59 }, 0, .vex_lig_wig, .avx },
12141257
1258 .{ .vorpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x56 }, 0, .vex_128_wig, .avx },
1259 .{ .vorpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x56 }, 0, .vex_256_wig, .avx },
1260
1261 .{ .vorps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x0f, 0x56 }, 0, .vex_128_wig, .avx },
1262 .{ .vorps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x0f, 0x56 }, 0, .vex_256_wig, .avx },
1263
1264 .{ .vpand, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xdb }, 0, .vex_128_wig, .avx },
1265
1266 .{ .vpandn, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xdf }, 0, .vex_128_wig, .avx },
1267
12151268 .{ .vpextrb, .mri, &.{ .r32_m8, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x14 }, 0, .vex_128_w0, .avx },
12161269 .{ .vpextrd, .mri, &.{ .rm32, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x16 }, 0, .vex_128_w0, .avx },
12171270 .{ .vpextrq, .mri, &.{ .rm64, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x16 }, 0, .vex_128_w1, .avx },
......@@ -1225,6 +1278,8 @@ pub const table = [_]Entry{
12251278
12261279 .{ .vpinsrw, .rvmi, &.{ .xmm, .xmm, .r32_m16, .imm8 }, &.{ 0x66, 0x0f, 0xc4 }, 0, .vex_128_wig, .avx },
12271280
1281 .{ .vpor, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xeb }, 0, .vex_128_wig, .avx },
1282
12281283 .{ .vpsrlw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_128_wig, .avx },
12291284 .{ .vpsrlw, .vmi, &.{ .xmm, .xmm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_128_wig, .avx },
12301285 .{ .vpsrld, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_128_wig, .avx },
......@@ -1242,6 +1297,8 @@ pub const table = [_]Entry{
12421297 .{ .vpunpckldq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x62 }, 0, .vex_128_wig, .avx },
12431298 .{ .vpunpcklqdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6c }, 0, .vex_128_wig, .avx },
12441299
1300 .{ .vpxor, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xef }, 0, .vex_128_wig, .avx },
1301
12451302 .{ .vroundpd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x09 }, 0, .vex_128_wig, .avx },
12461303 .{ .vroundpd, .rmi, &.{ .ymm, .ymm_m256, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x09 }, 0, .vex_256_wig, .avx },
12471304
......@@ -1278,6 +1335,12 @@ pub const table = [_]Entry{
12781335
12791336 .{ .vsubss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5c }, 0, .vex_lig_wig, .avx },
12801337
1338 .{ .vxorpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x57 }, 0, .vex_128_wig, .avx },
1339 .{ .vxorpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x57 }, 0, .vex_256_wig, .avx },
1340
1341 .{ .vxorps, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x0f, 0x57 }, 0, .vex_128_wig, .avx },
1342 .{ .vxorps, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x0f, 0x57 }, 0, .vex_256_wig, .avx },
1343
12811344 // F16C
12821345 .{ .vcvtph2ps, .rm, &.{ .xmm, .xmm_m64 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_128_w0, .f16c },
12831346 .{ .vcvtph2ps, .rm, &.{ .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x13 }, 0, .vex_256_w0, .f16c },
......@@ -1313,6 +1376,12 @@ pub const table = [_]Entry{
13131376 .{ .vbroadcastss, .rm, &.{ .ymm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x18 }, 0, .vex_256_w0, .avx2 },
13141377 .{ .vbroadcastsd, .rm, &.{ .ymm, .xmm }, &.{ 0x66, 0x0f, 0x38, 0x19 }, 0, .vex_256_w0, .avx2 },
13151378
1379 .{ .vpand, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xdb }, 0, .vex_256_wig, .avx2 },
1380
1381 .{ .vpandn, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xdf }, 0, .vex_256_wig, .avx2 },
1382
1383 .{ .vpor, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xeb }, 0, .vex_256_wig, .avx2 },
1384
13161385 .{ .vpsrlw, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd1 }, 0, .vex_256_wig, .avx2 },
13171386 .{ .vpsrlw, .vmi, &.{ .ymm, .ymm, .imm8 }, &.{ 0x66, 0x0f, 0x71 }, 2, .vex_256_wig, .avx2 },
13181387 .{ .vpsrld, .rvm, &.{ .ymm, .ymm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd2 }, 0, .vex_256_wig, .avx2 },
......@@ -1329,5 +1398,7 @@ pub const table = [_]Entry{
13291398 .{ .vpunpcklwd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x61 }, 0, .vex_256_wig, .avx2 },
13301399 .{ .vpunpckldq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x62 }, 0, .vex_256_wig, .avx2 },
13311400 .{ .vpunpcklqdq, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x6c }, 0, .vex_256_wig, .avx2 },
1401
1402 .{ .vpxor, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0xef }, 0, .vex_256_wig, .avx2 },
13321403};
13331404// zig fmt: on
src/type.zig+11-1
......@@ -5433,8 +5433,18 @@ pub const Type = extern union {
54335433 }
54345434 }
54355435
5436 // Works for vectors and vectors of integers.
5437 pub fn maxInt(ty: Type, arena: Allocator, target: Target) !Value {
5438 const scalar = try maxIntScalar(ty.scalarType(), arena, target);
5439 if (ty.zigTypeTag() == .Vector and scalar.tag() != .the_only_possible_value) {
5440 return Value.Tag.repeated.create(arena, scalar);
5441 } else {
5442 return scalar;
5443 }
5444 }
5445
54365446 /// Asserts that self.zigTypeTag() == .Int.
5437 pub fn maxInt(self: Type, arena: Allocator, target: Target) !Value {
5447 pub fn maxIntScalar(self: Type, arena: Allocator, target: Target) !Value {
54385448 assert(self.zigTypeTag() == .Int);
54395449 const info = self.intInfo(target);
54405450
test/behavior/floatop.zig-1
......@@ -532,7 +532,6 @@ fn testFabs() !void {
532532
533533test "@fabs with vectors" {
534534 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
535 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
536535 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
537536 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
538537 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
test/behavior/math.zig-1
......@@ -1612,7 +1612,6 @@ test "absFloat" {
16121612 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
16131613 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
16141614 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1615 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
16161615 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
16171616 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
16181617
test/behavior/translate_c_macros.zig-1
......@@ -65,7 +65,6 @@ test "cast negative integer to pointer" {
6565
6666test "casting to union with a macro" {
6767 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
68 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
6968 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
7069 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
7170 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO